Flip-Flop Circuit

The present invention relates to flip-flop circuits and, more particularly, to flip-flop circuits constructed by use of a current switching type logic.

At present, a current switching type latch circuit is predominantly used as a basic circuit of a high speed flip-flop circuit. In view of requirement of a high speed operation, flip-flops of various types such as RS, JK and D types, are generally realized by applying various feedbacks to the current switching type circuits, as basic circuits. In designing various logic circuits including sequential logic circuits, there is a case where a flip-flop circuit in a certain portion of the logic circuit is not used as a flip-flop and the clock input is directly applied to the logic circuit, at the following stage to which the output of the flip-flop is applied. Particularly in the frequency divider, such a method is often used for varying the frequency dividing ratio. In this case, the output of the flip-flop circuit and the clock input to the flip-flop are switched by means of a gate circuit controlled by another control input signal, for supplying it to the succeeding stage logic circuit.

Thus, the above-mentioned method needs an additional current flow into the gate circuit for such a purpose, so that power consumption is increased and a delay time is elongated, due to a delay time of the gate circuit.

Accordingly, an object of the present invention is to provide a flip-flop circuit in which an optional one of a latched output and a clock input is readily obtained at its output, with no increase of power consumption and delay time.

According to the present invention, there is a flip-flop circuit comprising first and a second transistors whose bases and collectors are cross-coupled at first and a second nodes. Third and a fourth transistors have collecters which are coupled to the first and second nodes to form a current switching circuit. First switching means are connected in parallel with the collector and the emitter of the first transistor. Second switching means are connected to the collector and emitter of the fourth transistor, wherein the first and the second switching means are controlled by the same control signal.

According to another aspect of the present invention, a semiconductor logic circuit includes a flip-flop. A first current switching circuit with a pair of output points is commonly used with the flip-flop. A second current switching circuit complementally switches the flip-flop and the first current switching circuit. A first transistor has a collector coupled to one of the output points and an emitter coupled to commonly coupled emitters of the flip-flop. A second transistor has a collector coupled to the other of the output points and an emitter coupled to commonly coupled emitters of the first current switching circuit. A control signal is supplied to bases of the first and second transistors.

According to the present invention, a circuit comprises a first node, a second node, a third node, a fourth node, a first and a second transistor having first parts and control parts cross-coupled at the first and the second nodes and second parts commonly coupled to the third node. A third transistor has a first part coupled to the first node and a second part coupled to the fourth node. A fourth transistor has a first part coupled to the second node and a second part coupled to the fourth node. At least one of the third and fourth transistors receives a first signal at its control part. Responsive to a second signal the third node and the fourth node are selectively coupled to the constant current source means. First switching means are coupled between the second node and the third node and second switching means are coupled between the first node and the fourth node. The first and second switching means are simultaneously controlled by a control signal.

In the above circuit, the first to fourth transistors may be bipolar transistors having collectors as their first parts, bases as their control parts and emitters as their second parts.

Furthermore in the above circuit, the first to fourth transistors may be insulated-gate field-effect transistors having drains as their first parts, gates as their control parts and sources as their second parts.

According to the invention, a circuit comprises a plurality of stages of master-slave flip-flops including a master flip-flop and a slave-flip-flop, the master flip-flop including a first and a second node. First and second transistors have collectors and bases cross-coupled at the first and second nodes. A third transistor has a collector coupled to the first node. A fourth transistor is coupled to the second node. A first means is responsive to a first control signal for selectively enabling one pair of the first and second transistors and third and fourth transistors. The slave flip-flop includes a third and a fourth nodes. Fifth and sixth transistors have collectors and bases cross-coupled at the third and fourth nodes. Seventh and eighth transistors have collectors respectively coupled to the third and fourth nodes. Second means are responsive to a second control signal having a complementary relation to the first control signal for selectively enabling one pair of the fifth and sixth transistors and the seventh and eighth transistor. The second node is coupled to a base of the seventh transistor. The circuit further includes in at least one of the slave flip-flop first switching means for selectively coupling the fourth node and an emitter of the sixth transistor. Second switching means are selectively coupled to the third node and to an emitter of the seventh transistor. The first and second switch means are simultaneously switched to conductivity.

The invention will be better understood upon the following description in connection with the accompanying drawings, in which:

FIG. 1 shows a circuit diagram of a conventional flip-flop circuit;

FIG. 2 shows a circuit diagram of a first embodiment of a flip-flop according to the invention;

FIG. 3 shows a block diagram of a frequency dividing circuit to which the present invention is applied;

FIG. 4 shows a circuit diagram of a flip-flop circuit of a second embodiment according to the invention;

FIG. 5 shows a circuit diagram of a delay type flip-flop shown in FIG. 3; and

FIG. 6 shows a set of timing diagrams which are useful in explaining the operation of the frequency divider shown in FIG. 3.

Referring first to FIG. 1, there is shown a conventional flip-flop circuit which is known to those skilled in this field. In operation, a data input applied to an input terminal V.sub.D1 is sampled by turning on a transistor Q.sub.5 when a clock input V.sub.C1 is in a high level. When it is in a low level, its state is held by turning on a transistor Q.sub.6. Through the operation, an output Z.sub.1 has a logical output with the same phase as the phase of the input signal applied to the input V.sub.D2 and an output Z.sub.1 has a logical output which is in opposite phase as compared with the phase of the input. While reference voltages necessary for logic operation are applied to terminals V.sub.R1 and V.sub.R2 in general. In some cases, complementary signals, with respect to the input signal and the clock signal, may be applied thereto in place of V.sub.R1 and V.sub.R2 whereby the flip-flop circuit is operated in a balanced type.

This type flip-flop circuit functions merely as a sequential circuit and it is not possible to obtain an output in the form of data-through whenever the input signal or the clock signal is required.

An embodiment of a flip-flop circuit according to the invention will be described with reference to FIG. 2. In the circuit, transistors Q.sub.7 and Q.sub.12 coupled respectively in parallel with transistors Q.sub.8 andQ.sub.11, are newly added components and the bases of the transistors Q.sub.7 and Q.sub.12 are commonly connected to a terminal V.sub.M for switching.

For simplicity of explanation, it is assumed that the bases of the transistors Q.sub.11 and Q.sub.14 are supplied with intermediate potentials of the input side logic levels as reference potentials V.sub.R3 and V.sub.R4, respectively. When a potential level at the terminal V.sub.M is logically low, the transistors Q.sub.7 and Q.sub.12 are cut-off irrespective of the logical states of a data input V.sub.D2 and a clock input V.sub.C2. The circuit operates as an ordinary current switching type latch circuit, similar to the operation of the circuit shown in FIG. 1. To be more specific, when the clock input V.sub.C2 is in a high level, the data input V.sub.D2 is written thereinto and the data thus written is held when the clock input V.sub.C2 is in a low level.

Let us consider a case where the level at the terminal V.sub.M is high. When the clock V.sub.C2 is high, the transistor Q.sub.7 is ON, so that current flows through a resistor R.sub.3 while no current flows into a resistor R.sub.4, and the output Z.sub.2 is high the clock signal V.sub.C2 is also high. When the clock V.sub.C2 is low, only the transistor Q.sub.12 is ON, currents flow through the resistor R.sub.4 and the output Z.sub.2 is low, as the clock signal V.sub.C2 is low. Therefore, the output Z.sub.2 always has the same waveforms as that of the clock V.sub.C2. In accordance with the content of data input V.sub.D2 and with an immediately previous state, it may happen that the current flowing through the transistors Q.sub.8 or Q.sub.10 is shunted into the transistors Q.sub.8 or Q.sub.10. In such a case, however, because of the common connection of the collectors of those transistors, the flowing currents are always constant due to the use of a constant current source I2. The signal levels at the outputs Z.sub.2 and Z.sub.2 are not affected. Thus, with this arrangement, by switching the control input V.sub.M, an optional one of the outputs of a latch circuit is obtained due to the data of V.sub.D2 and clock of V.sub.C2. The output has a waveform of the clock V.sub.C2 as it is obtained at the output Z.sub.2. Further, since the circuit current is determined by only the constant current source I2, a power consumed by the embodiment is increased a little, as compared to the circuit shown in FIG. 1. With respect to a delay time of the circuit, since the collector capacitances of the transistors Q.sub.7 and Q.sub.12 are merely added to the outputs Z.sub.2 and Z.sub.2, the addition of the capacitances hardly effects the gate delay time.

As seen from the foregoing description, the flip-flop circuit according to the invention is constructed by merely adding a slight number of components and a control terminal to the conventional current switching type latch circuit. With such a simple construction, by controlling the control terminal, the proper output of the conventional latch circuit or a waveform which is the same as the waveform of the clock input may be optionally obtained, with no increase of either power consumption or delay time. Therefore, the flip-flop circuit according to the invention is advantageously applied to construct an integrated logic circuit including a sequential circuit.

One of the applications of the flip-flop circuit according to the invention is a frequency divider operating at high frequencies. In order to divide a high frequency, it is usual that toggle flip-flops or D-flip-flops are constructed by applying proper feedbacks to a master flip-flop and a slave flip-flop, which use the latch circuits shown in FIG. 1. Those circuits are combined to produce outputs of a predetermined frequency dividing ratio. In this case, if the circuit of the invention is used as a latch circuit of the slave in a specific flip-flop, various and variable frequency dividing ratios may be readily obtained.

A frequency divider is realized by the flip-flop circuits according to the invention and will be described with reference to FIG. 3 through FIG. 6. A frequency dividing circuit shown in FIG. 3 receives a clock pulse CP to divide the clock pulse CP by frequency dividing ratios of 1/10 to 1/44. Toggle flip-flops TF1 and TF2 use flip-flops according to the invention, each with a frequency dividing ratio of 1/2. By controlling signal levels at terminals M.sub.1 and M.sub.2, input signals applied to clock input terminals C and C may be output to the outputs Q and Q, as they are. In this case, the frequency dividing ratios of the flip-flops TF1 and TF2 are respectively 1. Therefore, an output of the clock pulse CP frequency-divided by one of the three frequency-dividing ratios 1, 1/2 and 1/4 is obtained on the output lines Q.sub.2 and Q.sub.2. The output lines Q.sub.2 and Q.sub.2 are coupled with a variable counter section 20 comprising delay (D) flip-flops DF1 to DF4 connected in a cascade fashion. Either the frequency-divider ratio 1/10 or 1/11 is selectable by controlling a signal level at the terminal M.sub.3. Therefore, the frequency divider shown in FIG. 3 has six frequency dividing ratios, as shown in Table 1, when signal levels at the terminals M.sub.1, M.sub.2 and M.sub.3 are properly set.

In Table 1, the combinations of Nos. 3 and 5, and 4 and 8 provide same frequency dividing ratios, respectively. In the circuit shown in FIG. 3, a terminal INZ is connected to terminals Z of the respective flip-flops and is used to set the respective flip-flops to between initial states, before the circuit starts to count.

FIG. 4 shows a circuit construction of the toggle flip-flops TF1 and TF2 employing flip-flops according to the invention in FIG. 3. As shown, transistors Q.sub.15 to Q.sub.19, Q.sub.26, Q.sub.27 and Q.sub.30 cooperatively form a master flip-flop and a complementary phase of output at a node N.sub.10 of a slave flip-flop. According to the invention, the slave flip-flop includes transistors Q.sub.20 of Q.sub.25, Q.sub.28, Q.sub.29, and Q.sub.31. The complementary phase is fed back to the base of the logic input transistor Q.sub.16. The transistors Q.sub.30 and Q.sub.31 are biased by a bias voltage V.sub.CCV and operate as constant current sources.

In the slave flip-flop, the bases of transistors Q.sub.20 and Q.sub.24 are connected to the terminal M in accordance with the invention. The transistors Q.sub.20 and Q.sub.24 are both nonconductive when the terminal M is in a low (logic "0") level, so that the flip-flop is in a normal operating condition. When the terminal M is in a high (logic"1") level, both of the transistors Q.sub.20 and Q.sub.24 produce output signals at output points N.sub.10 and N.sub.20 which correspond to true and complementary signals applied to terminals C and C. The output levels at the output points N.sub.10 and N.sub.20 are applied to the output terminals Q and Q, through emitter-follower transistors Q.sub.32 and Q.sub.33, respectively. Incidentally, a reference voltage may be applied to the bases of the transistors Q.sub.27 and Q.sub.29 without applying the complementary signal thereto.

Turning now to FIG. 5, there is shown a circuit diagram of the delay flip-flops DF1 to DF4 in the counter 20 shown in FIG. 3. In FIG. 5, transistors Q.sub.34 to Q.sub.38, Q.sub.43, Q.sub.44 and Q.sub.47 cooperatively form a master flip-flop. Transistors Q.sub.39 to Q.sub.42, Q.sub.45, Q.sub.46 and Q.sub.48 similarly form a slave flip-flop. The input terminal D of the delay flip-flops is connected to the base of the transistors Q.sub.35. True and complementary control signals are supplied to the terminals C and C. The transistors Q.sub.47 and Q.sub.48 are biased by the voltage V.sub.CCV and constitute constant current sources. Incidentally, in the delay flip-flop DF4, the output Q is fed back to the input terminal D. As mentioned above, a reference voltage may be applied to the bases of the transistors Q.sub.44 and Q.sub.46 without the provision of the terminal C.

The operation of the circuit shown in FIG. 3 will be described with reference to FIG. 6. For simplicity, it is assumed that a rectangular waveform of the clock pulse CP is applied to the circuit and waveforms at the respective portions of the circuit shown in FIG. 3 are designated by corresponding reference symbols. Those flip-flops TF.sub.1 and TF.sub.2, and DF1 to DF4 are all arranged in a master-slave fashion in which the master flip-flop is in a gate condition at the trailing edge of the input pulse CP (clock pulse) which is to be divided. The slave flip-flop is in a gate condition at the leading edge of the input pulse, so that the output thereof changes. Under such a condition, the input pulse (clock pulse CP) is kept at a high level and the master flip-flop is held. The slave flip-flop is in the gate condition. If the terminal INZ is in a high level, the flip-flops are all set to high level, so that these flip-flops are forcibly set to the initial state. Although the waveforms in FIG. 6 are shown in the case of the frequency ratios 44 (.div. 44) and 40 (.div.40) where terminals <M.sub.1, M.sub.2 and M.sub.3 > are respectively kept logic ("0", "0", and "0") and ("0", "0", and "1"), the same thing is true for other cases, if the outputs of the toggle flip-flops TF1 and TF2 are considered to be the input pulses.

The above-mentioned embodiments use NPN type transistors, of a type which is now predominantly used in the integrated circuit. It is evident that PNP type transistors or insulated-gate field effect transistors may also be used similarly in the invention.