Dual-Fet Sample and Hold Circuit

This invention is an improved sample-and-hold circuit.

A sample-and-hold circuit is commonly used to "hold" at its output for a predetermined time the voltage that was applied to its input during a short "sampling" period, usually during that time immediately prior to the holding period. Commonly, a variable voltage is applied to the input, a pulse is applied to initiate a sampling period, and the output will continue for some period to output the input voltage level that existed at the time of the pulse. A problem inherent in this type of circuit is that the sampling pulse is coupled through to the output line, which impairs the accuracy of the circuit. More specifically, in an uncompensated sample-and-hold circuit, during the sampling period the output voltage is an accurate representation of the input voltage, but, at the end of that period, the trailing edge of the sampling pulse is coupled through the gate-to-drain capacitance to the output, resulting in a dc offset or "hold step". This is especially true in high speed circuits. A complex and necessarily expensive circuit could be designed to minimize this effect. What is required is a simple circuit that would accomplish this result.

The described circuit accomplishes this objective by using an FET which, when closed, acts as a switch to charge up a capacitor during the sampling period. At the end of the sampling period, this FET opens, and the value stored at the output capacitor is then available as the circuit output. However, the sampling pulse, applied to the FET gate, is also coupled through to the capacitor and appears as a low amplitude dc offset on the output line.

To compensate for this, a second FET is provided. This one also is coupled to the output line, and receives the sampling pulse at its gate. However, it is biased so that it never turns on. The result is that this FET does not interfere with the operation of the first FET, but the sampling pulse is coupled through this FET to the output line. By using a sampling pulse for the second FET opposite in polarity but identical in timing to the first, the two pulses will cancel at the mutual output line. The result is a simple sample-and-hold circuit which can operate with accuracy at high speeds.

FIG. 1 is a simplified equivalent drawing of the circuit.

FIG. 2 is a schematic diagram of the circuit.

FIG. 3 is a schematic diagram of a multiplexing sample-and-hold circuit.

The equivalent circuit of FIG. 1 operates to hold an instantaneous voltage supplied by any voltage source 1 at the time of two input sampling pulses applied to the input lines 15, 16 at the output 9.

This instantaneous input voltage is applied to the first FET 2 at its source 20. The FET 2 is shown in its equivalent form, with a capacitance 3 coupling source 20 and gate 24, and also with a capacitance 4 coupling the gate 24 and drain 21. The series resistance 5 is shown as a resistor and the operation of the FET is approximated by the switch 6.

During the sampling period, the input pulse at the gate 24 closes the switch 6, allowing the output capacitor 8 to follow the input voltage supplied by the voltage source 1. At the end of the sampling pulse, the switch 6 opens, and the output capacitor 8 maintains its charge to produce the output voltage.

In addition to this sampled voltage, the pulse, applied at input 16 is coupled through the gate-to-drain capacitance 4, and also appears on the output line 9 as a noise pulse and hold step.

To compensate, a second FET 10 is provided. This FET has the identical structure, a source 22 to gate 25 capacitance 11, a gate 25 to drain 23 capacitance 14, a series resistance 12 and a series switch 13. However, a bias is applied at the input 15 so that the FET is always open, and therefore this FET 10 is not in the charge path of the output capacitor 8. However, a pulse of opposite polarity to the one applied to input 16 is applied to input 15 and is coupled to the output line 9.

The outputs of both circuits are tied at point 7 which acts as a summing junction, cancelling the pulses. Thus, at the output 9, the sampled voltage is available but the coupled-through pulses are cancelled out.

The actual circuit is shown in FIG. 2. A variable voltage from a signal input 1 is applied at FET 2 through the series resistance 5 to the source 20. During the sampling time a pulse is also supplied from the gate input 26 through any suitable amplifier 27 to the gate 24. The FET turns on, allowing the output capacitor 8 to charge.

The output of amplifier 27 is inverted in a second amplifier 28 and applied through a resistance network comprising three resistors 29,30,31 to the gate 25 of a second FET 10. The resistance network 29,30,31 is coupled to a voltage selected so that the second FET 10 will never turn on. However, the pulse at the gate 25 is coupled through the capacitance of the FET 10 to the FET 2 source 22 and drain 23 and from there to point 7 where the pulses coupled through both FETs are cancelled.

The resistive network 29,30,31 may be variable to allow the adjustment of the biasing voltage and the amplitude of the pulse applied to the FET 10 gate 25 to exactly cancel the pulses at point 7.

For the specific case where two or more input voltages must be multiplexed, the sample-and-hold multiplexing circuit of FIG. 3 may be used. The details of FIG. 2 apply except that there are two switching FETs 40,41 in addition to the compensating FET 10. It is assumed that the two input voltage sources 42 and 43 are independent, that the sampling pulses S1 and S2 are not present simultaneously, and that a compensating pulse S occurs for each S1 and S2 pulse. It is also assumed that the gate of the compensating FET is biased negatively as in FIG. 2 so that it remains off.

A further difference is that all FET drains in FIGS. 2 and 3 are connected, but that while the sources 20, 22 are connected in FIG. 2, the sources 44,45 are coupled through the voltage inputs 42,43 to ground, and source 46 is directly grounded.

The sample-and-hold multiplexer of FIG. 3 may be converted to a conventional multiplexer by replacing capacitor 8 with a resistor 50, shown connected to the output by dotted lines. In an uncompensated multiplexer, the sampling pulse coupled through the FET 40 capacitances to the output line will result in a noise pulse on the output line, as compared to a dc level error in an equivalent sample-and-hold circuit. In this case, compensating FET 10 operates identically to cancel the pulse at the output line.

Another embodiment of a two-channel multiplexer or sample-and-hold multiplexer is created by using the entire circuit of FIG. 2, except for capacitor 8, for each of the two channels. The output lines are connected to each other and to either a resistor or capacitor to implement a multiplexer or sample-and-hold circuit, respectively. In this case, each compensating FET 10 is connected to its corresponding switching FET 2 at both drain and source, to allow a better matching of capacitances and a better cancelling of the hold step or noise pulse.

The invention is not limited to any of the embodiments described above, but all changes and modifications thereof not constituting departures from the spirit and scope of the invention are intended to be covered by the following claims: