Automatic Gain Control Circuit

The invention relates to electrical circuit arrangements. One example of an electrical circuit arrangement to which the invention relates is an automatic gain control (AGC) circuit arrangement.

Various AGC circuit arrangements are known. However, a problem which can arise with known AGC circuit arrangements is that their bandwidth varies with gain and thus with the level of output signal for a given input. Where a wide loop bandwidth is required (e.g. to handle amplitude modulation up to 20 KHz or more), this variation of bandwidth can give rise to instability.

An object of the invention is an improved automatic gain control circuit arrangement.

A more specific object of the invention is an automatic gain control circuit arrangement having a bandwidth which is not unduly affected by the level of the input signal.

According to the invention, there is provided an automatic gain control circuit arrangement for producing an output signal which is dependent on an input signal and whose mean level has a desired value, comprising a signal path having an input for receiving the input signal and an output at which is produced the output signal, the signal path including control means controllable to vary the level of the signal in the signal path and amplifying means for amplifying the signal in the signal path, the circuit arrangement also including detecting means connected to sense the level of the signal in the signal path after its level has been varied by the control means and amplified by the amplifying means, and operative in response to variations of the sensed level from the desired value to produce a control signal dependent on the variations and which adjusts the control means in a sense such that it offsets the said variations, the control means comprising one part primarily responsive to the alternating component of the control signal and another part primarily responsive to the D.C. component of the control signal whereby changes in the gain of the amplifying means or in the level of the input signal which tend to alter the upper limit of the loop bandwidth of the circuit arrangement are substantially offset by the effect of the resultant change in the gain of the said other part of the control means.

According to the invention, there is also provided an automatic gain control circuit arrangement, comprising means for receiving an input signal, first modulating means connected to modulate the level of the input signal, second modulating means connected to modulate the output of the first modulating means, an amplifier for amplifying the output of the second modulating means and for applying it to an output terminal, a detector for detecting the level of the output of the amplifier, means operative to compare the detected level with a reference dependent on a desired value of the mean level of the signal produced at the output terminal whereby to produce a control signal dependent on the difference between the actual level of the output of the amplifier and the said desired value, the first and second frequency-dependent impedance paths of applying the control signal to the first and second modulating means respectively, one impedance path having an impedance which decreases with increasing frequency and the other impedance path having an impedance which increases with increasing frequency, whereby one modulating means performs modulation primarily dependent on the value of the alternating component of the control signal and the other modulating means performs modulation primarily dependent on the D.C. component of the control signal, so that the upper limit of the bandwidth of the circuit arrangement is substantially unaffected by changes in the gain of the amplifier or in the mean level of the input signal.

AGC circuit arrangements embodying the invention will now be described by way of example only and with reference to the accompanying diagrammatic drawings in which:

FIG. 1 is a circuit diagram of one of the AGC circuit arrangements;

FIG. 2 is a Bode plot of the circuit arrangement of FIG. 1;

FIG. 3 is a circuit diagram of another of the AGC circuit arrangements; and

FIG. 4 is a circuit diagram of a further one of the AGC circuit arrangements.

In the following description, direct voltage signal components or constant amplitude signals are represented by upper case "V", together with a distinguishing subscript, while varying amplitude components of such direct current or constant amplitude signals are represented by a lower case "v" together with a distinguishing subscript.

The AGC circuit arrangement (FIG. 1) has an input terminal 5 at which is received the input signal S.sub.i =V.sub.i +v.sub.i. The signal is passed to one terminal of a first modulator 6 which receives a modulating signal S.sub.c1 on a second input line 7. The output V.sub.6 of the modulator 6 is passed to the first input of a second modulator 8 which receives a modulating signal S.sub.c2 on a second input line 12.

The output V.sub.8 of the second modulator 8 is passed through an amplifier 14 having an output line 16. The level of the signal V.sub.o on the line 16 is sensed by a detector 18 which produces a resultant output on a line 20 which is applied through a resistor R2 to a point 23. Also applied to the point 23 is a reference signal S.sub.r via a terminal 30 and a resistor R3. Therefore, the integrator input receives the algebraic sum of the signals applied to the point 23 through the resistors R2 and R3. Integrator 28 has an integrating capacitor C1 connected across it.

The output S.sub.c of the integrator 28 provides the modulating signals S.sub.c1 and S.sub.c2 for the modulators 6 and 8. The signal S.sub.c1 is produced via a capacitor C2 which is shunted by a resistor R4 connected to a bias supply (not shown) by a terminal 32. The signal S.sub.c2 is produced via a resistor R5 which is shunted to ground by a capacitor C3. The result, therefore, is that the modulator 6 is responsive only to the alternating components of the signal S.sub.c, while the modulator 8 is responsive only to the D.C. and low frequency components of the signal S.sub.c.

The output signal, V.sub.o, of the circuit arrangement is taken from a terminal 36 connected to the line 16 from the amplifier 14.

The AGC circuit of FIG. 1 will now be analysed. In the analysis which follows, the following terms will be used (in addition to those mentioned above):

gain of amplifier 14 is A.sub.1 ;

gain of the detector 18 is A.sub.2 ;

(where V.sub.c1 is the bias voltage applied via resistor R.sub.4);

the gain of modulator 6 (v.sub.6 /v.sub.i)=A.sub.3 ;

the gain of modulator 8 (v.sub.8 /v.sub.6)=A.sub.4 ; and

the values of the capacitors and resistors are taken to be represented by the references identifying them in FIG. 1.

Considering modulator 6,

but A.sub.3 =K.sub.1 .multidot.V.sub.c1 where K.sub.1 is the transfer characteristic of the modulator.

Therefore, ##EQU1## This assumes V.sub.i is constant (v.sub.i =0).

Considering modulator 8, by analogy with Equation (1),

where K.sub.2 is the transfer characteristic of modulator 8.

But this assumes V.sub.6 is constant and is the variation due to V.sub.c2. With V.sub.c2 constant (v.sub.c2 =0) and V.sub.6 varying,

Therefore, combining Equations (2) and (3),

Now, ##EQU2## Initially, it has been assumed that V.sub.i is constant. Therefore v.sub.i =0. Under these conditions (and assuming V.sub.r is constant, v.sub.r =0), the total loop gain G.sub.1 is ##EQU3## Substituting from Equations (1), (4) (6) and (7) into Equations (8), and assuming that C.sub.2 =C.sub.3 =C and R.sub.4 =R.sub.5 =R, ##EQU4##

FIG. 2 shows a Bode plot (loop gain against the logarithm of angular frequency) of Equation (9) where the angular frequencies .omega..sub.o, .omega..sub.1 and .omega..sub.3 correspond respectively to the time constants T.sub.o, T.sub.1 and T.sub.3 defined above. .omega..sub.2 is the angular frequency at the upper end of the frequency band of the circuit.

By geometry from FIG. 2,

Therefore,

Thus,

Substituting from Equations (10), (11) and (12) in Equations (13), ##EQU5##

Equation (14) therefore shows the factors which affect .omega..sub.2 that is, the factors which affect the upper limit of the bandwidth of the circuit. These factors are A.sub.1, A.sub.2, A.sub.4, K.sub.1 and V.sub.i.

The operation of the circuit arrangement will be considered assuming that it is desired to keep V.sub.o constant, and that this will be done by keeping V.sub.r constant.

If, now, there is an increase in A.sub.1, then, due to the D.C. feedback through the modulator 8, A.sub.4 will be reduced so as to hold V.sub.o constant. Therefore, for a given V.sub.o, A.sub.1.A.sub.4 is constant.

If now there is an increase in V.sub.i, then again, due to the D.C. feedback path through modulator 8, A.sub.4 will be reduced to keep V.sub.o constant. Therefore, for a given V.sub.o, A.sub.4.V.sub.i is constant.

Therefore, summarising, for a given V.sub.o, A.sub.1.A.sub.4.V.sub.i is constant.

In addition, A.sub.2, the gain of the detector 18, must be constant (otherwise, the circuit arrangement will not be able to maintain V.sub.o constant).

Therefore, for a given V.sub.o,

For small values of control signal v.sub.c1, the factor K.sub.1 for the modulator 6 should be constant.

Therefore, overall, .omega..sub.2 is constant.

The foregoing assumes that V.sub.o is constant. However it may be desired to operate the circuit arrangement so that V.sub.o varies (by a controlled amount). This may be done by varying the reference signal V.sub.r. However, a change in V.sub.r will produce a change (in the opposite sense) in V.sub.o. This is achieved by the variation of A.sub.4 by means of the signal V.sub.c2. Therefore, Equation (15) no longer applies, and thus .omega..sub.2 is not constant if V.sub.o varies.

However, Equation (15) shows that if A.sub.2 can be made inversely proportional to V.sub.o, then A.sub.2 .multidot.A.sub.4 will be constant as V.sub.o varies. In such a case, ##EQU7## will be constant for all values of V.sub.o, and so, therefore, will .omega..sub.2.

FIG. 3 shows the circuit arrangement of FIG. 1 modified in order to ensure that A.sub.2 is inversely proportional to V.sub.o. In the circuit of FIG. 3, the output of detector 18 is now fed through a resistor R.sub.1 to ground, and an adjustable tapping on this resistor is fed through a buffer amplifier 40 to the resistor R.sub.2. In this circuit, therefore, the gain A.sub.2 now becomes the overall gain of the sub-circuit comprising the detector 18, the resistor R.sub.1 and the buffer amplifier 40. In operation, the reference V.sub.r is held constant (even when it is desired to vary V.sub.o), and in order to change V.sub.o, adjustments are made to the position of the tapping on the resistor R.sub.1 so as to alter the value of A.sub.2. Thus, a reduction in A.sub.2 increases V.sub.o by producing a resultant increase in A.sub.4 (via the control signal V.sub.c2).

Therefore, with the circuit arrangement of FIG. 3, .omega..sub.2 remains substantially constant for all values of V.sub.o (as well as for changes in the value of A.sub.1 and V.sub.i).

In the circuit arrangements shown in FIGS. 1 and 3, a problem can arise at very low modulation frequency. Under these conditions, the impedance in the path for the signal V.sub.c1 becomes significant and v.sub.c1 tends to zero and the signal V.sub.c2 becomes effectively equal to V.sub.c. Therefore, the modulator 8 must be capable of applying all the necessary modulation. For high levels of pulse modulation at these low frequencies, modulator 8 becomes overloaded and ineffective principally because the circuit limits the rate at which V.sub.c2 can increase by charging capacitor C.sub.3.

FIG. 4 shows a modification to the circuit arrangement of FIG. 3 (but which can also be applied to the circuit arrangement of FIG. 1) in order to deal with this problem. The modification consists in the provision of by-pass circuits in series with the control inputs of the modulators 6 and 8, together with two additional resistors R.sub.6, R.sub.7. The by-pass circuits are provided by diodes D.sub.1, D.sub.2 and D.sub.3. Diode D.sub.3 is connected to the junction between the D.sub.1 and D.sub.2 which are respectively directly connected to the inputs of the modulators 6 and 8.

Normally, all these diodes are non-conducting.

However, at very low frequencies where C.sub.3 prevents V.sub.c2 from changing sufficiently rapidly, the diodes D.sub.2 and D.sub.3 conduct therefore bypassing the effect of capacitor C.sub.3.

The mathematical analysis given above is in simplified form because it ignores the interaction between the modulators at the crossover frequency (i.e. the frequency where one modulator ceases to be effective and the other begins to become effective). However, this does not have any practical affect on the analysis at other frequencies and does not affect the constancy which the circuit arrangement gives to .omega..sub.2 as explained above.