(B+a)-Bit D/a Converter With B-Bit Auxiliary D/a Converter

A(1) Field of the invention

The invention relates to a digital-to-analog converter (D/A converter for short), for converting a digital signal consisting of a sequence of code words each comprising a plurality of bits into an analog signal.

A(2). Description of the prior art

D/A converters are used in mutually very different technical fields. Generally speaking they convert a digital signal, formed by a sequence of code words each comprising a certain number of bits and occurring at a certain sampling frequency f.sub.s into a time-continuous signal. To enable this conversion each code word is converted into a signal sample whose amplitude is proportional to said code words and constant during a sampling period T which is equal to 1/f.sub.s. This furnishes a staircase signal which is usually also applied to a low-pass filter at the output of which the desired analog signal occurs. Embodiments of D/A converters are shown in reference 1. Many D/A converters are implemented from a plurality of resistors through which accurately defined currents flow. The number of currents required for decoding a code word is at least equal to the number of bits of which this code word consists. If these code words have been obtained by encoding a speech signal they usually do not comprise more than 12 bits. If, however, they are obtained by encoding a music signal and hi-fi quality is required after decoding then they comprise, for example, 16 bits. The more bits a code word comprises the more accurate the resistors and the currents must be and the higher the complexity and the price of such a D/A converter. This price inhibits the use of these D/A converters in, for example, audio equipment such as magnetophones, for the consumer's market.

Hereinafter a code word consisting of, for example, d bits will be denoted by "d-bit code word". In a similar manner a D/A converter arranged for decoding a d-bit code word will be denoted by "d-bit D/A converter".

It is an object of the invention to provide a digital-to-analog converter which can be realized in an economically justified manner.

According to the invention the digital-to-analog converter for converting a digital signal formed by a sequence of code words each comprising b+a bits into an analog signal comprises:

(a) a converter input for receiving the digital signal and a converter output;

(b) integration and amplitude-limiting means for generating a digital auxiliary signal which is an amplitude-limited version of the integrated signal applied to these means;

(c) first coupling means for coupling the input of the integration and amplitude-limiting means to the converter input;

(d) quantizing means connected to said integration and amplitude-limiting means for limiting the word length of the code words of the digital auxiliary signal for generating a quantizing means output signal formed by a sequence of code words each comprising b bits;

(e) difference and amplitude-restoration means;

(f) second coupling means for coupling the input of the difference and amplitude-restoration means to the output of the quantizing means;

(g) third coupling means for coupling the output of the difference and amplitude-restoration means to the converter output;

(h) a b-bit auxiliary digital-to-analog converter which is included in the circuit formed by the second coupling means, the difference and amplitude-restoration means and the third coupling means.

With the digital-to-analog converter according to the invention, a (b+a)-bit D/A conversion is realized using, in general, a cheaper and simpler b-bit auxiliary D/A converter. In order to obtain a signal-to-quantizing noise ratio associated with a (b+a)-bit-D/A-converter, a pre-processing operation is performed on the digital input signal before applying this signal to the quantizing means. A post-processing operation is thereafter performed on the output signal of the quantizing means. This post-processing operation shifts the quantizing noise signal introduced by the quantizing means to such a frequency band that it can be suppressed by a filter circuit. The pre-processing circuit has for its object to realize said suppression of the noise signal without affecting the desired signal.

FIG. 1 shows schematically the power spectrum of an analog signal;

FIG. 2 shows also schematically one period of the power spectrum of a digital signal having associated therewith a sampling frequency which is equal to the Nyquist frequency;

FIG. 3 shows one period of the power spectrum of a digital signal and the noise signal power spectrum introduced by amplitude-quantization;

FIG. 4 shows the symbol for an interpolator;

FIG. 5 shows schematically one period of the power spectrum of the output signal of the interpolator shown in FIG. 4 if a signal having the power spectrum shown in FIG. 2 is applied thereto;

FIG. 6 shows one period of the power spectrum of a digital signal with which a sampling frequency is associated which is N=2 times higher than the Nyquist frequency, as well as the noise signal power spectrum introduced by amplitude quantization;

FIG. 7 shows schematically the general set-up of the digital-to-analog converter according to the invention;

FIG. 8 shows the variation of the function sin.sup.2 (2.pi.fT/2) occurring in expression (21);

FIG. 9 shows a variant of the digital-to-analog converter shown in FIG. 7;

FIG. 10 shows graphically the variation of a periodical amplitude-limiting function which is non-linear in each period;

FIG. 11 shows graphically the variation of a periodical amplitude-limiting function which is linear in each period;

FIG. 12 shows a simplification of the digital-to-analog converter shown in FIG. 9;

FIG. 13 shows an embodiment of the cascade arrangement of the integrating network and the auxiliary amplitude-limiter for use in the digital-to-analog converter of FIG. 9;

FIG. 14 shows an embodiment of a signal source circuit for use in the digital-to-analog converter of FIG. 9;

FIG. 15 shows an embodiment of a difference network;

FIG. 16 shows a so-called nested version of the digital-to-analog converter shown in FIG. 9.

1. Special Issue on Analog/Digital Conversion; IEEE Transactions on circuits and systems, Vol. CAS-25, No. 7, July 1978.

2. Digital Signal Processing; A. V. Oppenheim, R. W. Schafer; Prentice-Hall 1975, pages 413-418;

3. Dutch Patent Application No. 7703633, corresponding to U.S. Pat. No. 4,131,764;

4. Optimum FIR Digital Filter Implementations for Decimation, Interpolation and Narrow Band Filtering; L. R. Rabiner, R. E. Crochiere; IEEE Transactions on Acoustics Speech and Signal Processing, Vol. ASSP-23, October 1975, pages 444-456;

5. Further Considerations on the Design of Decimators and Interpolators; R. E. Crochiere, L. R. Rabiner; IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-24, August 1976, pages 296-311;

6. Computation Rate and Storage Estimation in Multirate Digital Filtering with Half-Band Filters; M. G. Bellanger; IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-25, August 1977, pages 344-346.

E(1.1) The power spectrum of a digital signal

A digital signal is a time and amplitude-discrete signal. Such a signal is, for example, obtained by sampling an analog signal x.sub.a (t) at instants nT, resulting in signal samples which will be denoted by x.sub.a (nT), by quantizing the signal samples thus obtained resulting in quantized signal samples x.sub.a (nT) and by converting them into a multi-bit number, called code-word hereinafter and denoted by x(n). Herein n represents an integer located in the interval -.infin.<n<.infin. and T represents the sampling period. The said digital signal is now formed by the sequence of code words x(n) and this signal will be denoted by {x(n)}. The quantity 1/T is sometimes called sampling frequency and will be denoted by f.sub.s.

If it is now assumed that each of the code words x(n) comprises b+a bits, these bits being indicated by c.sub.i (n), where i=0, 1, 2, . . . b+a-1, respectively, and which are either equal to 1 or to 0 then it holds that

or ##EQU1## In (1), V.sub.max represents the upper limit of the amplitude of the analog signal x.sub.a (t) so that it holds for x.sub.a (t) that:

In the preceding it was described that to enable the conversion of the analog signal x.sub.a (t) into the sequence of code-words x(n), this analog signal x.sub.a (t) must first be sampled at a rate f.sub.s. If now the frequency spectrum of x.sub.a (t) differs from zero only at the frequency-interval 0.ltoreq.f.ltoreq.f.sub.x then f.sub.s must be at least 2f.sub.x. By way of illustration FIG. 1 shows schematically the power spectrum P.sub.x.sbsb.a (f) of x.sub.a (t) and FIG. 2 shows, also schematically, one period of the power spectrum P.sub.x (f) of the digital signal {x(n)}.

It is now useful to investigate how the power spectrum looks like of a digital signal {z(n)} obtained by reducing the word length of each of the code-words x(n) to b bits, for example, by rounding. To effect this a non-linear quantizing operation Q[.] must be performed on each of the code words x(n) thus that z(n) can be written as

This quantizing operation can also be described in a different manner, it namely also holds that

In this expression e(n) represents the quantizing error, it holding for this error that:

These quantizing errors may be considered as being code-words of a digital noise signal {e(n)} having a power density spectrum which is uniformly distributed of a frequency interval 0.ltoreq.f.ltoreq.f.sub.s. Consequently, this noise signal may be considered as "white noise" (see reference 2). If the total noise power of this noise signal is denoted by P.sub.e then it holds that

This noise power will now distribute itself uniformly over the frequency interval 0.ltoreq.f.ltoreq.f.sub.s. FIG. 3 shows all this for one period of the power spectrum of the signal {z(n)}.

As FIG. 3 shows not only the original signal having the power spectrum P.sub.x (f) but also a noise signal having a power spectrum P.sub.e (f) for which it holds that:

is present in the frequency interval 0.ltoreq.f.ltoreq.2f.sub.x.

E(1.2) Sampling frequency and quantizing noise

In paragraph E(1.1) it is described that, if the word length of each of the code-words x(n) is reduced from b+a bits to b bits a noise signal is then introduced having the power density spectrum P.sub.e (f). As mentioned hereinbefore it holds that: T=1/f.sub.s. In other words, P.sub.e (f) is directly proportional to the sampling period T or inversely proportional to the sampling frequency. This means that if we would be able to increase the sampling frequency f.sub.s =2f.sub.x which is associated with {x(n)}' by a factor of N, so that a digital signal {x'(n)} is obtained with which a sampling frequency f'.sub.s =Nf.sub.s is associated, the power density spectrum P'.sub.e (f) of the digital noise signal {e(n)}, obtained by quantizing each code-word x'(n) in the above described manner, would be given by

The above-mentioned increase of the sampling frequency by a factor of N can now be achieved by means of an arrangement which inserts each time N code words having the value zero between two consecutive code-words x(n) and x(n-1) and, possibly, a digital filter in cascade therewith. Such an arrangement is described in reference 3 where it is called SRI element. A digital low-pass filter can be used as the digital filter. The cascade arrangement of this SRI element and this digital filter is sometimes called interpolator, it will be denoted by means of the symbol shown in FIG. 4. In this symbol N represents the increase factor. References 4, 5 and 6 describe embodiments of such an interpolator.

If now more particularly the digital signal {x(n)} having the power spectrum shown in FIG. 2 is applied to the interpolator shown in FIG. 4 then this interpolator produces a digital signal {x'(n)} having a power spectrum P.sub.x '(f) the shape of which for N=2 is schematically shown in FIG. 5. If this digital signal {x'(n)} is now subjected to the quantizing operation mentioned in paragraph E(1.1) then a digital signal is obtained having a power spectrum schematically shown in FIG. 6. Of the noise signal introduced by this quantizing operation the frequency component located in the frequency interval f.sub.x .ltoreq.f.ltoreq.(2N-1)f.sub.x can now be suppressed by means of a digital low-pass filter, so that a noise signal is left having a total power equal to P.sub.e /N.

E(2) The arrangement according to the invention

This paragraph describes and explains the general set-up of a digital-to-analog converter, shown in FIG. 7, for converting a digital signal {x(n)} formed by a sequence of (b+a)-bit code-words x(n) into an analog signal x(t) with the use of a b-bit auxiliary-digital-to-analog converter which is considerably cheaper than a (b+a)-bit-D/A-converter.

The D/A converter shown in FIG. 7 comprises a b-bit auxiliary D/A converter 1 which is implemented in a conventional manner. This auxiliary D/A converter 1 comprises a digital signal input 1 and an analog signal output 3. If a digital signal {z(n)} is applied to this auxiliary D/A converter, this converter produces signal samples z.sub.a (nT) for which it holds that

In (9) e'(n)V.sub.max represents a sample of an amplitude-limited error signal occurring from inaccuracies in the auxiliary D/A converter.

The input 2 of this auxiliary D/A converter is connected through a quantizing device 10 to the output of a pre-processing device 4 to which a digital signal {x'(n)} consisting of the (b+a)-bit code-words x'(n) is applied. It will be assumed that this digital signal {x'(n)} occurs at the output of the interpolator 13 to which a digital signal {x(n)} is applied with which a sampling frequency 2f.sub.x is associated and has the power spectrum schematically shown in FIG. 2. A sampling frequency 2Nf.sub.x is thus associated with {x'(n)} and this digital signal has the power spectrum shown in FIG. 5 for N=2.

The output of the auxiliary D/A converter is connected to the input of a post-processing device 5 which has its output connected to the input of a low-pass filter 6 which applies the desired analog signal x(t) to its output 7.

The pre-processing device 4 comprises an integrating network 8 and an amplitude-limiting device 9 having a limiting function f[.]. The integrating network 8 can be in the form of an accumulator and produces, in response to the code-words x'(n) applied thereto, the code-words y(n) for which it holds that: ##EQU2## These code-words are applied to the amplitude-limiting device 9 which produces the code-words y(n) for which it holds that:

These code-words y(n), consisting of b+a bits are now applied to the quantizing device which, in response thereto, produces the b-bit code-words z(n) with

This quantizing device 10 can be implemented so that it applies the b most significant bits of y(n) to the b-bit-auxiliary D/A converter 1. If y(n) is given in 2-complement, this form of quantizing is known as "value truncation" (see reference 2).

The post-processing device 5 comprises an amplitude restoration device 11 and a difference network 12. The amplitude-restoration device 11 has an amplitude-restoration function g[.] and, in response to the signal samples z.sub.a (nT) applied thereto, it produces the signal samples z.sub.a (nT) for which it holds that

For an accurate restoration of the amplitude it must hold that g[.] is inverse to f[.]. Generally speaking this means for a variable .alpha. that:

(13) can now be written:

so that

These signal samples z.sub.a (nT) are now applied to the difference network 12, which is assumed to be of the first order. This difference network 12 produces the output signal samples z.sub.a (nT) for which it holds that

so that

With (10) it follows therefrom that

If now the cut-off frequency of the low-pass filter is taken equal to 1/(2NT), the analog signal x(t) can be obtained from the signal samples z.sub.a (nT). If this low-pass filter is assumed to be an ideal filter then it holds more particularly that: ##EQU3##

The noise signal r(n) present in the signal z.sub.a (nT) and produced by, inter alia, quantizing device 10 has a power spectrum which will be denoted by P.sub.r (f) and which has a constant value. The use of a difference network 12 so affects this power spectrum that the noise power is shifted to the frequency interval f.sub.x <f<(2N-1)f.sub.x. This can be explained as follows. If the noise signal in z.sub.a (nT) is represented by s(nT), then it holds in accordance with (18) that:

If now the power spectrum of s(nT) is represented by P.sub.s (f) then it can be derived that:

FIG. 8 shows the variation of the function sin.sup.2 (2.pi.fT/2) as a function of f. As P.sub.r (f) is finite for all values of f, it appears from FIG. 8 that the introduced noise signal r(n), which has a power density which is uniform of the entire frequency band 0.ltoreq.f.ltoreq.f.sub.s, is suppressed in so far as it is located in the frequency intervals 0.ltoreq.f<f.sub.x and (2N-1)f.sub.x .ltoreq.f.ltoreq.2Nf.sub.x, so that the total noise power produced at the output of the ideal low-pass filter 6 and which will be indicated by P.sub.s is given by the expression: ##EQU4## If it is now a requirement for P.sub.s to be below a certain threshold value the value of N follows from (24).

E(3) The amplitude-limiting and restoration function

Only one special requirement was imposed in the foregoing on the amplitude-limiting function. Namely, this function is assumed to be invertable because otherwise no amplitude-restoration function can be found. That, however, not every invertable function can be used as amplitude-limiting function may appear from the following examples. Assuming that:

With (25) (10) changes into:

For an accurate restoration of the amplitude it must now hold that:

With (27) (13) changes into:

From (26) and (28) it follows that if e(n)+e'(n)=0 it indeed holds, as intended, that:

As, however, e(n)+e'(n) is unequal to zero, this relationship is seriously disturbed.

A very advantageous amplitude-limiting function is obtained by periodically repeating a function which is defined in a certain interval and varies monotously in this interval and which is invertable. That interval and, consequently, also said period must be chosen suitably. Hereinafter this period will be denoted by R. A possible amplitude-limiting function is now given by

In (30) k.sub.n represents an integral and positive number and indicates the ordinal number of the interval, having a length R wherein y(n) is located. The value of R must now be chosen so that the relation:

is satisfied.

As the signal samples z.sub.a (nT) produced at the output of the amplitude-restoration device 11 must satisfy (16), it can be derived that it must hold for the amplitude-restoration function that

where with:

By assuming that

(32) change into

Herewith it follows, in the general sense from (17) that

Since the amplitude of each of the code-words x(n) and x'(n) is limited, the amplitude of each signal sample z.sub.a (nT) is also limited, in accordance with (18). This means that although k.sub.n and k.sub.n-1 are in principle unlimited the difference k.sub.n -k.sub.n-1 represents a finite number.

As furthermore z.sub.a (nT) can never exceed V.sub.max it holds, if the period R is chosen greater than or equal to 2, that then: ##EQU5##

As indicated in (34), k.sub.n -k.sub.n-1 can assume one out of three possible values. This is related with the fact that y(n) can be both greater and smaller than y(n-31 1). Should, however, x(n) always be positive, then y(n) would increase monotously. In that case k.sub.n -k.sub.n-1 can only be 0 or +1. Starting from the assumption that:

and that R>2 then it holds that: ##EQU6## In addition the foregoing means that z.sub.a (nT) can be fully determined from the difference z'.sub.a (nT)-z'.sub.a [(n-1)T]. If, namely,

then

and

If, on the contrary:

then

and

E(4) Special embodiments

FIG. 9 shows schematically a modification of the arrangement shown in FIG. 7, the modification being obtained by choosing the amplitude-limiting function, defined in expression (30), in accordance with the expression:

For the amplitude-restoration function indicated in expression (32) it must now hold that:

It should be noted that the constant .eta. in the expressions (30) and (32) is chosen equal to unity. For the period R a value must now be chosen so that (31) is satisfied, so that it must hold that:

This is satisfied by

The relationship defined in expression (39) between y(n) and y(n) is graphically shown in FIG. 10, the period R having been taken in accordance with (42).

From (33) and (40) it now follows that:

Because R exceeds 2, expression (34) holds for k.sub.n -k.sub.n-1.

The arrangement shown in FIG. 9 is implemented to a very great extent in the same manner as the arrangement shown in FIG. 7. In this FIG. 9 elements corresponding to those in FIG. 7 have been given the same reference numerals as in FIG. 7.

As shown in FIG. 9 the amplitude-limiting device 9 is now formed by a cascade arrangement of two auxiliary limiters 14 and 15. The auxiliary limiter 14 produces a digital residual signal {y(n)} as well as the digital number k.sub.n -k.sub.n-1. For the relationship between the input signal {y(n)} and the output signal {y(n)} of the auxiliary limiter 14 it holds that:

This signal {y(n)} is now applied to the auxiliary limiter 15 which produces the signal {y(n)} for which it holds that:

The number k.sub.n -k.sub.n-1 produced by the auxiliary limiter 14 is applied to a signal source circuit 16 to which also a reference signal RV.sub.max is applied and which produces an output signal the value of which is equal to (k.sub.n-k.sub.n-1)RV.sub.max.

For the generation of the signal samples z.sub.a (nT) defined in expression (43) the amplitude restoration device 11 is now formed by a cascade arrangement of an auxiliary restorer 17 and an adding device 18. The difference network 12 is now arranged between the output of the auxiliary restorer 17 and the input of the adding device 18. The signal samples z.sub.a (nT) produced by the auxiliary-D/A-converter 1 are now applied to the auxiliary restorer 17, which in response thereto produces the signal samples z'.sub.a (nT) for which it holds that:

These signal samples z'.sub.a (nT) are now applied to the difference network 12 which in response thereto produces signal samples of the shape z'.sub.a (nT)-z'.sub.a [(n-1)T] which are applied to the adding device 18 to which also the signal value (k.sub.n -k.sub.n-1)RV.sub.max is applied. So the signal samples z.sub.a (nT) defined in (43) are produced at the output of this adding device and again applied to the low-pass filter 6.

In the embodiment shown in FIG. 9, the amplitude-limiting device 9 is formed by two auxiliary limiters 14 and 15 and the amplitude-restoration device by an auxiliary restorer 17 and an adding device 18. It is indeed possible to realize the auxiliary limiter 14 in a simple and economic manner (see paragraph E(5)), but implementing the auxiliary limiter 15 and the auxiliary restorer 17 is not always simple and economically feasible. However, this auxiliary limiter 15 and auxiliary restorer 17 can each be formed by means of a direct through-connection; namely if the amplitude-limiting function defined by the expression (30) is given by:

For .eta.=1 R can be chosen equal to 2 so that:

The relationship between y(n) and y(n), given in (48) is shown graphically in FIG. 11. As expression (48) is of the same form as expression (44), FIG. 11 shows more generally the relationship between y(n)/(R/2) and y(n)/(R/2) by means of a graph.

Associated with the amplitude-limiting function as defined in (48) is, in accordance with (32), an amplitude-restoration function which must be defined as follows:

so that:

FIG. 12 shows an embodiment based on the amplitude-limiting function defined in (48) and on the amplitude-restoration function defined in (49). For this embodiment it is further assumed that the signal applied to the integrating network 8 is always positive, so that the expressions (36), (37), (38) given in paragraph E(3) still hold. This arrangement of FIG. 12 differs from the arrangement shown in FIG. 9 in the following respects:

1. The pre-processing device 4 now does not produce numbers k.sub.n -k.sub.n-1 so that the signal source circuit 16 shown in FIG. 9 is no longer present in this arrangement of FIG. 12. The auxiliary limiter 15 is now formed by a direct through-connection.

2. The post-processing device 5 now comprises an auxiliary restorer 17 formed by a direct through-connection. In addition a polarity detector 19 is present which has its input connected to the output of the difference network 12. This polarity detector now produces, for example, a positive voltage of a certain reference level if the signal occurring at the output of the difference network 12 is positive. If, however, said signal is negative this polarity detector produces a negative voltage of a certain reference level. The output voltages of this polarity detector control a switch 20, shown symbolically only in the Figure, through which a reference voltage having a value of 0 Volt is applied to the adding device 18 each time the polarity detector produces a positive voltage, and a reference voltage of 2 V.sub.max Volts being applied to the adding device 18 via this switch each time polarity detector produces a negative voltage.

3. In order to ensure that the signal applied to the integrating network 8 is always positive for any random input signal {x(n)} for which it holds that -1.ltoreq.x(n).ltoreq.+1 the pre-processing device comprises an adding device 21 to which the digital signal {x'(n)} as well as a constant having the value +1 are applied. Thus, there occur at the output of this adding device the code words x(n) for which it holds that:

with -1<x'(n)<+1 so that x(n) is always positive.

E(5) Detailed embodiments of some components

E(5.1) The accumulator 8 and the auxiliary limiter 14

FIG. 13 shows in greater detail an embodiment of the cascade arrangement of the integrating network 8 and the auxiliary limiter 14 used in the arrangement shown in FIG. 9. Hereinafter the sign bit of a code-word .phi. will be denoted by sign (.phi.) and it will be assumed that:

when .phi..gtoreq.0

when .phi.<0

The embodiment shown in FIG. 13 of the above-mentioned cascade arrangement is formed by an adder 22 to which the (b+a)-bit code words x'(n) are applied through a first input and the code-words y(n-1) through a second input. This adder 22 is now arranged so that it produces code-words y'(n) for which it holds that: y'(n)=x(n)+y(n-1) and which have one bit more than x'(n). More particularly it holds that the most significant bit in x'(n) has the value 2.sup.-1, whereas the most significant bit in y'(n) has the value 2.sup.0. This code word y'(n) is now further applied to a second adder 23 to which also a (b+a+1)-bit auxiliary number .gamma. is applied and this sum number is now the desired number y(n). This number y(n) is not only applied to the auxiliary limiter 15 (see FIG. 9) but also to a delay device 25 having a time delay T/N. The output of the delay device 25 is connected to the second input of the adder 22.

The storage device 24 contains three numbers in base-2-code namely the numbers:

which are each stored in a certain addressable storage location of this storage device. Through an address decoder 24' these storage locations are addressable by the sign bit sign [y'(n)] and the most significant bit of y'(n). If this most significant bit is represented by y'.sub.0 then the storage device 24 produces more particularly the number: ##EQU7##

The cascade arrangement of the integrating network 8 and the auxiliary limiter 14 can be considerably simpler if this cascade arrangement is used in the arrangement shown in FIG. 12. As x(n) is always positive, so that k.sub.n need not be determined, the function of this cascade arrangement can be performed by a (b+a)-bit accumulator.

E(5.2) The signal source circuit

FIG. 14 shows a detailed embodiment of the signal source circuit 16, which is suitable for use in the arrangement shown in FIG. 9 and in conjunction with the embodiment shown in FIG. 13 of the cascade arrangement of integrating network 8 and auxiliary limiter 14. The signal source circuit shown in FIG. 14 comprises two switches 26 and 27, which are shown symbolically only. The switch 26 is controlled by the sign bit sign [y'(n)] of y'(n) and the switch 27 is controlled by the most significant bit y'.sub.0 of y'(n). In addition, this signal source circuit comprises an output 28 which, in the arrangement of FIG. 9, is connected to an input of the adder 18.

The signal source circuit operates as follows: when y'.sub.0 =0 then the output 28 is connected to ground through the switch 27 and a voltage of 0 Volt is thus supplied to this output. If y'.sub.0 =1 then the output 28 is connected to the output of the switch 26 through the switch 27, a voltage of +RV.sub.max being applied to this output when sign [y'(n)]=0, a voltage of -RV.sub.max being applied to this output when sign [y'(n)]=1.

E(5.3) The difference network

FIG. 15 shows an embodiment of the difference network 12. This network comprises a differential amplifier 29 a first input of which is directly connected to the input 30 of the difference network to which the signal samples z'.sub.a (nT) are applied. The second input of the differential amplifier 29 is also connected to the input 30, namely through a sample and hold circuit. In the Figure the sampling circuit is shown symbolically by the switch 31 and the hold circuit is shown symbolically by the capacitor 32. Sampling pulses are applied to the switch 31 with a frequency 2Nf.sub.x and the instant at which the n.sup.th sampling pulse occurs is just prior to the moment z'.sub.a (nT) changes into z'.sub.a [(n+1)T].

E(6) Final remarks

1. In special circumstances it may be preferred to structure the difference network 12 in a different manner then shown in FIG. 15, namely by means of digital circuit components. In order to enable the use of such a difference network the D/A converter 1 must be arranged somewhere between the output of the difference network 12 and the output of the filter 6. If now more particularly this D/A converter 1 is connected to the output of the adder 18 then the elements 17, 12, 18 and 16 of the arrangement shown in FIG. 9 can all be implemented in digital techniques; the elements 12, 18, 19 and 20 of the arrangement shown in FIG. 12 can then be implemented in digital techniques.

2. In practice it appeared that, instead of a difference network it is alternatively possible to use a differentiating network, for example a simple RC-network in the post-processing device. It will be assumed that the term difference network also comprises the notion differentiating network.

3. For the arrangements described in the foregoing it appeared that for a certain value of N the quantizing device 10 may suppress only a certain number of bits of the code words y(n); for example not more than three. This means that if x(n) is a 16-bit code-word a 13-bit D/A converter must then be used which may, however, still be relatively expensive. It is however, possible to suppress more bits than the above-mentioned three bits, the value of N remaining equal without a deterioration of the signal quantizing noise. This can be achieved with any one of the above-described arrangements, namely by "nesting" such an arrangement in known manner. For example, nesting the arrangement shown in FIG. 9 results in the arrangement shown in FIG. 16. In this arrangement shown in FIG. 16 the digital signal {x'(n)}, produced by the interpolator is applied to the quantizing device 10 through a cascade arrangement of M pre-processing devices 4(1), 4(2), . . . 4(M). The output signal samples z.sub.a (nT) produced by the auxiliary D/A converter 1 are applied in their turn to the output filter 6 via a cascade arrangement of also M post-processing devices 5(1), 5(2), . . . 5(M). In the arrangement shown in FIG. 16 M is equal to three. The three pre-processing devices 4(1), 4(2) and 4(3) are each implemented in the same manner as the pre-processing device shown in FIG. 9. Also each of the three post-processing devices 5(1), 5(2), 5(3) are implemented in the same manner as the post-processing device shown in FIG. 9.

4. In the embodiments shown the interpolator 13 is assumed to be constituted by a so-called SRI-element followed by a digital filter (see paragraph E(1.2)). However, in practice it appears that this digital filter is not a requirement; this is more particularly the case shown in the embodiment of FIG. 12. If an increase in the sampling frequency of the digital input signal is deemed necessary, a SRI-element might then be sufficient.

5. Each of the shown embodiments comprises an output filter 6. However, such a filter can be dispensed with in many applications.