Astable MOS FET Multivibrator

BACKGROUND OF THE INVENTION

This invention relates to a Schmitt trigger astable MOS FET multivibrator circuit.

When an amplifier is constructed by serially connecting an even number of CMOS FET type inverters with the output terminal of the last stage inverter connected to the input terminal of the first stage inverter, and the input voltage varies at a level close to the threshold voltage of the inverter, the output signal changes between the logic levels "0" and "1". This effect can be particularly troublesome for astable multivibrators. To suppress such erroneous behavior caused by noise, it is considered necessary to give the above-mentioned amplifier a hysteresis characteristic, thereby changing the logic level of inverted threshold voltage in a case where the input voltage has its logic level varied from high to low or vice versa.

FIG. 1 shows an input-output characteristic of the above-mentioned amplifier to illustrate the hysteresis characteristic thereof. V.sub.in denotes an input voltage, and V.sub.out shows an output voltage. V.sub.THH indicates the threshold voltage of the amplifier where the input voltage V.sub.in has its logic level changed from "0" to "1". V.sub.THL represents the trheshold voltage of the amplifier where the input voltage V.sub.in has its logic level changed from "1" to "0". The larger the difference between these threshold voltages V.sub.THH and V.sub.THL, the smaller the effect of noises included in the input voltage V.sub.in. An amplifier having the above-mentioned hysteresis characteristic is referred to as "a Schmitt trigger circuit."

FIG. 2 shows an arrangement of a prior art Schmitt trigger circuit which includes three series-connected inverters 1, 2, 3 and P-and N-channel MOS FETs 4 and 5 connected in parallel between the output terminals of the first and third inverters 1 and 3. An input signal supplied to the inverter 1 is also applied to the gates of MOS FETs 4 and 5.

There will now be described the case where the input voltage V.sub.in is increased from a logic level of "0" to that of "1". When the input voltage V.sub.in rises slightly higher than the threshold voltage V.sub.THH, then an output voltage V.sub.1 from the inverter 1 falls slightly from the threshold voltage V.sub.THL of the inverter 2. This voltage change is amplified by the inverters 2 and 3. Accordingly, an output voltage V.sub.out from the amplifier gets slightly lower than the output voltage V.sub.1 from the inverter 1. At this time, considerably high back gate bias voltage is impressed on the MOS FETs 4 and 5, which appreciably increase their effective resistance in response. Consequently, the N-channel MOS FET 4 is not rendered operative, unless the output voltage V.sub.out from the amplifier falls considerably. Accordingly, a decline occurs in the voltage of a signal fed back from the output terminal of the inverter 3 to the input terminal of the inverter 2, causing the output voltage V.sub.1 from the inverter 1 to make a very gentle fall.

Where the input voltage V.sub.in has its logic level changed from "1" to "0", then the output voltage V.sub.1 from the inverter 1 rises very slowly. It is seen, therefore, that the prior art Schmitt trigger circuit of FIG. 2 has a speed limitations, which, if used in an astable multivibrator, would limit the upper frequency of the multivibrator.

It is accordingly the object of this invention to provide a Schmitt trigger astable multivibrators circuit which is free from the effect of back gate bias voltage and can be operated at a high speed.

According to an aspect of this invention, there is provided an astable multivibrator circuit which comprises first and second power supply terminals; a second inverter whose input terminal is connected to the output terminal of the first inverter; a third inverter including an inverter section formed of a MOS circuit whose input and output terminals are respectively connected to the output and input terminals of the second inverter, and MOS elements which are connected to both terminals of the conduction path of the MOS between the first and second power supply terminals and whose gates are jointly connected to the input terminal of the first inverter; a time constant circuit for supplying a signal to the input of the first inverter; and switching means for activating the time constant circuit in response to an ouptut signal from the second inverter and for permitting a signal having a prescribed frequency to be produced from the time constant circuit to the first inverter.

FIG. 1 shows the input-output characteristic of the prior art Schmitt trigger circuit;

FIG. 2 indicates the arrangement of the prior art Schmitt trigger circuit;

FIG. 3 sets forth the arrangement of a Schmitt trigger circuit according to one embodiment of this invention;

FIG. 4 shows the arrangement of a Schmitt trigger circuit according to another embodiment of the invention;

FIG. 5 presents the arrangement of an astable multivibrator according to still another embodiment of the invention;

FIG. 6 illustrates the waveform of an input signal supplied to the astable multivibrator of FIG. 5;

FIG. 7 indicates the waveform of an output signal from the multivibrator;

FIG. 8 is a modification of the bistable multivibrator of FIG. 5;

FIG. 9 sets forth the arrangement of an astable multivibrator according to still another embodiment of the invention;

FIG. 10 indicates the arrangement of a monostable multivibrator according to a further embodiment of the invention;

FIGS. 11 to 13 give the waveforms of signals to illustrate the operation of the monostable multivibrator of FIG. 10;

FIG. 14 is a modification of the monostable multivibrator of FIG. 10; and

FIG. 15 shows the arrangement of a monostable multivibrator according to a still further embodiment of the invention.

There will now be described a Schmitt trigger astable multivibrator circuit embodying this invention by reference to the accompanying drawings.

A Schmitt trigger circuit of FIG. 3 embodying this invention includes an inverter 11 formed of, for example, a CMOS FET element and supplied with input voltage V.sub.in, an inverter 12 for inverting an output signal from the inverter 11, and an inverter 13 for inverting an output signal from the inverter 12 and feeding the resultant output signal back to the input terminal of the inverter 12.

The inverter 13 includes N- and P-channel MOS FETs 14 and 15 whose gates are jointly connected to the output terminal of the inverter 12, an N-channel MOS FET 16 connected between the source of the N-channel MOS FET 14 and ground, and a P-channel MOS FET 17 connected between the drain of the P-channel MOS FET 15 and a power supply terminal V.sub.DD. The MOS FETs 16 and 17 are rendered conductive or nonconductive according to the logic level of input terminal V.sub.in supplied to the gates thereof. Output voltage V.sub.out from the Schmitt trigger circuit of FIG. 3 is drawn out of the output terminal of the inverter 13.

There will now be described the case where input voltage V.sub.in supplied to the Schmitt trigger circuit of FIG. 3 has its logic level changed from "0" to "1". At this time, the N-channel MOS FET of the inverter 11 is biased to be rendered conductive, and gradually decreases in effective resistance. The MOS FET 16 of the inverter 13 is biased for conductive state and the MOS FET 17 thereof is biased to nonconductive state.

While the input voltage V.sub.in does not exceed the threshold voltage V.sub.THH of the Schmitt trigger circuit, the inverter 12 generates an output voltage having a logic level of "0". Therefore, the MOS FET 15 is kept conductive and the MOS FET 14 remains nonconductive.

Output voltage from the inverter 13, that is, output voltage V.sub.out from the Schmitt trigger circuit is kept at a V.sub.DD level or a logic level of "1". When the input voltage V.sub.in reaches the threshold voltage V.sub.THH, then the N-channel MOS FET of the inverter 11 is rendered conductive.

At this time, output voltage V.sub.1 from the inverter 11 which is defined by a ratio between the effective resistance of the N-channel MOS FET and the effective resistance of the series connected MOS FETs 15 and 17 of the inverter 13 becomes equal to the threshold voltage of the inverter 12. As the result, the logic level of output voltage from the inverter 12 is changed from "0" to "1", causing the MOS FET 14 to be rendered conductive and the MOS FET 15 to be rendered nonconductive. Since, at this time, the MOS FET 16 is already rendered conductive, no appreciable difference arises between the source potential of the MOS FET 14 and the substrate potential. Therefore, the MOS FET 14 is little impressed with back gate bias voltage, and output voltage from the inverter 13 sharply falls.

Since, output voltage from the inverter 13 is directly impressed on the input terminal of the inverter 12, output voltage from this inverter 12 rapidly rises, and output voltage from the inverter 13 sharply falls. Also, where the input voltage V.sub.in falls from a logic level of "1" to "0", the inverters 11, 12 and 13 operate substantially in the same manner as described above, causing output voltage from the Schmitt trigger circuit of FIG. 3 to fall sharply.

In the Schmitt trigger circuit of FIG. 3 when, the mutual conductance of the MOS FETs 14 and 16 of the inverter 13 is made larger than that of the P-channel MOS FET and the mutual conductance of the MOF FETs 15 and 16 of the inverter 13 is similarly made larger than that of the N-channel MOS FET, then it is possible to provide a wide difference between the threshold voltages V.sub.THH and V.sub.THL of the Schmitt trigger circuit of FIG. 3.

FIG. 4 shows the arrangement of a Schmitt trigger circuit according to another embodiment of this invention. This Schmitt trigger circuit is not provided with the inverter 11 but instead with a control circuit 21 for receiving an input signal V.sub.in and control signal V.sub.x. The Schmitt trigger circuit further includes an N-channel MOS FET 22 connected between the MOS FETs 14 and 16 and a P-channel MOS FET 23 connected in parallel with the MOS FET 17. In other respects, the embodiment of FIG. 4 has substantially the same arrangement as that of FIG. 3. The conduction state of MOS FETs 22 and 23 is controlled by the logic level of a control signal V.sub.x supplied to the gates of the MOS FETs 22 and 23.

The control circuit 21 includes P-channel MOS FET 24 and N-channel MOS FET 25 whose gates are supplied with an input signal V.sub.in and whose conduction paths are connected in series; P-channel MOS FET 26 is connected in parallel with the MOS FET 24 and N-channel MOS FET 27 is connected between the source of the MOS FET 25 and ground. A control signal Y.sub.x is supplied to the gates of the MOS FETs 26 and 27.

In this case, it should be noted that the effective resistance of the MOS FETs 22, 23, 26, 27 gradually varies with the voltage level of the control signal V.sub.x. For example, where the control signal V.sub.x is made to have the highest voltage level, then the MOS FETs 23 and 26 prominently rise in effective resistance, thus rendering the arrangement of FIG. 4 equivalent to that of FIG. 3. When the voltage of the control signal V.sub.x is reduced from the highest level, then the MOS FETs 23 and 26 decrease in effective resistance, and the MOS FETs 22 and 27 increase in effective resistance.

Where, therefore, the logic level of the input voltage V.sub.in changes from "0" to "1", then the output voltage from the control circuit 21, which is defined by a ratio between a sum of the effective resistance of the parallel connected MOS FETs 17 and 23 and the effective resistance of the MOS FET 15 on the one hand, and the effective resistance of the series-connected MOS FETs 25 and 27 on the other, increases over the case when the control voltage is made to have the highest level.

Conversely, where the logic level of the input voltage V.sub.in changes from "1" to "0", then the output voltage from the control circuit 21, which is defined by a ratio between the effective resistance of the parallel connected MOS FETs 24 and 26 and the effective resistance of the series connected MOS FETs 14, 22 and 16, decreases from the case where the control voltage is set at the highest level. Namely, the lower the control voltage V.sub.x, the higher the threshold voltages V.sub.THH and V.sub.THL of the Schmitt trigger circuit of FIG. 4.

FIG. 5 indicates the arrangement of an astable multivibrator circuit according to another embodiment of this invention, which is constructed by connecting an input circuit section 30 to the Schmitt trigger circuit of FIG. 3. This input circuit section 30 includes parallel-connected capacitor C.sub.1 and resistor R.sub.1 to constitute a CR time constant circuit, and a P-channel MOS FET element 31 which is connected between the power supply terminal V.sub.DD and the junction of the capacitor C.sub.1 and the resistor R.sub.1. The gate of element 31 is supplied with an output signal from the inverter 12 of the Schmitt trigger circuit section.

There will now be described the operation of the astable multivibrator of FIG. 5 by reference to FIG. 6 showing the waveform of a input signal V.sub.in supplied to the Schmitt trigger circuit section, as well as to FIG. 7, illustrating the waveform of an output signal V.sub.out from the Schmitt trigger circuit section.

Assume now that the logic level of the input voltage V.sub.in has been changed from "1" to "0". Then the MOS FET 17 is rendered conductive and the MOS FET 16 becomes nonconductive. Therefore, the inverter 12 produces an output signal having a logic level of "0", causing the MOS FET 14 to be rendered nonconductive and the MOS FETs 15 and 31 conductive. Accordingly, the output voltage V.sub.out from the Schmitt trigger circuit rises as illustrated in FIG. 7.

The capacitor C1 is gradually charged through the MOS FET 31 which is now rendered conductive, causing the input voltage V.sub.in slowly to rise as shown in FIG. 6. When the input voltage V.sub.in reaches the threshold voltage V.sub.THH of the Schmitt trigger circuit section, i.e., has a logic level of "1", then the MOS FET 16 is rendered conductive, and the MOS FET 17 is turned off.

At this time, the inverter 12 has a logic level of "1", causing the MOS FET 14 to be rendered conductive and the MOS FETs 15 and 31 to be rendered nonconductive. Output voltage V.sub.out from the Schmitt trigger circuit section falls to a logic level of "0", as indicated in FIG. 7. Electric energy charged in the capacitor C.sub.2 is released through the resistor R.sub.1, causing the input voltage V.sub.in to decrease slowly as seen from FIG. 6.

Where the input voltage V.sub.in again has its logic level changed to "0", that is, it reaches the threshold voltage V.sub.THL of the Schmitt trigger circuit section, then the astable multivibrator is operated in the same manner as described above, issuing pulses having a constant pulse width as illustrated in FIG. 7.

With the astable multivibrator of FIG. r, assume that the effective resistance of the MOS FET 21 when rendered conductive is denoted by R.sub.ON, current running through the MOS FET by I.sub.1, and current conducted through the resistor R.sub.1 by R.sub.2. When, a voltage drop V.sub.2 occurring in the MOS FET 31 is expressed by the following equation:

The input voltage V.sub.in is expressed by the following equation: ##EQU1## Derived from the above equation (2) are the following equations: ##EQU2## Further assuming t=0 and V.sub.in =V.sub.THL, the following equation results: ##EQU3## Assuming R.sub.ON <R.sub.1, the above equation (5) may be rewritten as follows: ##EQU4##

The length sof time tr and tf required for the input voltage V.sub.in to rise and fall are respectively indicated by the following equations: ##EQU5##

The repetition rate at which the output signal V.sub.out is repeatedly generated, namely, the oscillation frequency f of the astable multivibrator of FIG. 5 is expressed by the following equation: ##EQU6##

As previously mentioned the threshold voltages V.sub.THL and V.sub.THH of the Schmitt trigger circuit section are defined by the MOS FETs constituting the Schmitt trigger circuit section. Therefore, the oscillation frequency f of the astable multivibrator can be determined by the resistor R.sub.1, capacitor C.sub.1 and the effective resistance of the MOS FET 31 when rendered conductive.

FIG. 8 shows a modification of the astable multivibrator of FIG. 5. This multivibrator has substantially the same arrangement as that of FIG. 5, except for an input circuit section 32 repacing the input circuit section 30 of FIG. 5. The input circuit section 32 includes a series circuit of a resistor R.sub.2 and capacitor C.sub.2 which jointly constitute a CR time constant circuit and are connected between the power supply terminal V.sub.DD and ground, and an N-channel MOS FET 33 which is connected in parallel with the capacitor C.sub.2 and whose gate is supplied with an output signal from the inverter 12. The astable multivibrator of FIG. 8 is operated in the same manner as that of FIG. 5, and produces an output voltage signal which has such a waveform as illustrated in FIG. 7.

FIG. 9 indicates the arrangement of an astable multivibrator according to still another embodiment of the invention, which is constructed by connecting an input circuit section 30 of the same arrangement as that used in the astable multivibrator of FIG. 5 to the input terminal of the Schmitt trigger circuit section of FIG. 4.

The astable multivibrator of FIG. 9 is operated theoretically in the same manner as that of FIG. 5. Since, as described in connection with FIG. 4, the threshold voltages V.sub.THH and V.sub.THL of the Schmitt trigger circuit section can be made to vary with the logic level of the control signal V.sub.x, the oscillation frequency of the astable multivibrator of FIG. 9 can be arranged by the logic level of the control signal V.sub.x.

FIG. 10 shows the arrangement of a monostable multivibrator according to still another embodiment of this invention, which is constructed by connecting an input circuit 40 to the input terminal of the Schmitt trigger circuit section of FIG. 3. The input circuit 40 includes a resistor R.sub.3 and capacitor R.sub.3 which are connected in series jointly to constitute a CR time constant circuit, and an N-channel MOS FET element 41 which is connected in parallel with the capacitor C.sub.3 and whose conduction state is controlled according to the logic level of an externally supplied signal. An output signal drawn out at the junction of the capacitor C.sub.3 and the resistor R.sub.3 is conducted to the inverter 11.

There will now be described the operation of the monostable multivibrator of FIG. 10 by reference to the waveforms of voltage signals illustrated in FIGS. 11 and 13. FIG. 11 shows the waveform of a voltage signal V.sub.g externally supplied to the gate of the MOS FET 41. FIG. 12 indicates the waveform of an input voltage signal V.sub.in supplied to the inverter 11. FIG. 13 sets forth the waveform of an output voltage signal V.sub.out from the monostable multivibrator of FIG. 10.

There will now be described the case where the gate voltage V.sub.g of the MOS FET 41 has a logic level of "0", and the MOS FET 41 remains nonconductive. Under this condition, the capacitor C.sub.3 is charged up to the source voltage V.sub.DD, causing the input voltage V.sub.in of the inverter 11 to be maintained at a level of V.sub.DD. When the gate voltage V.sub.g has its logic level changed to "1" and the MOS FET 41 is rendered conductive, then the electric energy stored in the capacitor C.sub.3 is discharged through the conduction path of the MOS FET 41. As the result, the input voltage V.sub.in falls to the ground potential as shown in FIG. 12. Where, in this case, the input voltage V.sub.in exceeds the threshold voltage V.sub.THL of the Schmitt trigger circuit section, then the inverters 11, 12 and 14 are put into operation and an output voltage signal V.sub.out from the Schmitt trigger circuit section sharply rises, as described in connection with the Schmitt trigger circuit of FIG. 3.

Thereafter, when the gate voltage V.sub.g has its logic level changed to "0" and the MOS FET 41 is rendered nonconductive, then the capacitor C.sub.3 is charged up to the source voltage V.sub.DD. Where the voltage caused by electric energy charged in the capacitor C.sub.3 rises above the threshold voltage V.sub.THH of the Schmitt trigger circuit section, then the inverters 11, 12 and 13 are put into operation, causing an output voltage V.sub.out sharply to fall.

Thus, an output voltage signal having such waveform as shown in FIG. 13 is produced relative to the gate voltage signal V.sub.g indicated in FIG. 11. The monostable multivibrator of FIG. 10 enables the pulse width of the output voltage signal to be properly controlled by setting the resistor R.sub.3 and capacitor C.sub.3 to have a suitable value.

FIG. 14 shows a modification of the monostable multivibrator of FIG. 10. The monostable multivibrator of FIG. 14 has substantially the same arrangement as that of FIG. 10, except for an input circuit section 42 replacing the input circuit section 40 of FIG. 10. The input circuit 42 includes a parallel connected resistor R.sub.4 and capacitor C.sub.4 jointly constituting a CR time constant circuit and a P-channel MOS FET element 43 connected between the parallel circuit of the resistor R.sub.4 and capacitor C.sub.4 and the power supply terminal V.sub.DD. The gate of the MOS FET 43 is externally supplied with a gate signal V.sub.g. The monostable multivibrator of FIG. 14 is operated in the same manner as that of FIG. 10 and produces an output voltage signal having such a waveform as shown in FIG. 13.

FIG. 15 presents the arrangement of a monostable multivibrator according to a further embodiment of this invention, which is constructed by connecting an input circuit section 40 of the same arrangement as that of the monostable multivibrator of FIG. 10 to the input terminal of the Schmitt trigger circuit of FIG. 4. The monostable multivibrator of FIG. 15 is operated theoretically in the same manner as that of FIG. 10. Since the threshold voltage V.sub.THH and V.sub.THL of the Schmitt trigger circuit section can be made to vary with the logic level of the control signal V.sub.x, the width of output pulses from the monostable multivibrator of FIG. 15 can be changed according to the logic level of the control signal.

There have been described the preferred embodiments of this invention. However, the invention is not limited thereto. For example, an odd number of series-connected inverters may be used with the Schmitt trigger circuit of FIGS. 3 and 4 in place of a single inverter 12. Further, the control circuit 21 of the Schmitt trigger circuit of FIG. 4 may be replaced by an inverter which supplies an inverted input signal V.sub.in to the inverter 12. Moreover, the MOS FETs 22 and 23 can be omitted from the Schmitt trigger circuit of FIG. 4. With the Schmitt trigger circuit of FIGS. 3 and 4, an output signal may be drawn out from the inverter 12 instead of from the inverter 13.