Digital Filter Bank Detector

This invention relates generally to electrical signal filtering apparatus and more particularly to a digital filter bank for processing IF signals developed in a radio receiver for recovering coded FSK data burst signals whose center frequency drift is large compared to their bandwidth.

Briefly, the subject invention is included in a frequency shift keying FSK radio receiver and comprises a digitally synthesized filter bank detector including a plurality of contiguous narrowband filters. Employed are means for implementing a signal conditioner, an envelope weighting computer, a Fourier transform processor and a post-detection processor. The signal conditioner is adapted to convert an IF signal to a sequence of multi-bit digital words at a relatively high sampling rate. The digital words or samples are then processed by the envelope weighting computer and the Fourier transform processor, in combination, to synthesize the digital filter bank. The envelope weighting computer establishes the filter shape, while the Fourier transform processor establishes the center frequency for the plurality of contiguous narrowband filters and computes the envelope amplitude of the samples at each frequency. The post-detection processor is adapted to provide clipping and threshold logic for each of the filters, search/track logic to identify a valid FSK filter pair and demodulation and data regeneration logic for regenerating the received message signals.

FIG. 1 is an electrical block diagram broadly illustrative of the preferred embodiment of the subject invention;

FIG. 2 is a diagram illustrative of a bank of 16 contiguous filters digitally synthesized by the subject invention;

FIG. 3 is an electrical block diagram illustrative of the signal conditioner portion of the digital filter bank detector shown in FIG. 1;

FIG. 4 is an electrical block diagram illustrative of the envelope weighting computer portion of the detector shown in FIG. 1;

FIG. 5 is an electrical block diagram illustrative of the Fourier transform processor portion of the detector shown in FIG. 1;

FIG. 6 is an electrical block diagram illustrative of the post-detection processor portion of the detector shown in FIG. 1;

FIG. 7 is an electrical block diagram of the timing unit which provides the clock signals for the subject invention;

FIG. 8 is a diagram illustrative of the modified fast Fourier transform algorithm performed by the Fourier transform processor shown in FIG. 5;

FIG. 9 is a flow chart of the envelope detector algorithm performed in the Fourier transform processor of FIG. 5; and

FIG. 10 is a flow chart illustrative of the program cycle of the post-detection processor apparatus shown in FIG. 6.

Referring now to the drawings wherein like reference numerals refer to like elements throughout, reference is first made to FIG. 1 wherein reference numeral 10 designates a radio receiver which is adapted to receive coded frequency shift keying (FSK) data burst signals (at a message rate of 300 bits per second, for example) whose center frequency drift is large (plus or minus 5 filter spacings in FIG. 2, for example) compared to their bandwidth (frequency shift of plus or minus 2 to 3 filter spacings) and extract these signals in real time from co-channel noise, interference or jamming signals utilizing a digital filter bank detector 12, which is the subject matter of the present invention. The digital filter bank detector 12 is particularly adapted to improve the performance of a military radio receiver, a typical example being an AN/USQ-46 RF monitor set. The receiver 10 is shown including a front-end section 14 which is coupled to an RF antenna 16 and adapted to provide an IF signal. The IF signal which may be, for example, a signal whose center frequency is in the region of 21.4 MHz and having a bandwidth of for example 20 KHz is fed to the filter bank detector 12 as well as a limiter/discriminator section 18, which is adapted to provide an audio output. The output of the limiter/discriminator section 18 is additionally fed to a data regenerator section 20, which is adapted to feed into a data decoder section 22 through electronic switch device 24 which is also coupled to the detector 12. The output of the data decoder is coupled to a data display device 26 and operates in a fashion well known to those skilled in the art.

As shown in FIG. 1, the digital filter bank detector 12 is comprised of four major portions or sub-sections. A signal conditioner 28 is included which acts to convert a 20 KHz bandwidth IF signal centered at 21.4 MHz to a sequence of 12-bit digital words at a sampling rate exactly equal to 48 times the filter spacing in FIG. 2, for example a sampling of 53.6 KHz for filters spaced 1117.5 Hz apart in center frequency. Next an envelope weighting computer 30 is provided which accepts the digital word samples and establishes the filter shape of 16 contiguous narrowband filters as shown in FIG. 2 and acts in combination with a Fourier transform processor 32 which operates to establish 16 mutually equally spaced center frequencies and computes envelope amplitudes at each frequency. The Fourier transform processor 32 acts in concert with the envelope weighting computer 30 to process the digital samples and synthesize a digital filter bank. Lastly a post-detection processor 34 is also included in the filter bank detector 12 which incorporates adaptive clipping and threshold logic to identify a valid FSK filter pair and demodulation and data regeneration data logic for regenerating received message signals in the form of reconstructed binary data and clock signals which are fed via a mode switch 24 to the data decoder 22.

The detector 12 also incorporates a regulated power supply 36, a timing unit 38 which is adapted to provide the necessary clock signals required to synchronize operation of the signal processing means 28, 30, 32 and 34, a monitor unit 40 and a front panel control sub-section 42.

Considering now the details of the filter bank detector 12, reference is now made to FIG. 3 where there is shown in block diagram form the details of the signal conditioner sub-section 28. The IF signal from the front-end section 14 of the receiver 10 is fed into a crystal filter and amplifier circuit 44 which provides selective bandpass amplification and filtering of the IF input signal which is then coupled to a balanced mixer 46 which is also coupled to a temperature-compensated crystal oscillator (TCXO) 48. The mixer 46 operates to translate the IF center frequency downward from 21.4 MHz to a second IF center frequency of, for example, 40.8 KHz. This new IF signal is fed to the filter-amplifier 50 including a 12-pole passive filter, not shown, which is used to control aliasing in the sampling process which is to follow. At this point an IF text point 52 is also provided.

The 40.8 KHz IF signal is next quantized in time and amplitude by means of a sample-and-hold circuit 54 which is adapted to provide time quantizing and an analog to digital (A/D) converter 56 which is adapted to provide amplitude quantizing. A first clock signal (53.64 KHz) is coupled to both the sample-and-hold circuit 54 and the A/D converter 56 via terminal point 58 shown in FIG. 3. A second clock signal (697.32 KHz) is additionally applid to the A/D converter 56 via terminal 60. The first clock signal determines the sampling rate, while the second clock signal is adapted to generate a 12-bit binary number by the method of successive approximation. The output of the A/D converter comprises an offset binary code (all 0's=minus full scale, all 1's=plus full scale) which is then changed to 2's complement notation by inversion of the most significant (sign) bit.

Proceeding now to FIG. 4, the 12-bit words from the A/D converter 56 are fed via data bus 61 to the envelope weighting computer 30 (FIG. 1) where the most recent 384 words are processed in each frame, the processing frame rate being chosen very nearly four times faster than the message bit rate (for example, a frame rate of 1192 Hz representing the sampling rate of 53.64 KHz divided by a factor of 45, for a nominal message bit rate of 300 bits per second.) In particular, the 12-bit words from the A/D converter are fed to a dual 45.times.12 word input buffer consisting of shift registers 62 and 64. A 384.times.12 word recirculating shift register 66 is coupled to the shift registers 62 and 64 by means of 12 pole electronic switching devices which are shown schematically and identified by reference numerals 68 and 70. The 12-bit data words received from the A/D converter 56 at a 53.64 KHz sampling rate are loaded into register 62 during every other frame and into register 64 during the intervening frames. While register 62 is being used to store 45 new data samples, register 64 is used to update the recirculating shift register 66. The shift registers 62, 64 and 66 and switching devices 68 and 70 are controlled by the outputs from a shift clock and gate generator circuit 72 which receives a 53.64 KHz, a 557.856 KHz, a 1192 Hz and a 596 Hz clock signal from the timing unit shown in FIG. 7 via circuit leads 74, 76, 78 and 79 respectively. Outputs from the generator 72 are coupled to various elements via signal leads having the alphabetical designations A . . . G as shown in FIG. 4.

Updating of shift register 66 in one frame is achieved by applying high speed (557.856 KHz) shift pulses to register 64 via B and setting electronic switches 68 and 70 to their respective "0" position. The next 45 words representing new input data are transferred from register 64 to register 66 by the simultaneous application of pulses at a 557.856 KHz rate on leads B and C. At the same time, the oldest 45 words previously held in shift register 66 are discarded. After 45 shift pulses have occurred, switch 70 is activated to its "1" position by a signal coupled thereto via line F and further outputs from the register 64 are ignored. During the next frame register 62 will be used to update shift register 66. Updating from register 62 occurs in the same manner described except that switch 68 will be in its "1" position in response to a signal applied thereto via circuit lead E.

After the shift register 66 has been updated at the beginning of each frame i.e. 45 of the first 48 pulses, its output words are circulated back into its input via data bus 80 and switch 70 for the next 384 high speed (557.856 KHz) shift pulses thereby effecting a time compression of 10.4/1 on the 53.64 KHz words from the A/D converter. As the 12-bit words are recirculated, they are applied to one input of a 12.times.12 digital multiplier circuit 82 where the word samples are multiplied by a time-domain weighting function e.sub.l obtained from a ready-only memory 84 which has predetermined constant weighting coefficients stored therein. The weighting coefficients approximate an ideal sinx/x pattern where the width of the main lobe corresponds roughly to one half of a message bit interval. Because the weighting coefficients e.sub.l are symmetrical about their midpoint, only 192 samples are stored in the ROM 84 and they are read out first with an increasing address and then with a decreasing address under the control of an up/down counter 86. The multiplier 82 is designed to preserve the 16 most significant bits of the full 24-bit product which normally results from multiplying two 12-bit numbers. The multiplier output accordingly comprises truncated 16-bit words which are applied to an output accumulator consisting of a 16-bit adder 88, a 48-word shift register 90, and a 16-bit electronic switch 92 which is operated by a signal applied via lead G. The shift register 90 is operated in accordance with a signal applied from the generator 72 via lead D.

The register 90 is used as an accumulator memory for computed output data to take advantage of the fact that all of the center frequency weighting functions used in the Fourier transform processor 32 are repetitive every 48 samples. During the first 48 high speed 557.856 KHz clock pulses, register 90 is cleared by shifting out the previously computed 48 data words to a 16-bit data bus 94. Register 90 is disconnected from the adder during this time by placing the switch 92 in its "0" position in response to a control signal on lead G. During the next 384 recirculation clock pulses, the input to shift register 90 is reconnected to the sum output of the adder 88. The two 16-bit inputs to the adder 88 are the multiplier product output and the delayed output from register 90. As each multiplier output word is computed, it is added to the previous sum of products stored 48 pulses earlier in register 90. Each of the 48 words in register 90 is accumulated eight times during the 384 recirculation shifts of register 66.

During the last 36 of the 468 high speed clock pulses in each frame, the envelope weighting computer is idle except for the input register 62 or 64 which is loading new data at the 53.64 KHz shift rate. Shift register 90, on the other hand, retains the computed 48 output words during the idle period which are then transferred as the signal samples f.sub.l on data bus 94 to the Fourier transform processor 32 in the beginning of the next data frame. This operation thus digitally synthesizes the time-domain envelope response of a plurality (16) of identical filters all having the same shape or frequency response, differing only in center frequency. Weighting by 16 different center frequency functions is accomplished in the Fourier transform processor 32 now to be descried.

Referring now to FIG. 5, there is shown in block diagrammatic form a bus-oriented digital Fourier transform processor (FTP) having a dual arithmetic capability. Essentially the FTP processor 32 (FIG. 1) is comprised of two 16-bit arithmetic logic units 96 (ALU-1) and 98 (ALU-2) which are selectively coupled in accordance with a stored program to two 16-bit data word random access memories (RAM) 100 (F1) and 102 (F2) through scaler means (multipliers X1 or X1/2) 104, 106 and 108, 110. Additionally, multi-bit electronic switches 112 and 114 interconnect the RAMs 100 and 102 to the scalers 104 and 108. Also, a multiplier (x) circuit 116 is connected between the RAM 102 and the switch 114. The multiplier 116 is adapted to receive inputs from a read-only memory (ROM) 118 which is programmed with trigonometric coefficients or weighting factors which are outputted either indirectly in response to a phase latch circuit 120, or directly in response to a program instruction decoder 126.

A stored operational program is contained in a 468-word programmable ROM 122 indexed by means of a program counter 124. A program decoder 126 is coupled to the ROM 122 and is operable to address specific memory locations in RAM 100, RAM 102 and ROM 118, and also to effect predetermined interconnection of the elements shown in FIG. 5 to provide 36 different circuit configurations for implementing 36 different instructions which are defined in Appendix 1A and used in accordance with the program specified in the FTP program list outlined in Appendix 1B. The specific circuit configurations for the elements of FIG. 5 for each instruction type are shown in Appendix 1C. Appendices 1A, 1B, and 1C are attached to and form a part of the detailed specification.

The program outlined in Appendix 1B is adapted to perform operations equivalent to the following computations: ##EQU1## where I.sub.k is the in-phase component at frequency k ##EQU2## where Q.sub.k is the quadrature-phase component at frequency k,

where .phi..sub.k is an estimate of the true phase angle at frequency k, and

where E.sub.k is the envelope amplitude at frequency k. In equations (1), (2), (3), and (4), the frequency index k takes on the values from 4 to 19 in synthesizing a bank of 16 contiguous filters covering, for example, a passland of 3.8-21.8 KHz if the sampling rate is 53.64 KHz.

The I.sub.k and Q.sub.k values are computed using a 48-point modified fast Fourier transform (FFT) algorithm. The modified algorithm employed differs from a conventional FFT algorithm in the following respects: (a) the modified algorithm contains 3:1 transformations as well as 2:1 transformations; (b) because only 32 outputs are required (I.sub.k and Q.sub.k values for each filter), the operations needed to produce the remaining 16 outputs of a full 48-point transform are omitted; (c) the sequence of operations performed is designed to minimize the number of irrational multiplications (by factors other than 0, .+-.1/2, or .+-.1) and also to minimize the number of irrational multiplying factors; and (d) an absolute value computation is computed on the last step in which each I.sub.k or Q.sub.k output value is produced. A simplified flow diagram for the 48-point modified FFT algorithm is shown in FIG. 8. The computations consist of 2:1 and 3:1 transformations designed to produce intermediate combinations of input data associated with progressively smaller groups of output data. The FFT algorithm is computed in eight stages, i.e. eight passes through the 48 stored data words. The circled numbers in FIG. 8 indicate the stages during which each 2:1 or 3:1 transformation is accomplished. As is well known, each basic step combines data samples in pairs. A new pair of data samples is obtained as a weighted sum and a weighted difference of the original pair of samples. At the end of each step the original pair of samples is discarded and the new pair of samples is stored in their place. The envelope amplitude E.sub.k for each narrowband filter is next computed in the processor shown in FIG. 5 by means of a successive phase algorithm. This indirect method of computing E.sub.k makes more efficient use of the dynamic range available in a 16-bit digital processor than the more direct method of taking the square root of the sum of the squares. The phase approximation algorithm is based on the trigonometric formula given in equation (3), which can be restated in the form:

A flow diagram of the envelope detector algorithm is illustrated in FIG. 9. By taking the absolute magnitudes .vertline.K.sub.k .vertline. and .vertline.Q.sub.k .vertline. the possible values of .phi..sub.k are initially restricted to the range 0.degree. to 90.degree.. The magnitudes .vertline.I.sub.k .vertline. and .vertline.Q.sub.k .vertline. are then interchanged if necessary to further restrict .phi..sub.k to the range 0.degree. to 45.degree.. A trial value in the middle of this range (22.5.degree.) is then used as the first approximation for .phi..sub.k. Depending on the polarity of the result from equation (5a), .phi..sub.k is then either increased or decreased by 11.25.degree.. The same process is repeated using successively smaller corrections to .phi..sub.k until a final value is obtained which is accurate to within .+-.0.7.degree.. The envelope amplitude E.sub.k is then computed using equation (4). Each E.sub.k envelope sample is outputted from the Fourier transform processor on data bus 128 (FIG. 5) on the twelfth step of sixteen 12-step cycles occurring between steps 263 and 454 of the program as shown in Appendix 1B.

The sixteen E.sub.k samples are fed to the post-detection processor 34 (FIG. 1) which implements an adaptive threshold function, a search/track function, and a data regeneration of the message signals in digital form. The details of the post-detection processor are shown in FIG. 6 and include a single arithmetic logic unit 130 (ALU-1) intercoupled with a pair of random access memories 132 (F1) and 134 (F2) in a manner similar to the Fourier transform processor (FIG. 5). It also includes a table look-up ROM 136 containing predetermined numerical constants which is controlled either indirectly by a phase angle latch 138 or a K factor switch section 140, or directly by an instruction decoder 156. The ROM 136 couples to multiplier 142 along with the output of the RAM 132. The output of the RAM 132 is coupled to the arithmetic logic unit 130 by means of a multi-pole electronic switch 144 either directly or through the multiplier 142 or through a scaler (X1/2) circuit 146. The switch 144 is also adapted to connect the input of the arithmetic logic unit 130 to the output of the read only memory 136. The other input to the arithmetic logic unit 130 couples to the random access memory 136 through a multi-pole electronic switch 148 which is also adapted to input the E.sub.k envelope samples which have been subjected to a fixed scaling and clipping operation which is provided by means of the circuit 150.

The post-detection processor operates on a 468-step program cycle, the flow chart of which is diagrammatically illustrated in FIG. 10. The program cycle operates at a 557.856 KHz clock rate in accordance with a program stored in the read-only memory 152. A program counter 154 controls the output of instructions which are defined in Appendix IIA and listed in Appendix IIB. The instruction decoder 156, together with the sign latch 131, the search/track unit 158, and the output unit 159 effects a repertoire of 57 circuit configurations as illustrated in Appendix IIC for the 57 instruction types required over the 468-step program cycle.

In operation, each E.sub.k sample is received from the Fourier transform processor (FIG. 5) where it is subjected to both a fixed and an adaptive clipping operation. The fixed clip level is set at "1/2 of positive full scale", while the adaptive clip level is at "K1.times.AVG" which is a controllable number of db above the average spectrum background level, the constant K1 being set by the control unit 42 shown in FIG. 1.

The clipped E.sub.k values are stored and used as input data for a recursive low pass filter (LPF) and very low pass filter (VLPF) algorithm which have the form:

where X.sub.i is the input sample for the ith frame, Y.sub.i is the output sample for the ith frame, and K is a controllable time constant (K3 for LPF and K4 for VLPF) selectable from the front panel control unit 42. Each of the 16 narrowband filters is flagged as being below threshold by forcing the sign of its LPF value negative whenever its short term energy does not exceed its VLPF value (long term energy) by a controllable threshold constant K5. The average spectrum level (AVG) is updated every frame to the mean value of all VLPF's whose corresponding E.sub.k values were below the clipped level. The previous AVG value is retained, however, if more than a controllable number K2 of the E.sub.k values exceeded the clip level.

Next the search algorithm examines the filter LPF values in pairs. There are ten pairs of LPF values with a spacing of four filters, eleven pairs with a spacing of five filters, and ten pairs with a spacing of six filters which fall within the tolerance limits for the FSK (frequency shift keying) sensor transmitters associated with the particular radio receiver AN/USQ-46. These thirty-one pairs of LPF values are examined sequentially to find a pair above a predetermined threshold, meaning that both LPF's are positive. If one or more valid pairs are found, the filter pair having the largest sum of LPF's is selected for tracking, otherwise the program remains in the search mode.

The tracking algorithm is adapted to continue selecting an acquired filter pair as long as both LPF's remain above threshold. If either LPF falls below threshold, the next higher or lower filter is selected, provided that it represents a new valid filter pair above threshold, otherwise the program reverts to the search mode. This mode of tracking continues during the eight "0" bits in a message preamble. When a "1" bit (message start flag) is detected, the program switches to a "hold" mode and the last tracked filter pair is retained for the duration of the message.

The demodulator and data regenerator algorithms implemented by the PDP program are active only in the track or hold modes. Demodulation consists of subtracting the stored E.sub.k values for the selected pair of filers to obtain the demodulated data samples D.sub.i. A reference level L.sub.i, used during data regeneration, is also computed as the sum of the VLPF's for the selected pair of filters. The four most recent D.sub.i samples are stored in the matched filter memory implemented in steps 158-174. Four samples represent approximately one message bit. Bit timing pulses T.sub.i are computed from D.sub.i using the same recursive low pass filter algorithm cited in equation (6) with a predetermined time constant K.sub.6. Undelayed samples D.sub.i are supplied to the bit timing algorithm for the first four frames after filter acquisition. Thereafter, delayed samples .+-.D.sub.i-4 are applied with polarity controlled by the last data decision to approximate an unmodulated 300 Hz sine wave. The amplitude and phase of the 300 Hz component in the bit timing memory are computed using a simple 4-point Fourier transform. When the amplitude E.sub.i times a predetermined threshold constant K.sub.7 equals the reference level L.sub.i, bit timing is declared valid. Thereafter, a sync pulse is generated whenever the computed phase angle .phi..sub.i falls within the sync sector corresponding to a message bit transition. Bit timing is tracked throughout a received message and if it becomes invalid before message completion, the memory is cleared and a search mode reinitiated.

For each frame in which a sync pulse is generated, a matched filter output sample M.sub.r and a preamble correlator output sample P.sub.r are computed. The matched filter output sample is computed from the last four D.sub.i samples and the current phase sample .phi..sub.i according to the following expression: ##EQU3##

The eight most recent M.sub.r samples are stored and used for computing the preamble correlator samples P.sub.r according to the following expression: ##EQU4## The last seven preamble "0's" and the flag bit "1" are included in the message preamble correlation. Prior to detection of the flag bit, data decisions are made only if the last P.sub.r sample times a threshold constant K.sub.8 exceeds the reference level L.sub.1. Data decisions are based on the polarity of the matched filter output M.sub.r. Once a data decision is made and found to be valid, the apparatus initiates the hold mode and the preamble correlator samples are ignored for the remainder of the message which is fed to the data decoder 22 in FIG. 1. Upon receipt of either a parity reset pulse indicative of unsuccessful decoding or an EOC (end-of-code) reset pulse indicative of successful decoding, the data regenerator and LPF memory is cleared and the search mode is reinitiated.

In order to synchronize operation of the apparatus described above, the timing unit 38 as shown in FIG. 7 is employed. Basically it consists in utilizing a master timing oscillator 162 whose output is coupled to a plurality of frequency divider circuits. More particularly, where for example the output of the timing oscillator 162 comprises a 11.15712 MHz signal, it is first coupled to a .div.2 frequency divider 164 whose output is branched first to a .div.8 circuit 166 and a .div.10 circuit 168. The output of the divider circuit 166 comprises the 697.32 KHz clock signal which is coupled to the A/D converter 56 shown in FIG. 3. This clock signal is additionally fed to a .div.13 frequency divier circuit 170 which provides the sample rate clock signal of 53.64 KHz applied to the sample and hold circuit 54 as well as the A/D converter 56 shown in FIG. 3. The output of the frequency divider circuit 170 is further divided by a .div.45 circuit 172 which develops a 1192 Hz reset signal for the .div.10 divider circuit 168 and the .div.468 circuit 174 coupled thereto, the latter providing the 1192 Hz frame rate clock signal applied to the shift clock and gate generator 72 shown in FIG. 4 while the output of the .div.10 circuit 168 comprises the 557.856 KHz program clock signals applied to the envelope weighting computer (FIG. 4), the Fourier transform processor (FIG. 5), and the post-detection processor (FIG. 7). In addition, a .div.2 circuit 176 is coupled to the frequency divider 172 for providing a 596 Hz signal which is applied to the shift clock and gate generator circuit 72 shown in FIG. 4 for developing the gate signal E for controlling input buffer alternation between the operation of the shift registers 62 and 64.

In summation, what is disclosed is a digital signal processor including means for synthesizing a bank of contiguous narrowband filters, all having the same shape of frequency response and differing only in center frequency, for detecting IF signals extracted from an FSK RF receiver to recover data messages which are then reinserted into data decoder and display apparatus of the receiver.

While there has been shown and described what is at present considered to be the preferred embodiments of the subject invention, further modifications thereto will readily occur to those skilled in the art. It is not desired, therefore, that the invention be limited to specific arrangements as shown and described, but it is to be understood that all equivalents, alterations and modifications coming within the spirit and scope of the invention as defined by the subjoined claims are herein meant to be included.