Display Device for Electronic Calculator or the Like

This invention relates to a display device for use in an electronic apparatus such as an electronic calculator, and more particularly a new and effective display device for displaying data derived from an electronic calculator.

In the past, when it was desired to display data having a length more than the capacity of a display panel in an electronic calculator, the data to be displayed would be split into two or more groups in advance. Nevertheless, the connection between the groups was often indefinite and vague, leading to operator errors in recognizing the overall or combined contents being displayed.

It is therefore an object of the present invention to surmount the above discussed difficulties with the prior art. It is another object of the present invention to provide a display device for use in electronic calculators or the like which is capable having displaying data of a length more than the capacity of a display panel by shifting the overall display contents such as numerals, characters and symbols at every passage of a given length of time. The above discussed difficulties are overcome by constantly moving the display contents without switching the display contents at the conclusion of each group, thereby enhancing legibility of the display contents.

One of the features of the present invention lies in that the display contents are shifted and circulated in such a manner that the beginning of the display contents are again displayed after the overall display contents have gone from the edge of the display panel. In other words, the beginning of the display contents is not displayed unless the overall contents disappear from the edge of the panel. The display device according to the present invention provides an easy to read display with a definite delimitation.

Another feature of the present invention is that the displaying operation is accomplished in either a conventional mode (namely, the static mode) or a shift mode, depending upon what kind of data is to be displayed. Fr example, data such as operation results are displayed in the conventional mode (the static mode), whereas instructions as to the order of arithmetic operations are displayed in the shift mode and thus the instructions being displayed are moved at every passage of the given length of time. Even though the same contents are displayed on the panel, it becomes possible to identify the significance (or the type) of the contents by the displaying condition. This feature of the present invention is very instrumental to multiple function calculators.

As still another advantageous feature, the prevent invention provides a display device for an electronic calculator with various facilities: displaying in a similar manner to talking-news on buildings data to be next introduced when the calculator is in a halt condition on the way of executing program calculations (that is, a particular calculation comes to a halt until data are entered at a step of entering data from outside of the calculator on the way of executing the calculation); modifying characters (symbols) at a particular region of the overall display contents according to the internal operating state of the calculator; and also displaying calculation results for a given length of time immediately before the display state is commenced.

For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a plan view of an example of a programmable calculator embodying a display device according to the present invention;

FIG. 2 is an explanatory diagram of the progress of the displaying state of the calculator;

FIG. 3 is a schematic block diagram showing the essence of the calculator;

FIGS. 4A, 4B, 4C and 4D are logic diagrams of an example of a central processor unit (CPU) in the calculator;

FIG. 5 is a composite schematic diagram of the CPU in the calculator;

FIG. 6 is a flow chart for explaining the displaying operation according to the present invention; and

FIG. 7 is a flow chart for explaining the left shift operation of a character memory MC.

In FIGS. 1 and 2, there are illustrated a plan view of a programmable calculator according to one preferred embodiment of the present invention and a representation showing the progress of the display state of the calculator.

In FIG. 1, a display device, for example, a dot matrix type alphanumerical liquid crystal display panel is labeled 1 and a keyboard unit is labeled 2. FIGS. 2(a)-2(i) show events over the progress of the display state when a calculator such as a function calculator reaches a halt condition during the progress of calculations to instruct the operator to introduce input data to be next introduced. FIG. 2(a) depicts a normal display mode whereas FIGS. 2(b)-2(g) depict a shifting or running display at respective points in time according to the present invention. In FIG. 2(a), there is displayed the leading character of an instruction indicative of introduction of input data to be next entered. This is followed by the display state (c) after the passage of a given length of time (say, 0.5 sec), the display state (d) after the passage of further 0.5 sec and so forth. In this way, the display contents are shifted in the sequence of (b).fwdarw.(c).fwdarw.(d) . . . (e).fwdarw.(f).fwdarw.. . . (g).fwdarw.(h).fwdarw.(i) at every given length of time. After the overall display contents have gone, the display panel is restored to the initial or conventional state. The above operation sequence is then repeated.

FIG. 3 is a block diagram of one embodiment of a calculator equipped with the display device according to the present invention. The embodiment shown in FIG. 3 contains a key input unit 3, a central processor unit 4 (hereinafter referred to as "CPU") described below for decoding and executing instructions, a character generator CRG 5 for decoding output signals from registeres SA and SX, a dot matrix type liquid display panel 6 of for example an eight digit capacity each digit in a 5.times.7 matrix, digit select signal leads 7 and segment select signal leads 8.

FIG. 4, a composite diagram of FIGS. 4A-4D, shows a logic wiring diagram of a specific example of the CPU scheme in the calculator whereby the display operation of the present invention is effected. FIG. 5 shows how to combine FIGS. 4A-4D concerning the CPU. The following will set forth a logic structure of the CPU.

A random access memory RAM has a 4 bit input and output capacity and is accessible by a specific digit position thereof as identified by a digit address and a file address. The RAM includes a digit address counter BL, a digit address decoder DC.sub.1, a file address counter BM, a file address decoder DC.sub.2 and an adder AD.sub.1 which serves as an adder and a subtractor respectively in the absence and presence of a control instruction 14 . It further includes a second adder AD.sub.2 and a gate G.sub.1 for providing either a digit "1" or an operand I.sub.A to an input to the adder/subtractor AD.sub.1 and delivering I or I.sub.A when a control instruction 15 or 16 is developed, respectively. An input gate G.sub.2 is provided for the memory digit address counter BL, which enables the output of the adder/subtractor AD.sub.1, the operand I.sub.A and another operand I.sub.B to pass therethrough respectively when control instructions 10 , 11 and 12 are developed. A gate G.sub.3 is disposed to provide a digit "1" or the operand I.sub.A to an input to the adder/subtractor, the former being provided upon the development of an instruction 5 and the latter upon the development of an instruction 6 . A gate G.sub.4 is an input gate to the memory file address BM which enables the output of the adder AD.sub.2, the operand I.sub.A and the contents of an accumulator ACC to pass upon the development of instructions 7 , 8 and 9 . A file selection gate G.sub.5 is further provided for the memory RAM. A decoder DC.sub.3 translates the operand I.sub.A and supplies a gate G.sub.6 with a desired bit specifying signal. The gate G.sub.6 contains a circuit arrangement for introducing a binary code "1" into a specific bit position of the memory identified by the operand decoder DC.sub.3 and a binary code "D" into a specific bit position identified by DC.sub.3, respectively, when a control instruction 2 or 3 is developed. Upon the development of an instruction 4 the contents of the accumulator ACC are read out.

A read only memory ROM has its associated program counter PL which specifies a desired step in the read only memory ROM. The read only memory ROM further contains a step access decoder DC.sub.4 and an output gate G.sub.7 which shuts off transmission of the output of the ROM to an instruction decoder DC.sub.5 when a judge flip flop F/F J is set. The instruction decoder DC.sub.5 is adapted to decode instruction codes derived from the ROM and divide them into an operation code area I.sub.O and operand areas I.sub.A and I.sub.B, the operation code being decoded into any control instruction 1 - 61 . The decoder DC.sub.5 is further adapted to output the operand I.sub.A or I.sub.B as it is when sensing an operation code accompanied by an operand. An adder AD.sub.3 increments the contents of the program counter PL. An input gate G.sub.8 associated with the program counter PL provides the operand I.sub.A and transmits the contents of a program stack register SP when the instructions 20 and 61 are developed, respectively. When the instructions 20 , 61 and 60 are being processed, any output of the adder AD.sub.3 is not transmitted. Otherwise the AD.sub.3 output is transmitted to automatically load "1" into the contents of the program counter PL. A flag flip flop FC has an input gate G.sub.9 therefor which introduces binary codes "1" and "0" into the flag flip flop FC when the instructions 17 and 18 are developed, respectively. A key signal generating gate G.sub.10 provides the output of the memory digit address decoder DC.sub.1 without any change when the flag F/F FC is in the reset state (0), and renders all outputs I.sub.1 -I.sub.n "1" whatever output DC.sub.1 provides when FC is in the set state (1). The accumulator ACC is 4 bits long and a temporary register X is also 4 bits long. An input gate G.sub.11 for the temporary register X transmits the contents of the accumulator ACC and the stack register SX respectively upon the development of the instructions 29 and 59 . An adder AD.sub.4 executes a binary addition on the contents of the accumulator ACC and other data. The output C.sub.4 of the adder AD.sub.4 assumes "1" when the fourth bit binary addition yields a carry. A carry F/F C has its associated input gate G.sub.12 which sets "1" into the carry F/F C in the presence of "1" of the fourth bit carry C.sub.4 and "0" into the same in the absence of C.sub.4 (0). "1" and "0" are set into C upon the development of 21 and 22 , respectively. A carry (C) input gate G.sub.18 enables the adder AD.sub.4 to perform binary additions with a carry and thus transmits the output of the carry F/F C into the adder AD.sub.4 in response to the instruction 25 . An input gate G.sub.14 is provided for the adder AD.sub.4 and transfers the output of the memory RAM and the operand I.sub.A upon the development of 23 and 24 , respectively. An output buffer register F has a 4 bit capacity and an input gate which enables the contents of the accumulator ACC to enter into F upon the development of 31 . An output decoder SD decodes the contents of the output buffer F into display segment signals SS.sub.1 -SS.sub.n. An output buffer register W has a shift circuit SHC which shifts the overall bit contents of the output buffer register W one bit to the right at a time in response to 32 or 33 . An input gate G.sub.16 for the output buffer register W provides "1" and "0" to the first bit position of W upon 32 and 33 , respectively. Immediately before 37 1" or or "0" enters into the first bit position of W the output buffer shift circuit SHC becomes operative.

An output control flag F/F N.sub.p has an input gate G.sub.17 for receiving "1" and "0" upon the development of 34 and 35 , respectively.

The buffer register W is provided with an output control gate G.sub.18 for providing the respective bit outputs thereof at one time only when the flag F/F N.sub.p is in the set state (1). There are further provided a judge F/F J, inverters IV.sub.1 -IV.sub.4 and an input gate G.sub.19 for the judge F/F J for transferring the state of an input KN.sub.1 l into J upon the development of 36 . In the case where KN.sub.1 =0, J=1 because of intervention of the inverter IV.sub.1. An input gate G.sub.20 for the judge F/F J is adapted to transfer the state of an input KN.sub.2 into J upon 38 . When KF.sub.1 =0, J=1 becuase of intervention of the inverter IV.sub.3. An input gate G.sub.22 for the judge F/F J is adapted to transfer the state of the input KF.sub.2 into J upon 39 . When KF.sub.2 =0, J=1 because of the intervened inverter IV.sub. 4. An input gate G.sub.23 is provided for the judge flip flop J for transmission of the state of an input AK into J upon the development of 40 . When AK=1, J=1. An input gate G.sub.24 is provided for the judge flip flop J to transmit the state of an input TAB into J pursuant to 41 . When TAB=1, J=1. A gate G.sub.25 is provided for setting the judge F/F J upon the development of 42 . A comparator V.sub.1 compares the contents of the memory digit address counter BL with preselected data and provides an output "1" if there is agreement. The comparator V.sub.1 becomes operative when 43 or 44 is developed. The data to be compared are derived from a gate G.sub.26 which is an input gate to the comparator V.sub.1. The data n.sub.1 to be compared are a specific higher address value which is often available in controlling the RAM. n.sub.1 and n.sub.2 are provided for comparison purposes upon the development of 43 and 44 , respectively.

An input gate G.sub.27 is provided for the decision F/F J to enter "1" into J when the carry F/F C assumes "1" upon the development of 45 .

A decoder DC.sub.6 decodes the operand I.sub.A and helps decisions as to whether or not the contents of a desired bit position of the RAM are "1". A gate G.sub.28 transfers the contents of the RAM as specified by the operand decoder DC.sub.6 into the judge F/F when 46 is derived. When the specified bit position of the RAM assumes "1", J=1. A comparator V.sub.2 decides whether or not the contents of the accumulator ACC are equal to the operand I.sub.A and provides an output "1" when the affirmative answer is provided. The comparator V.sub.2 becomes operative according to 47 . A comparator V.sub.3 decides under 48 whether the contents of the memory digit address counter BL are equal to the operand I.sub.A and provides an output "1" when the affirmative answer is obtained. A comparator V.sub.4 decides whether the contents of the accumulator ACC agree with the contents of the RAM and provides an output "1" in the presence of the agreement. A gate G.sub.29 transfers the fourth bit carry C.sub.4 occurring during additions into the judge F/F J. Upon the development of 50 C.sub.4 is sent to F/F J. J=1 in the presence of C.sub.4. A flag flip flop FA has an input gate G.sub.31 which provides outputs "1" and "0" upon the development of 52 and 53 , respectively. An input gate G.sub.32 is provided for setting the judge F/F J when the flag flip flop FA assumes "1". A flag flip flop F.sub.B also has an input gate G.sub.33 which provides outputs "1" and "0" upon 55 and 56 , respectively. An input gate G.sub.34 for the judge flip flop J is adapted to transfer the contents of the flag flip flop F.sub.B into the F/F J upon the development of 54 . An input gate G.sub.35 associated with the judge F/F J is provided for transmission of the contents of an input B upon 19 . When B=1, J=1. An input gate G.sub.36 associated with the accumulator ACC is provided for transferring the output of the adder AD.sub.4 upon 26 and transferring the contents of the accumulator ACC after inverted via an inverter IV.sub.5 upon 27 . The contents of the memory RAM are transferred upon 28 , the operand I.sub.A upon 13 , the 4 bit input contents k.sub.1 -k.sub.4 upon 57 , and the contents of the stack register SA upon 59 . A stack register SA provides the output outside the present system. A stack register SX also provides the output outside the system. An input gate G.sub.37 associated with the stack register SA transfers the accumulator ACC upon 58 . An input gate G.sub.38 associated with the stack register SX transfers the contents of the temporary register X. A program stack register SP has an input gate G.sub.39 for loading the contents of the program counter PL incremented by "1" through the adder into the program stack register.

An illustrative example of the instruction codes contained within the ROM of the CPU structure, the name and function of the instruction codes and the control instructions developed pursuant to the instruction codes will now be tabulated in Table 1 wherein A: the instruction codes, B: the instruction name, C: the instruction description and D: The CPU control instructions.

(1) SKIP

Only the program counter PL is incremented without executing a next program step instruction, thus skipping a program step

(2) AD

A binary addition is effected on the contents of the accumulator ACC and the contents of the RAM, the addition results being loaded back into the accumulator ACC.

(3) ADC

A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry F/F C, the results being loaded back to the accumulator ACC.

(4) ADCSK

A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry flip flop C, the results being loaded into the accumulator ACC. If the fourth bit carry C.sub.4 occurs in the results, then a next program step is skipped.

(5) ADI

A binary addition is achieved upon the contents of the accumulator ACC and the operand I.sub.A and the results are loaded into the accumulator ACC. If the fourth bit carry C.sub.4 is developed in the addition results, then a next program step is skipped.

(6) DC

The operand I.sub.A is fixed as "1010" (a decimal number "10") and a binary addition is effected on the contents of the accumulator ACC and the operand I.sub.A in the same way as in the ADI instruction. The decimal number 10 is added to the contents of the accumulator ACC, the results of the addition being loaded into ACC.

(7) SC

The carry F/F C is set ("1" enters into C).

(8) RC

The carry F/F C is reset ("0" enters into C).

(9) SM

The contents of the operand I.sub.A are decoded to give access to a desired bit position of the memroy specified by the operand ("1" enters).

(10) RM

The contents of the operand I.sub.A are interpreted to reset a desired bit position of the memory specified by the operand ("0" enters).

(11) COMA

The respective bits of the accumulator ACC are inverted and the resulting complement to "15" is introduced into ACC.

(12) LDI

The operand I.sub.A enters into the accumulator ACC.

(13) L

The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the file address counter BM.

(14) LI

The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the memory file address counter BM. At this time the memory digit address counter BL is incremented. If the contents of BL agree with the preselected value n.sub.1, then a next program step is skipped.

(15) XD

The contents of the memory RAM are exchanged with the contents of ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is decremented. In the event that the contents of BL agree with the preselected value n.sub.2, then a next program step is skipped.

(16) X

The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is loaded into the memory file address counter BM.

(17) XI

The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is incremented. In the event that BL is equal to the preselected value n.sub.1, a next program step is skipped.

(18) XD

The contents of the memory RAM replaces the contents of the accumulator ACC, the operand I.sub.A being sent to the memory file address counter BM. The memory digit address counter BL at this time is incremented. If the contents of BL are equal to n.sub.2, then a next program step is skipped.

(19) LBLI

The operand I.sub.A is loaded into the memory digit address counter BL.

(20) LB

The operand I.sub.A is loaded into the memory file address counter BM and the operand B to the memory digit address counter BL.

(21) ABLI

The operand I.sub.A is added to the contents of the memory digit address counter BL in a binary addition fashion, the results being loaded back to BL. If the contents of BL are equal to n.sub.1, then no next program step is carried out.

(22) ABMI

The operand I.sub.A is added to the contents of the memory file address counter BM in a binary fashion, the results being into BM.

(23) T

The operand I.sub.A is loaded into the program step counter PL.

(24) SKC

If the carry flip flop C is "1", then no next program step is taken.

(25) SKM

The contents of the operand I.sub.A are decoded and a next program step is skipped as long as a specific bit position of the memory specified by the operand I.sub.A assumes "1".

(26) SKBI

The contents of the memory digit address counter BL are compared with the operand I.sub.A and a next succeeding program step is skipped when there is agreement.

(27) SKAI

The contens of the accumulator ACC are compared with the operand I.sub.A and if both are equal to each other a next program step is skipped.

(28) SKAM

The contents of the accumulator ACC are compared with the contents of the RAM and if both are equal a next program step is skipped.

(29) SKN.sub.1

When the input KN.sub.1 is "0", a next program step is skipped.

(30) SKN.sub.2

When the input KN.sub.2 is "0", a next program step is skipped.

(31) SKF.sub.1

When the input KF.sub.1 is "0", a next program step is skipped.

(32) SKF.sub.2

When the input KF.sub.2 is "0", a next program step is skipped.

(33) SKAK

When the input AK is "1", a next program step is skipped.

(34) SKTAB

When the input TAB is "1", a next program step is skipped.

(35) SKFA

When the flag flip flop F/A assumes "1" a next program step is skipped.

(36) SKFB

When the flag flip flop F.sub.B assumes "1", a next program step is skipped.

(37) WIS

The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position) receiving "1".

(38) WIR

The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position being loaded with "0".

(39) NPS

The output control F/F N.sub.p for the buffer register W is set ("1" enters).

(40) NPR

The buffer register output control flip flop N.sub.p is reset ("0" enters therein).

(41) ATF

The contents of the accumulator ACC are transferred into the output buffer register F.

(42) LXA

The contents of the accumulator ACC are unloaded into the temporary register X.

(43) XAX

The contents of the accumulator ACC are exchanged with the contents of the temporary register X.

(44) SFA

The flag F/F FA is set (an input of "1").

(45) RFA

The flag F/F FA is reset (an input of "0").

(46) SFB

The flag flip flop F.sub.B is set (an input of "1").

(47) RFB

The flag flip flop F.sub.B is reset (an input of "0").

(48) SFC

An input testing flag F/F F.sub.C is set (an input of "1").

(49) RFC

The input testing flag F/F F.sub.C is reset (an input of "0").

(50) SKB

When an input .beta. is "1", a next program step is skipped.

(51) KTA

The inputs k.sub.1 -k.sub.4 are introduced into the accumulator ACC.

(52) STPO

The contents of the accumulator ACC are sent to the stack register SA and the contents of the temporary register X to the stack register SX.

(53) EXPO

The contents of the accumulator ACC are exchanged with the stack register SA and the contents of the temporary register X with the stack register SX.

(54) TML

The contents of the program counter P.sub.L incremented by one are transferred into the program stack register SP and the operand I.sub.A into the program counter P.sub.L.

(55) RIT

The contents of the program stack register SP are transmitted into the program counter P.sub.L.

Table 2 sets forth the relationship between the operation codes contained within the ROM of the CPU structure and the operand.

Taking an example wherein the output of the read only memory ROM is 10 bit long, the instructoin decoder DC.sub.5 decides whether the instruction AD or COMA (see TAble 1) assumes "0001011000" or "0001011111" and develops the control instructions 23 , 26 , or 27 . SKBI is identified by the fact that the upper six bits assume "000110", the lower 4 bits "0010" being treated as the operand I.sub.A and the remaining ninth and tenth bits "11" as the operand I.sub.B. The operand forms part of instruction words and specifies data and addresses for next succeeding instructions and can be called an address area of an instruction.

Major processing operations (a processing list) of the CPU structure will now be described in sufficient detail.

(I) A same numeral N is loaded into a specific region of the memory RAM (NNN.fwdarw.X)

(II) A predetermined number of different numerals are loaded into a specific region of the memory (N.sub.1, N.sub.2, N.sub.3, . . . .fwdarw.X)

(III) The contents of a specific region of the memory are transferred into a different region of the memory (X.fwdarw.Y)

(IV) The contents of a specific region of the memory are exchanged with that of a different region (X.crclbar.Y)

(V) A given numeral N is added or subtracted in a binary fashion from the contents of a specific region of the memory (X.+-.N)

(VI) The contents of a specific region of the memory are added in a decimal fashion to the contents of a different region (X.+-.Y)

(VII) The contents of a specific region of the memory are one digit shifted (X right, X left)

(VIII) A one bit conditional F/F associated with a specific region of the memory is set or reset (F set, F reset)

(IX) The state of the one bit conditional F/F associated with a specific region of the memory is sensed and a next succeeding program address is changed according to the results of the state detection.

(X) It is decided whether the digit contents of a specific region of the memory reach a preselected numeral and a next succeeding program step is altered according to the results of such decision.

(IX) It is decided whether the plural digit contents of a specific region of the memory are equal to a preselected numeral and a program step is altered according to the results of the decision.

(XII) It is decided whether the digit contents of a specific region of the memory are smaller than a given value and a program step to be next executed is changed according to the decision.

(XIII) It is decided whether the contents of a specific region of the memory are greater than a given value and the results of such decision alter a program step to be next executed.

(XIV) The contents of a specific region of the memory are displayed. (XV) What kind of a key switch is actuated is decided.

The above processing events in (1)-(15) above are executed according to the instruction codes step by step in the following manner.

The foregoing is the description of the respective major processing events in the CPU architecture.

By reference to a flow chart of FIG. 6 an example of the display operation of a calculator implementing the display device according to the preset invention will now be described in detail.

In FIG. 6, n.sub.1 represents the step of executing operations programmed by the operator and n.sub.2 the step of checking if the calculator is in a halt. Unless the calculator is in a halt n.sub.1 .revreaction.n.sub.2 are repeated. The halt condition used herein means that a particular calculation comes to a halt until data are entered at the step of entering data from outside of the calculator on the way of executing the particular calculation. If the halt condition is reached, n.sub.2 .fwdarw.n.sub.3 so that a given value N.sub.1 is sent to a counter CO which is built in a specific region of RAM. During the step n.sub.4 the results MX of calculations (or running results) are displayed. The step n.sub.5 is effected to check if the count of the counter CO is "0". If CO.noteq.0, then the step n.sub.6 is effected to subtract "1" from the count of the counter CO. In other words, a cycle of the steps n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub. 6 .fwdarw.n.sub.4 .fwdarw.n.sub.5 .fwdarw.is repeated N.sub.1 +1 times, displaying MX for a given period of time (say, 5 sec). Thereafter, when the count of the counter CO reaches "0", n.sub.5 .fwdarw.n.sub.7 to add "1" to a counter R which is part of RAM.

Assume now that the counter R is reset to "0". R contains the recoveries of the halt condition. During n.sub.8 suppress codes CS are loaded into a character memory MC which occupies a specific region of RAM and contains characters each having 8 bit codes. The purpose of the suppress codes CS is to keep the display from displaying anything, for example, encoded as "11111111". During n.sub.9 the character generator MC is allowed to contain codes indicative of "DE (.tau.)" at its first digit position. n.sub.10 is then executed to load the count of a program counter P.sub.L within ROM plus "1" into the program stack register SP. cf. the instruction code No. 54 which is to specify its home address with the aid of the return RIT instruction No. 55. Then, n.sub.10 .fwdarw.n.sub.26 to load a given value N.sub.2 into the counter CO within RAM. During n.sub.27 the contents of the character generator MC are displayed. n.sub.28 follows to check if the count of the counter CO reaches "0" and if CO.noteq.0 the step n.sub.29 tekes place to subtract "1" from the count of the counter CO. Whether there is any key input applied is decided during n.sub.30 and in the absence of any key actuation the steps are linked as n.sub.30 .fwdarw. n.sub.27. In other words, a chained cycle of n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.29 .fwdarw.n.sub.30 .fwdarw.n.sub.27 and so on is repeated N.sub.2 +1 times, in which case the displaying operation goes on for a given length of time. After that n.sub.28 .fwdarw.n.sub.31, thus shifting the visual display of the contents of the character memory MC to the left by the one digit length. The step n.sub.32 is to determine whether the conditional F/F A (part of RAM) is in the set or reset state. F/F A is set during n.sub.35 after all data are stored into the character memory MC, thus deciding whether the display of the data (FIGS. 2(b) through 2(f)) has been completed. In this instance, with F/F A in the reset state, n.sub.32 .fwdarw.n.sub.33 and then step n.sub.11 is reached through the return (RIT) instruction. The step n.sub.11 corresponds to the count of the program counter P.sub.L in ROM stored pursuant to the TML instruction at n.sub.10. In this manner, the visual display indicative of "DE ()" is completed as viewed from FIG. 2(b) through the steps n.sub.9 .fwdarw.n.sub.10 .fwdarw.n.sub.26 .fwdarw.n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.27 .fwdarw.n.sub.30 .fwdarw.n.sub.27 .fwdarw.n.sub.28 . . . .fwdarw.n.sub.31 .fwdarw.n.sub.32 .fwdarw.n.sub.33. A sequence of the operating steps n.sub.11 .fwdarw.n.sub.12 .fwdarw.n.sub.26 .fwdarw.n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.29 .fwdarw.n.sub.30 .fwdarw.n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.31 .fwdarw.n.sub.32 .fwdarw.n.sub.33 provides a visual display of "DEH ( )" as shown in FIG. 2(c). Likewise, a sequence of the operating steps of n.sub.15 .fwdarw.n.sub.16 .fwdarw.n.sub.26 .fwdarw. n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.29 n.sub.30 .fwdarw.n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.31 .fwdarw.n.sub.32 .fwdarw.n.sub.33 provides a visual display of "DEHTA (- )".

Subsequently, the step is advanced from n.sub.33 to n.sub.17 to store the step to be returned through the RIT instruction and n.sub.17 .fwdarw.n.sub.38 to monitor the count of the counter R.

When R=1 particularly under the first halt condition at n.sub.7, n.sub.38 .fwdarw.n.sub.44 to allow the character memory MC to contain at its first digit position codes indicative of "A". Through the developments of n.sub.44 .fwdarw.n.sub.45 .fwdarw.n.sub.18, the step n.sub.19 to be returned through the return instruction is recalled, followed by the step n.sub.26. Therefore, a visual display of "DEHTA A (- A)" is provided through n.sub.44 .fwdarw.n.sub.45 .fwdarw.n.sub.18 .fwdarw.n.sub.26 .fwdarw.n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.29 .fwdarw.n.sub.30 .fwdarw.n.sub.27 .fwdarw.n.sub.28 .fwdarw.n.sub.31 .fwdarw.n.sub.32 .fwdarw.n.sub.33.

In the foregoing manner, the contents of the character memory are visually displayed while the contents of the character memory are progressively shifted and a new character to be displayed is loaded into its first digit position, as viewed from FIGS. 2(b) through 2(f). After the display is completed as indicated in FIG. 2(f), the step n.sub.35 becomes operative through the return instruction, in which the conditional F/F A is forced into the set state. During the next step n.sub.36 the suppress codes CS are contained at the first digit position of the character generator MC, which codes establishes a boundary between different two displaying contents. The step n.sub.37 is carried out to decide whether the overall digits within the character generator MC assume the suppress codes CS. The decision as to MC=CS is aimed at beginning the display operation with the head of the contents to be displayed after the overall digits are shifted off on the display panel. Since in this case the overall digit assume no suppress codes, n.sub.37 .fwdarw.n.sub.26 to enable a display as shown in FIG. 2(g). Thereafter, the contents of the character memory are shifted during n.sub.31 and allowed to contain the suppress codes during n.sub.36. As a result, the displaying contents are gone from the extreme left end of the display panel. Provided that the memory character is filled completely with the suppress codes, n.sub.36 .fwdarw.n.sub.37 .fwdarw.n.sub.9 to repeat the display operation. In other words, "DEHTA A WO IREYO ( A and INSERT DATA A in its English version)" is visually repeatedly displayed.

Since the operator has completed the program for the calculation at the step n.sub.1 under these circumstances, he then inserts the data A via the keys. The step n.sub.30 recognizes that there has actually been the key input, returning to the steps n.sub.1. The calculation routine is reopened with the step n.sub.1 according to the newly keyed data.

Then, if the calculator comes to a halt again, then n.sub.2 n.sub.3 and the instantaneous calculation results are displayed for a given length of time via the chained steps of n.sub.4 .fwdarw.n.sub.5 .fwdarw.n.sub.6 .fwdarw.n.sub.4 in the same way as in the first halt condition. "1" is added to the counter R during n.sub.7. In this case R=2. Likewise the first halt condition the same steps are repeated up to n.sub.17, followed by n.sub.38 .fwdarw.n.sub.39 .fwdarw.n.sub.43 in which codes representative of "B" are loaded into the character memory MC during n.sub.43. Therefore, "DEATH B WO IREYO (INSERT DATA B in its English version)" is displayed under the second halt condition. Similarly, "DEHTA C WO IREYO (INSERT DATA C in its English version)" is displayed under the third halt condition and "DEHTA D WO IREYO" under the fourth halt condition.

FIG. 7 is a flow chart of a subroutine ##STR46## shown in FIG. 6. The conditional F/F B (part of RAM) is reset during the step n.sub.a and the contents of the character memory MC are 4 bits shifted to the left during the step n.sub.b. The step n.sub.c is effected to monitor the state the flip flop B, followed by the step n.sub.d of setting the flip flop B. During the step n.sub.b the character memory MC is shifted 4 bits to the left again. This subroutine ends with the next succeeding monitoring of the flip flop B. Since each of the characters contained within the character memory MC has 8 bits, MC is shifted one character by repeating the 4 bit long shift operation twice.

It is obvious that the respective processing events depicted in FIGS. 6 and 7 can be executed according appropriate subcombinations of the above defined functional operations accomplished by the CPU architecture. Table 3 shows the relationship between the processing events depicted in FIG. 6 and the functional operations accomplished by the CPU architecture. The processing list numbers correspond to the above described functional procedures (I) through (XV).

As is clear from Table 3, the respective steps in FIG. 6 are accomplished by the functional operations of the CPU architecture. The steps n.sub.1, n.sub.10, n.sub.12, n.sub.14, n.sub.16 -n.sub.18, n.sub.20, n.sub.22, n.sub.24, n.sub.33 and n.sub.34 are easily understood from the disclosure of the CPU architecture.

Table 4 depicts the relationship between the respective steps of shifting the character memory MC to the left and the functional operations of the CPU architecture.

Similarly, the MC left shift operation can be accomplished by the respective steps as is clear from Table 4.

As noted earlier, the present invention makes the CPU architecture which interprets and executes the various instructions, available for the displaying purposes in electronic calculators and so forth.

Whereas the present invention has been described with respect to a specific embodiment, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.