Electronic Musical Instrument for Tone Formation by Selectable Tone Synthesis Computations

This invention relates to an electronic musical instrument and, more particularly, to a digital type electronic musical instrument capable of producing tone signal waves by calculation under algorithms wherein different set of computations provide different kinds of tone (properties, e.g., different tone colors).

In a prior art electronic musical instrument of a type wherein tone signals (or tone source signals) are produced by implementing a predetermined algorithm, this algorithm is a fixed one and tones of various tone colors are produced by this fixed algorithm. In an electronic musical instrument employing a frequency modulation technology, for example, a basic algorithm is implemented by the following equation (1);

where A(t) is a coefficient determining magnitude of the amplitude of a calculated waveform (i.e. envelope amplitude), I(t) is a coefficient determining depth of the modulation (modulation index), n.sub.1 .omega. and n.sub.2 .omega. are angular velocities respectively determining the frequency of the carrier and that of the modulating wave, which angular velocities correspond to the tone pitch of a depressed key.

In this type of electronic musical instrument, algorithm is also implemented by the following equation (2) which is so to speak a multi-series application of the equation (1). ##EQU1## where A.sub.k (t), I.sub.k (t), n.sub.1k .omega., n.sub.2k .omega. are the same as A (t), I(t) n.sub.1 .omega. and n.sub.2 .omega. for every k=1, 2, 3, . . . , m.

The algorithm is also implemented by the following equation (3) which is obtained by turning the equation (1) to polynominal (multi-term fashion): ##EQU2## where A(t), I.sub.k (t), n.sub.1 .omega., n.sub.2k .omega. are the same as the above described values.

The algorithm in this type of electronic musical instrument is also implemented by the following equation (4) which is obtained by nesting the equation (1):

in which a subjected to frequency modulation in a double mode. A(t), I.sub.1 (t), I.sub.2 (t), n.sub.1 .omega., n.sub.2 .omega. and n.sub.3 .omega. are the same values as those described above.

Although there have been proposed various devices for producing tones by implementing algorithm described above, each of these devices can carry out only one of the described algorithms, i.e. only a fixed type algorithm peculiar to the device.

It should be noted, however, that harmonic spectra of tone signals obtained by implementation of the above described algorithms are different from one another so that no single one of the algorithms can achieve production of all kinds of tone colors (tone properties). For example, a tone signal produced by implementation of calculation in accordance with the equation (1) is suited for synthesis of certain particular tone colors but not for synthesis of other tone colors. The same is the case with a tone signal produced by implementation of the equation (2), (3) or (4).

Accordingly, the prior art devices which employ a fixed algorithm (i.e. only one kind of algorithm) have limitation in the range of tone color (tone properties) produced by the device with a result that sufficient variety in the tone color can hardly be obtained.

It is, therefore, an object of the present invention to provide an electronic musical instrument capable of generating tone signals which are most suited for respective selected kinds of tones (of selected properties by implementing computation under selected one of different algorithms according to the selection of tone kind (typically a tone color) and thereby imparting variety to the produced tone.

According to the present invention, algorithm of a tone signal forming circuit is sequentially controlled in accordance with algorithm control data stored in an algorithm or computation control circuit in correspondence to respective tone colors (properties). The tone signal forming circuit comprises arithmetic circuits composed of memories, adders, multipliers etc. which are connected to one another through gates or latch circuits. Each of the gates (or latch circuits) is sequentially controlled by algorithm control data outputted by the algorithm control circuit. The tone signal forming circuit implements computation in accordance with combination of the arithmetic circuits which combination is determined by the algorithm control data. In an electronic musical instrument employing a key assigner and thereby being capable of producing a plurality of tone simultaneously, the computation is carried out within one channel time of the key assigner. If, for example, this computation is carried out by calculation of six steps, the algorithm control circuit outputs algorithm control data of six steps within one channel time.

A preferred embodiment of the invention will now be described in conjunction with the accompanying drawings.

In the Drawings,

FIG. 1 is a block diagram showing an embodiment of the invention;

FIG. 2 is a block diagram showing an example of a circuit which generates clock pulses concerning the illustrated embodiment;

FIG. 3 is a block diagram showing an example of a time function generation circuit in detail;

FIG. 4 is a graph showing time relation between clock pulses .phi..sub.0, .phi..sub.1 and .phi..sub.2 ; and

FIG. 5 is a graph showing contents stored in an algorithm control data generation circuit.

Referring to FIG. 1 which shows an embodiment of the present invention in the form of a block diagram, various algorithms performed in accordance with the frequency modulation system are controlled by 4-bit algorithm control data L.sub.1 -L.sub.4 outputted by an algorithm control data generation circuit 23.

A key depressed in a keyboard 1 is detected by the key assigner 2. The key assigner 2 has tone production channels corresponding to a maximum number of tones to be produced simultaneously (e.g. twelve), assigns a key code KC representing the detected key to one of the available tone production channels and delivers out the assigned key code KC as a time division multiplexed signal with the channel times corresponding to the respective channels being used as time slots for the time division multiplexed signal. This key assigner 2 is driven by the clock pulse .phi..sub.1 and the above described channel time corresponds to the period of this clock pulse .phi..sub.1. The clock pulse .phi..sub.1 is obtained, as shown in FIG. 2, from a final stage of an 8stage ring counter 26 to which a master clock pulse .phi..sub.0 generated by a clock pulse generation circuit 25 is applied. One shot of the clock pulse .phi..sub.1 is generated for every eight shots of the master clock pulses .phi..sub.0. As the key assigner 2 has assigned a key code KC representing the depressed key to any of the tone production channels, the key assigner 2 outputs a key-on pulse KP of a predetermined pulse width at the channel time corresponding to the tone production channel to which the key code KC has been assigned.

The time division key codes KC outputted by the key assigner 2 using the respective channel times as time slots are applied to a phase angle data generation circuit 3. The phase angle data generation circuit 3 outputs, upon receipt of the time division key code KC, a signal representing a phase angle .omega.t corresponding to each key code KC also as a time division signal. This phase angle data generation circuit 3 can be composed of a read-only memory (ROM) storing frequency information .omega. and utilizing the key code KC as address signal and an accumulator circuit accumulating the outputs of this read-only memory in response to a preset clock.

A tone color selection circuit 20 outputs a tone color selection signal TC representing a tone color selected from tone colors TC.sub.1 -TC.sub.n. This circuit 20 is driven by a suitable means such as a tone selection switch (not shown).

A time function generation circuit 24 receives the time division key-on pulse KP generated by the key assigner 2 and using the respective channel times as time slots and thereupon generates time function t(t=0 through t=m) corresponding to the key code KC which has been assigned to the respective channels. The time function t represents lapse of time required for forming a tone signal corresponding to the key code KC assigned to the respective channels. The envelope is developed in accordance with the time function t and the time point when the key-on pulse KP appears is designated by time function t=0 and the time point when the envelope finishes by time function t=m. The time function generation circuit 24 can be composed, for example, of a circuit as shown in FIG. 3. In FIG. 3, a time number memory 28 consists, for example, of a read-only memory which stores predetermined numerical data (i.e. time number T) using the tone color selection signal TC as an address signal. The time number memory 28 provides a predetermined time number T in response to the applied tone selection signal TC. This time number T determines a speed at which the time function t proceeds. As the time number T increases, this speed increases and vice versa. The time number T read from the time number memory 28 is applied to an adder 29.

The output of the adder 29 is applied to a 12-stage/y-bit shift register 31 driven by the clock pulse .phi..sub.1 through a gate circuit 30 which is gated by a signal obtained by inverting the key-on pulse KP supplied by the key assigner 2 by an inverter IN. The output of the final stage of this shift register 31 constitutes another input signal to the adder 29. Alternatively stated, the adder 29, the gate 30 and the shift register 31 constitute an accumulator which accumulate the time number T supplied by the time number memory 28 in a time sharing fashion. The key-on pulse KP is utilized as a clear signal for clearing the contents of the accumulator. If, for instance, the key code KC representing the depressed key assigner 2 has been assigned to a certain channel and thereupon the key-on pulse KP has been generated at a channel time corresponding to this channel, contents of the shift register corresponding to this channel are cleared in response to this key-on pulse KP and subsequently the accumulator consisting of the adder 29, the gate 30 and the shift register 31 accumulates the time number T provided by the time number memory 28 at each clock pulse .phi..sub.1. The shift register 31 provides an accumulated value at a corresponding time slot. Thus, the accumulated value outputted by the shift register 31 at a time slot of a corresponding channel time constitutes the time function t. For this time function t, all output bits of the shift register 31 need not be used but only a part of bits counted from the most significant bit may be used. When the result of accumulation of the time number T provided by the time number memory 28 has reached a value in which all bits are "1", an AND gate AN inputs of which are connected to all of the output bits of the shift register 31 is enabled at a channel time corresponding to this channel and a signal "1" is outputted by the AND gate AN. This output of the AND gate AN (i.e. "1") is fed to the key assigner 2 as a decay finish signal DF showing the end of the envelope.

A pitch data generation circuit 21 delivers out pitch data Ki (i=1 to 8) to be used for computation of a tone signal as will be described later in response to a tone color selection signal TC generated by the tone selection circuit 20, the time function t generated by the time function generation circuit 24 and synchronizing signal SY.sub.1 -SY.sub.8. The synchronizing signals SY.sub.1 -SY.sub.8 are provided by parallel outputs of an 8-stage ring counter 26 driven by the output .phi..sub.0 of a clock pulse generator 25 as shown in FIG. 2. Chronological relationship between the synchronizing signals SY.sub.1 -SY.sub.8 and the clock pulse .phi..sub.1 used for defining channel times is shown in FIG. 4. Each of the synchronizing signals SY.sub.1 -SY.sub.8 has a time slot which is obtained by dividing a time slot defined by the clock pulse .phi..sub.1 by eight. The pitch data generation circuit 21 is composed of a read-only memory accessed by the tone selection signal TC, the time function t and the synchronizing signals SY.sub.1 -SY.sub.8.

An envelope signal generation circuit 22 also is composed of a read-only memory accessed by the tone selection signal TC, the time function t and the synchronizing signals SY.sub.1 -SY.sub.8. The circuit 22 outputs an envelope signal A.sub.i (i=1 to 8) used for computation of the tone signal in response to the tone selection signal TC, the time function t and the synchronizing signals SY.sub.1 -SY.sub.8.

A computation or algorithm control data generation circuit 23 receives the tone selection signal Tc, the time function t and the synchronizing signal SY.sub.1 -SY.sub.8 and thereupon outputs 4-bit algorithm or computation control data L.sub.1 -L.sub.4 which determines contents of computation for forming a tone signal. Like the above described pitch data generation circuit 21 and the envelope signal generation circuit 22, the circuit 23 is composed of a read-only memory accessed by the tone selection signal TC, the time function t and the synchronizing signals SY.sub.1 -SY.sub.8. Contents stored in the circuit 23 are diagrammatically shown in FIG. 5. This read-only memory has addresses corresponding to the respective tone colors TC.sub.1 -TC.sub.n and each of these addresses is divided into addresses t=0 to t=m corresponding to the time function t. The respective addresses t=0 to t=m store algorithm control data L.sub.1 -L.sub.4 corresponding to the synchronizing signals SY.sub.1 -SY.sub.8.

The following Table 1 shows an example of the algorithm control data L.sub.1 -L.sub.4.

In accordance with the algorithm control control data L.sub.1 -L.sub.4 shown in Table 1, the computation by the following equation (5) is implemented:

Assuming that the algorithm control data L.sub.1 -L.sub.4 shown in Table 1 is outputted by the algorithm control circuit 23, description of the following circuit is made with respect only to a specific channel time.

At the time slot of the synchronizing signal SY.sub.1, pitch data K.sub.1 is generated by the pitch data generation circuit 21, an envelope signal A.sub.1 is generated by the envelope signal generation circuit 22 and algorithm control data (L.sub.1 -L.sub.4) "1000" in which the signal L.sub.1 only is "1" is generated by the algorithm control data generation circuit 23.

A signal outputted by the phase angle data generation circuit 3 and representing a phase angle .omega.t corresponding to the frequency of a tone for a depressed key is applied to a multiplier 6. To the multiplier 6 is also applied from the pitch data generation circuit 21 the pitch data K.sub.1 which is synchronized with the synchronizing signal SY.sub.1 so that the multiplier 6 multiplies the phase angle .omega.t with the pitch data K.sub.1 and outputs a product K.sub.1 .omega.t. This value K.sub.1 .omega.t is applied to an adder 7. Since at this time no signal has yet been applied to another input of the adder 7, this value K.sub.1 .omega.t is applied directly to a sinusoidal wave function memory 8 from the adder 7 and a corresponding sinusoidal wave function value sin K.sub.1 .omega.t thereby is read out. This value sin K.sub.1 .omega.t read from the sinusoidal wave function memory 8 is applied to a multiplier 9 where it is multiplied with the envelope signal A.sub.1 outputted by the envelope signal generation circuit 22. The product A.sub.1 sin K.sub.1 .omega.t is applied to an adder 10. No signal has yet been applied to another input of the adder 10 at this time so that the value A.sub.1 sin K.sub.1 .omega.t is directly loaded from the adder 10 to a register 4 driven by the clock pulse .phi..sub.0 through a gate circuit 5 gated by the signal L.sub.1.

At the time slot of the synchronizing signal SY.sub.2, the pitch data generation circuit 21 generates pitch data K.sub.2, the envelope signal generation circuit 22 provides the envelope signal A.sub.2 and the algorithm control data generation circuit 23 provides the algorithm control data (L.sub.1 -L.sub.4) "0010" in which the signal L.sub.3 only is "1". The multiplier 6 thereupon multiplies the phase angle .omega.t provided by the phase angle data generation circuit 3 with the pitch data K.sub.2 provided by the pitch data generation circuit 3, supplying a product K.sub.2 .omega.t to the adder 7. At this time the value A.sub.1 sin K.sub.1 .omega.t loaded in the register 4 is applied to another input of the adder 7. Accordingly, the adder 7 adds the value K.sub.2 .omega.t. The output value (K.sub.2 .omega.t+A.sub.1 sin .omega.t) of the adder 7 is applied to the sinusoidal wave memory 8 to read out a corresponding sinusoidal wave function value sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t). The sinusoidal wave function value sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t) is multiplied in the multiplier 9 with the envelope signal A.sub.2 from the envelope signal generation circuit and a product A.sub.2 sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t) is multiplied in the multiplier 9 with the envelope signal A.sub.2 from the envelope signal generation circuit and a product A.sub.2 sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t) is applied to an adder 13 through the adder 10 which has received no signal at another input thereof. At this time, the adder 13 has not yet received a signal at another input thereof. Accordingly, the adder 13 directly delivers out the value A.sub.2 sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t) applied thereto and this value is loaded in a latch circuit 14 in response to the signal L.sub.3.

At the time slot of the synchronizing signal SY.sub.3, the pitch data generation circuit 21 generates pitch data K.sub.3, the envelope signal generation circuit 22 an envelope signal A.sub.2 and the algorithm control data generation circuit 23 algorithm control data (L.sub.1 -L.sub.4) "1000" in which the signal L.sub.1 only is "1". At this time slot, the algorithm control data L.sub.1 -L.sub.4 is the same as that produced at the time slot of the synchronizing signal SY.sub.1 so that the same computation as that performed at the time slot of the synchronizing signal SY.sub.1 is performed. More specifically, the multiplier 6 multiplies the phase angle .omega.t from the phase angle generation circuit 3 with the pitch data K.sub.3 from the pitch data generation circuit 21 and applied a product K.sub.3 .omega.t to the sinusoidal wave function memory 8 to read out a corresponding sinusoidal wave function value sin K.sub.3 .omega.t. The multiplier 9 multiplies this sinusoidal wave function value with the envelope signal A.sub.3 generated by the envelope signal generation circuit 22 and a product A.sub.3 sin K.sub.3 .omega.t is loaded in the register 4 through the adder 10 and the gate circuit 5 gated by the signal L.sub.1.

At the time slot of the synchronizing signal SY.sub.4, the pitch data generation circuit 21 generates pitch data K.sub.4, the envelope signal generation circuit 22 the envelope signal A.sub.4, and the algorithm control data generation circuit 23 algorithm control data (L.sub.1 -L.sub.4) "0001" in which the signal L.sub.4 is "1". At this time slot, the multiplier 6 multiplies the phase angle .omega.t from the phase angle data generation circuit 3 with the pitch data K.sub.4 from the pitch data generation circuit 21. Then the product K.sub.4 .omega.t and the value A.sub.3 sin K.sub.3 .omega.t stored in the register 4 at the time slot of the synchronizing signal SY.sub.3 are added together in the adder 7. The output value (K.sub.4 .omega.t+A.sub.3 sin K.sub.3 .omega.t) of the adder 7 is applied to an address input of the sinusoidal wave function memory 8 to read out a corresponding sinusoidal wave function value sin (K.sub.4 .omega.t+A.sub.3 sin K.sub.4 .omega. t). The output of the memory 8 is multiplied with the envelope value A.sub.4 by the multiplier 9 and the product A.sub.4 sin (K.sub.4 .omega.t+A.sub.3 sin K.sub.3 .omega.t) is applied to an adder 13 through the adder 10. The adder 13 receives at the other input thereof the value A.sub.2 sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t) which was loaded in a latch circuit 14 by the signal L.sub.3 at the time slot of the synchronizing signal SY.sub.2. Accordingly, the adder 13 adds these values together to produce a value A.sub.2 sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t)+A.sub.4 sin (K.sub.4 .omega.t+A.sub.3 sin K.sub.3 .omega.t). This output value of the adder 13 is loaded in a latch circuit 15.

Thus, the signal e(t)=A.sub.2 sin (K.sub.2 .omega.t+A.sub.1 sin K.sub.2 .omega.t)+A.sub.4 sin (K.sub.4 .omega.t+A.sub.3 sin K.sub.3 .omega.t) loaded in the latch circuit 15 by computation in accordance with the algorithm control data L.sub.1 -L.sub.4 from the algorithm control data generation circuit 23 is stored in an accumulator 16.

A similar computation is carried out at each channel time and a result of computation for each channel time is stored in the accumulator 16. The results of computation with respect to the first through twelfth channels stored in the accumulator 16 are in turn loaded in a latch circuit 17 at a timing of a clock pulse .phi..sub.2. The clock pulse .phi..sub.2 is provided from a final stage of a 12-stage ring counter 27 which is driven by the clock pulse .phi..sub.1 defining each channel time as shown in FIG. 2. One shot of the clock pulse .phi..sub.2 is produced at every twelve shots of the clock pulse .phi..sub.1. The accumulator 16 is cleared by a signal obtained by delaying the clock pulse .phi..sub.2 by, for example, the clock pulse .phi..sub.0

The value stored in the latch circuit 17 is applied to a digital-to-analog converter (DAC) 18 where the value is converted to a corresponding analog signal. The above description has been made about an operation performed at a certain time point represented by the time function e.g. t=1, generated by the time function generation circuit 24. Similar computation is carried out in accordance with the time function t generated by the time function generation circuit 24 and, accordingly, an analog signal which varies with the time function t is produced by the digital-to-analog converter 18. The analog signal outputted by the digital-to-analog converter 18 in the above described manner is applied to a sound system 19 for sounding of a musical tone.

The above description has been made with respect to a case wherein the algorithm control data L.sub.1 -L.sub.4 as shown in Table 1 is generated by the algorithm control data generation circuit 23. Description will now be made with respect to a case wherein algorithm control data L.sub.1 -L.sub.4 as shown in the following Table 2 is generated by the algorithm control data generation circuit 23.

By this algorithm control data L.sub.1 -L.sub.4, computation of the following equation (6) is implemented:

As a time slot of the synchronizing signal SY.sub.1, the pitch data generation circuit 21 generates pitch data K.sub.1, the envelope signal generation circuit 22 an envelope signal A.sub.1 and the algorithm control data generation circuit 23 algorithm control data (L.sub.1 -L.sub.4) "0100" in which the signal L.sub.2 is "1". This enables the gate 12. Accordingly, the output of the multiplier 6 which multiplies the phase angle .omega.t generated by the phase angle data generation circuit 3 with the pitch data K.sub.1 generated by the pitch data generation circuit 21 is applied to the sinusoidal wave function memory 8 through the adder 7 which has not received any signal at the other input thereof. A corresponding sinusoidal wave function value sin K.sub.1 .omega.t is read from the memory 8. This value is multiplied in the multiplier 9 with the envelope signal A.sub.1 generated by the envelope signal generation circuit 22 and the product A.sub.1 sin K.sub.1 .omega.t is loaded in the register 11 driven by the clock pulse .phi..sub.0 through the adder 10 which has not received any signal at the other input thereof and the gate 12 which has been enabled by the signal L.sub.2.

At a time slot of the synchronizing signal SY.sub.2, the pitch data generation circuit 21 generates pitch data K.sub.2, the envelope signal generation circuit 22 an envelope signal A.sub.2 and the algorithm control data generation circuit 23 algorithm control data (L.sub.1 -L.sub.4) "1000" in which te signal L.sub.1 is "1". Thereupon the gate 5 is enabled. A value A.sub.2 sin K.sub.2 .omega.t computed in the same manner as described above is applied to the adder 10 through the multiplier 6, the adder 7, the sinusoidal wave function memory 8 and the multiplier 9. The adder 10 adds the value A.sub.1 sin K.sub.1 .omega.t loaded in the register 11 at the time slot of the synchronizing signal SY.sub.1 and being presently applied to the other input of the adder 10 and the value A.sub.2 sin K.sub.2 .omega.t together and supplies the sum A.sub.1 sin K.sub.1 .omega.t+A.sub.2 sin K.sub.2 .omega.t to the register 4 through the gate 5.

At a time slot of the synchronizing signal SY.sub.3, the pitch data generation circuit 21 generates pitch data K.sub.3, the envelope signal generation circuit 22 an envelope signal A.sub.3 and the algorithm control data generation circuit 23 algorithm control data (L.sub.1 -L.sub.4) "0010" in which the signal L.sub.3 is "1". At this time slot, the value K.sub.3 .omega.t provided by the multiplier 6 and the value A.sub.1 sin K.sub.1 .omega.t+A.sub.2 sin K.sub.2 .omega.t which was loaded in the register 4 at the time slot of synchronizing signal SY.sub.2 are added together in the adder 7 and a corresponding sinusoidal wave function value sin (K.sub.3 .omega.t+A.sub.1 sin K.sub.1 .omega.t+A.sub.2 sin K.sub.2 .omega.t) is read from the sinusoidal wave function memory 8 in response to the sum of the addition in the adder 7. The read out value is multiplied in the multiplier 9 with the envelope signal A.sub.3 and the product A.sub.3 sin (K.sub.3 .omega.t+A.sub.1 sin K.sub.1 .omega.t+A.sub.2 sin K.sub.2 .omega.t) is loaded in the latch circuit 14 by the signal L.sub.3 through the adders 10 and 13.

At a time slot of the synchronizing signal SY.sub.4, the pitch data generation circuit 21 generates pitch data K.sub.4, the envelope signal generation circuit 22 an envelope signal A.sub.4 and the algorithm control data generation circuit 23 algorithm control data (L.sub.1 -L.sub.4) "1000" in which the signal L.sub.1 is "1". This enables the gate 5. Accordingly, a computed value A.sub.4 sin K.sub.4 .omega.t is loaded in the register 4 through the multiplier 6, adder 7, sinusoidal wave function memory 8, multiplier 9, adder 10 and gate 5.

At a time slot of the synchronizing signal SY.sub.5, the pitch data generation circuit 21 generates pitch data K.sub.5, the envelope signal generation circuit 22 an envelope signal A.sub.5 and the algorithm control data generation circuit 23 algorithm data (L.sub.1 -L.sub.4) "1000" in which the signal L.sub.1 is "1". This enables the gate 5. The output value K.sub.5 .omega.t of the multiplier 6 and the value A.sub.4 sin K.sub.4 .omega.t loaded in the register 4 at a time slot of the synchronizing signal SY.sub.4 are added together in the adder 7 and a corresponding sinusoidal wave function value sin (K.sub.5 .omega.t+A.sub.4 sin K.sub.4 .omega.t) is read from the sinusoidal wave function memory 8 in response to the sum of the addition in the adder 7. The read out value is multiplied with the envelope signal A.sub.5 in the multiplier 9 and the product A.sub.5 sin (K.sub.5 .omega.t+A.sub.4 sin K.sub.4 .omega.t) is loaded in the register 4 through the adder 10 and the gate 5.

At a time slot of the synchronizing signal SY.sub.6, the pitch data generation circuit 21 generates pitch data K.sub.6, the envelope signal generation circuit 22 an envelope signal A.sub.6 and the algorithm control data generation circuit 23 algorithm data (L.sub.1 -L.sub.4) "0001" in which the signal L.sub.4 is "1". At this time slot, the output value K.sub.6 .omega.t of the multiplier 6 and the value A.sub.5 sin (K.sub.5 .omega.t+A.sub.4 sin K.sub.4 .omega.t) which was loaded in the register 4 at the time slot of the synchronizing signal SY.sub.5 are added together in the adder 7 and a corresponding sinusoidal wave function value sin {K.sub.6 .omega.t+A.sub.5 sin (K.sub.5 .omega.t+A.sub.4 sin K.sub.4 .omega.t)} is read from the sinusoidal wave function memory 8 in response to the sum value K.sub.6 .omega.t+A.sub.5 sin (K.sub.5 .omega.t+A.sub.4 sin K.sub.4 .omega.t). This sinusoidal wave function value is applied to the multiplier 9 to be multiplied with the envelope signal A.sub.6. The product of the multiplication A.sub.6 sin {K.sub.6 .omega.t+A.sub.5 sin (K.sub.5 .omega.t+A.sub.4 sin K.sub.4 .omega.t)} is applied to the adder 13 through the adder 10. This value is added in the adder 13 to the value A.sub.3 sin (K.sub.3 .omega.t+A.sub.2 sin K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t) which was loaded in the latch circuit 14 at the time slot of the synchronizing signal SY.sub.3. The sum A.sub.3 sin (K.sub.3 .omega.t+A.sub.2 sin K.sub.2 .omega.t+A.sub.1 sin K.sub.1 .omega.t)+A.sub.6 sin {K.sub.6 .omega.t+A.sub.5 sin (K.sub.5 .omega.t+A.sub.4 sin K.sub. 4 .omega.t)} is loaded in the latch circuit 15 in response to the signal L.sub.4.

The above described operation is made within one channel time just as the operation performed in accordance with Table 1. An operation similar to the one described above is performed during each channel time and the result of computation for each channel stored in the latch circuit 15 is applied to the accumulator 16. Contents of the accumulator 16 are supplied, in the same manner as described above, to a sound system 19 through the latch circuit 17 operated by the clock pulse .phi..sub.2 and the digital-to-analog converter 18.

The above described operations are only few examples of various operations which the device according to the invention is capable of performing.

It will be understood that if a algorithm control data L.sub.1 -L.sub.4 as shown in the following Table 3 is produced in accordance with the synchronizing signals SY.sub.1 -SY.sub.8, an equation

is implemented whereby computation of "four series with one term modulation" can be carried out.

If algorithm control data L.sub.1 -L.sub.4 as shown in the following Table 4 is sequentially produced, an equation ##EQU3## is implemented.

In this case, computation for producing a musical tone is performed not in accordance with the above described FM system (i.e. Tables 1-3) but in accordance with the harmonic synthesis system.

The above described algorithm control data L.sub.1 -L.sub.4 is stored in the algorithm control data generation circuit 23 in correspondence to the tone colors TC.sub.1 -TC.sub.n in such a manner that each control data corresponds to optimum algorithm for a selected tone color. Accordingly, computation according to the optimum algorithm for the selected tone color is implemented whereby a tone signal which is most suited to the selected tone color (property) can be formed.

It should be noted that this invention is applicable to a case where computation for forming a tone signal is carried out by employing an equation other than the above described equations.

It should also be understood that the calculation circuit such as the adders and multipliers and manners of connecting the gates and latch circuits are not limited to those illustrated in FIG. 1 but modifications can be made where applicable.