Thin Film Metal Package for LSI Chips

1. Technical Field

This invention relates to packaging of LSI chips in high densities with improved electrical characteristics.

An object of this invention is to provide improved A. C. characteristics of packages for LSI chips in high density electronic systems.

Another object of this invention is to build decoupling capacitance into a packaging structure for LSI chips.

Still another object of this invention is inhibiting electrical noise generated in high speed computers by the simultaneous switching of large numbers of LSI circuits. This noise arises from the nonzero inductance, L, of the power supply network and is proportional to Ldi/dt where di is the total switched current with a risetime dt. The trend in future circuits is to reduce present risetimes as much as is practical.

A further object of this invention is to minimize inductance of the packaging structure and to provide increased capacitance to smooth out the associated voltage transients in a LSI system.

2. Background Art

U.S. Pat. No. 3,519,959 of Bewley et al describes a power distribution substrate with a number of parallel planar conductors for providing integral conductors and capacitors in a unit which is adapted to connect to a component board to which a number of electrical components are secured. The component board has an edge including a plurality of aligned pins which connect to a number of openings in the power distribution substrate where the planar conductors having apparently coaxial connections can contact the pins. However, the concept of securing integrated circuits directly to the planar conductors is not suggested.

Arnold et al "High Performance Power Distributor", 21, 1016-1018 (1978) teaches use of internal parallel power planes composed of printed circuits. It does not suggest elimination of decoupling capacitors by integrating capacitance into the structure or connection of integrated circuits to the power planes directly through vias, etc.

U.S. Pat. No. 3,189,847 of Rymaszewski commonly assigned provides an energy distribution system with decoupling characteristics which uses a number of parallel conductive patterns would helically ("spirally") about a dielectric from which contacts are provided along one edge.

U.S. Pat. No. 3,962,713 of Kendall et al shows formation of a capacitor upon a semiconductor wafer substrate by means of thin film techniques including etching the semiconductor and depositing the metal layers by techniques such as vacuum deposition upon a dielectric layer which was grown or deposited upon the semiconductor. A metal layer on the back of the wafer forms the other plate of the capacitor. Such a capacitor is shown upon the same wafer as a transistor and the capacitor is formed by a reverse biased PN junction.

In accompanying drawings forming a material part of this disclosure;

FIG. 1 is a sectional perspective view of a laminated packaging structure in accordance with this invention.

FIG. 2 is a similar view of FIG. 1 wherein an additional lamination layer added.

FIG. 3 is a sectional perspective view of a pair of laminated packaging structures in spaced superposition with a chip and a decoupling capacitor connected to the lower structure.

FIG. 4A shows a plan view of a lower conductive element of a liminated packaging structure in accordance with the instant invention.

FIG. 4B is a sectional view taken along line 4B--4B in FIG. 4A.

FIG. 4C is a bottom view of the conductive element shown in FIG. 4A.

FIG. 5A is a plan view of a mating upper conductive element adapted for insertion into the element of FIGS. 4A-C.

FIG. 5B is a sectional view taken along line 5B--5B in FIG. 5A--5A.

FIG. 5C is a bottom view of the conductive element of FIG. 5A.

The packaging structure shown in FIGS. 1 and 2 consists of two or three generally parallel metal carrier sheets 10 and 11 (FIG. 1) or 10, 21 and 22 (FIG. 2) which sheets, together with insulating dielectric layers 12 between them combine to form a carrier sandwich. Carrier sheets 10 and 11 or 10, 21 and 22 serve as power supply planes for conducting and connecting electrical power to the C-4 terminals of LSI chips 30 in FIG. 3, for example. Chip 30 is an example of a large array of chips. In FIG. 3 on top of one side of the lower metal carrier sandwich 33 a multimetal layer thin film structure provides a grid 14 of orthogonal interconnection wires. Where necessary they are connected to the power planes of the carriers by vias which are not shown. Connection to other devices is made over C-4 solder pads 15 (See P. A. Totta, R. P. Sopher, "SLM Device Metallurgy and Its Monolithic Extension", IBM Journal of Research and Development, May 1969, pp 226-238). The carrier is designed to carry C-4 solder pad-mounted flip-chips 30. The connection between two different carriers 32 and 33 or to the next packaging level can be performed by pins 15 and/or edge connectors, press contacts or soldering. The power is supplied over power rods 16 (FIG. 3) cables or thicker pins. A chip 30 and a bonded decoupling capacitor 31 are shown. A fragment of the next metal carrier sandwich 32 is shown above the lower sandwich, supported on rod 16.

The metal carrier can be made of any highly conductive metal or alloy, which is desirable from the point of view of cost and fabrication. Metal formed by injection molding is most desirable. Suitable metals are aluminum or its alloys, beryllium or its alloys, copper or its alloys, and molybdenum or its alloys. Considering solder pad techniques and the expansion coefficient of 2.6.times.10.sup.-6 /.degree.C. of silicon, molybdenum has a coefficient of 2.7.times.10.sup.-6 /.degree.C. which is the closest expansion coefficient to silicon, and therefore is a preferred metal.

Dielectric 12 between the metal carrier sheets (10 and 11 in FIG. 1 for example) of the carrier sandwich separates the sheets (power planes) electrically, and connects them mechanically. Dielectric 12 must have good adhesion to the metal or its oxide. Dielectric 12 also must tolerate solder temperatures. Dielectrics, such as, polyimide, polysulfone, polycarbonate or any other high temperature polymers provide such characteristics. Inorganic materials such as some glasses and ceramics are satisfactory. Several refractory metals can be covered by native oxides which adhere well. In general, adhesion of polymers to oxides is good. In those cases, an excellent bond occurs automatically. With aluminum and beryllium, metal oxides are used to insulate thin film lines on top of the carrier for use in integrated circuit techniques. These oxides can be produced either by anodization or by other deposition methods.

In case of an aluminum carrier the process steps to achieve the carrier structure are as follows: Single metal sheets, manufactured by machining or injection molding are coated with oxide by anodization. The dimensional tolerances for the power supply sheets take into account anticipated growth or shrinkage of each individual metal sheet from anodization. This allows for interleaving of the metal carrier sheets. Note that pads 40 comprise generally rectangular shapes in openings 41 in the upper surface of plane 10, with rounded ends 45. Similarly pad 42 comprises a generally rectangular shape in opening 43 in the lower surface of sheet 11, with rounded ends (not shown).

The metal carrier sheets 10 and 11 are insulated from each other for direct current by polymer 12 as well as the anodized Al.sub.2 O.sub.3. The relatively high dielectric constant of Al.sub.2 O.sub.3 between the metal sheets is favorable, because it increases the AC-coupling between the power supply planes 10 and 11, which act at the same time as a decoupling capacitor. In further processing steps if necessary, the surface is planarized by lapping so the surface topography meets the flatness requirements of following thin film interconnection layers.

The structure can include Al metallurgy and Al.sub.2 O.sub.3 as insulators as follows: After the carrier surface is planarized, an aluminum layer of about 50 .mu.m is deposited on top of a 200 A thick layer of Ta, Nb, Hf, etc., like Ti, Si. At this point studs are formed by selectively anodizing the Al in all areas except at contacts. The tantalum (Nb, Hf, Ti, etc.) under Al.sub.2 O.sub.3 is converted to niobium (Ta, Hf, Ti, etc.) oxide in a subsequent oxidation step. From a point of view of contact resistance it may be desirable to omit Nb, (Ta, Hf, Ti, etc.) from the contacts areas. In such a case a masking step can be used to remove Nb (Ta, Hf, Ti, etc.) from the contact prior to Al deposition.

Subsequent interconnection layers are built up by depositing an additional pair of Nb (Ta, Hf, Ti, etc.) and aluminum layers. This is followed by appropriate masking steps and selective anodizing to define the wiring pattern of the first layer of interconnection wires. As in the previous step, the niobium has to be converted to Nb (Ta, Hf, Ti) oxide.

Both the stud (or via) layers and conductor metallurgy layers are formed in the same manner except that the stud layers use different masks from the conductor layers. Thus, the Nb (Ta, Hf, Ti, etc.) and Al deposition, masking, anodization and heating steps are repeated as many times as is necessary to build up the desired number of interconnection layers.

Alternatively the required number of interconnection wire layers can be achieved through the use of polyimide and copper, polyimide and gold, Parylene (a trademark of Union Carbide Corporation) polyparaxylene film and copper and Parylene film and gold. The combination of a molybdenum carrier with polyimide as an insulator, and copper thin film wires in Parylene film (.epsilon.=3) as an insulator is a most promising high speed carrier approach. Both copper and gold would be electroplated or deposited by electroless means.

In FIG. 2, the upper carrier sheet 10 rests above intermediate carrier sheet 22, which in turn rests upon lowercarrier sheet 21. Separating the carrier sheets in the same way as in FIG. 1 are the layers 12 of dielectric material. The intermediate sheet 22 serves as a power plane with pads 52 extending up through sheet 10 in openings 51 in sheet 10 and pads 52' extending down through lower sheet 21 in openings 51' through sheet 21. In addition, lower sheet 21 also serves as a power plane and it has a pad 54 extending up through hole 53 through sheets 22 and 10 to the upper surface of sheet 10. Similarly, holes 73 are provided through sheets 22 and 21 so that pads 72 can extend through to the lower surface of sheet 21 from upper sheet 10 to permit connections to the upper sheet from below the sandwich of sheets.

In FIG. 4A, the lower conductive element 8 includes the lower conductive sheet 11 of FIG. 1 with the pads 40 (preferably with rounded ends not shown in FIGS. 4A and 6B for convenience of machining during manufacture) and openings 43 for accepting pads 42 (preferably with rounded ends not shown in FIGS. 5C and 6). In addition, near the periphery of the element 8 is located an array of apertures 50 for vias. The vias would comprise wires having substantially smaller diameters than the apertures 50. An alignment flange 57 is also provided about the edge of the element 8 for holding the upper element 10 shown in FIG. 5 which comprises the upper sheet 10. Alignment holes 52 are provided in the corners of the sheet 11 which are diagonally opposite for reception of projections 54 on the upper sheet in FIG. 5B and 5C. Alignment edges 53 are provided on the other diagonally opposed edges of the inner margin of flange 57 for holding or aligning edges 55 of plane 10. When FIG. 5A is superposed upon FIG. 4A as shown in FIG. 6, the upper sheet 10 is inserted into the area surrounded by flange 57 and the clearances are selected to be sufficient that the application of dielectric 12 prior to assembly of parts 8 and 10 together will afford uniform dielectric thickness and insulation of the members from one another. Note that each of pads 42 is inserted between two pads 40 in element 8.

This invention is adapted to packaging of large scale integration chips carrying electronic solid state circuits with low resistance and high capacitive coupling between the power supply conductors providing electrical power to the chips.

A salient objective in packaging circuits for future high speed computers is inhibiting of electrical noise from simultaneous switching of a large number of circuits. This noise arises from the non-zero inductance, L, of the power supply network and is proportional to L.DELTA.I/.DELTA.t, where .DELTA.I is the total switched current with a risetime .DELTA.t.

This noise is typically controlled in part by minimizing power supply inductance and in part by using decoupling capacitors which smooth out the associated voltage transients in the power supply networks. Future performance requirements suggest the need to provide "integrated capacitors" (minimum self and lead inductance) physically placed as closely as possible to the semiconductor chips.

While this specification illustrates and describes the preferred embodiments of the subject invention, it is to be understood that the invention is not limited to the precise implementation and construction details described herein. The right is reserved to all changes and modifications encompassed by the scope of the underlying invention as defined in the claims which follow.