Digital Information Indicating System

1. Field of the Invention:

The present invention relates to an information indication system, particularly to an information indication system for digitally indicating a continuously varying output such as the output of the measured light in the case of a camera.

2. Description of the Prior Art:

The recent advance in digital techniques has made digital indication in the field of information indication more and more popular. This concept is also applied in the indication of the exposure determining factor in photography and has, to some extent, been used for indicating the photographic information of a camera.

However, photographic information for a camera is indicated only after various kinds of the photographic data have been processed, mainly based upon the quantity of the measured light. Accordingly, indication information naturally varies when some variation takes place in the information of the measured light, such as the brightness of the object to be photographed.

Thus when the indication information is indicated by means of an indication means such as a seven-segmented unit which presents a superior response to the variation of the input information, the indicated value varies in response to the above mentioned continuously varying indication information so that the photographer can not visually follow the variation of the indication value. This is so because the indication value itself varies within a very short period as to leave an after-image. Thus, visually, the indication value flickers so that it is impossible to read out the indication value.

U.S. Pat. No. 3,872,483 and DOLS No. 2,435,903 disclose systems according to which indication is made at a certain determined period by enlarging the sampling period in order to avoid the above mentioned shortcoming. These systems are provided with a light measuring circuit for measuring the brightness of the object to be photographed, and A-D converting means for converting the output of the light measuring circuit into a digital quantity, a digital indication means for indicating the output of the A-D converter and a sampling circuit for actuating the A-D converter at a certain determined period in such a manner that the output of the light measuring circuit is converted into a digital value at a certain determined period and updated at a certain determined period. Accordingly, the analog-digital conversion is not carried out continuously but only at the certain determined period. Thus, even when during the pause of the analog-digital conversion, the output of the light measuring circuit varies abruptly so as to deviate largely from the output of the light measuring circuit when the output is converted into digital value, the output converted already into digital value presents the value obtained before the large variation. Thus, in the case of system for an automatic exposure camera with digital control for determining the exposure automatically by means of the output converted into digital value, the output converted into digital value presents the former value even though, as explained above, during the pause of the analog digital conversion the output of the light measuring circuit has varied. The exposure mechanism then, does not operate in accordance with the actual value of the measured light, and fails to obtain a correct exposure. During the pause of the analog digital conversion the indication itself presents the former value and the present instantaneous value can not be indicated until the output has been converted into a digital value after the certain determined period. Further the photographer who decides the exposure himself can not learn the variation immediately when, as explained above, during the pause of the analog digital conversion the output of the measured light varies widely. To repeat, the photographer is obliged to decide the exposure in accordance with the indication value before variation, setting an incorrect exposure condition. This is again disadvantageous.

Thus, the present invention is intended to offer a digital information indication system without the above mentioned shortcoming in accordance with which system the above mentioned flickering can be avoided while a large variation of the brightness of the object to be photographed from the indicated value within the above mentioned certain determined period is immediately detected so as to update the indication. The system is composed in such a manner that the analog-digital conversion is always carried out for the continuously varying information, the timing of the indication being controlled in such a manner that the output of the A-D converter is sampled at a certain determined period during which period the variation of the indication value can visually be followed. In the case of a variation from the indicated value being more than a certain predetermined value, the indication being varied independently of the above mentioned certain determined period.

A purpose of the present invention is to provide a digital information indication system free from the shortcoming of the conventional digital indication system.

Another purpose of the present invention is to provide a digital information indication system in accordance with which for abruptly varying information, the indication value is updated at a certain determined period while the information which deviates widely from the then indicated value is detected so as to immediately update the content of the indication independently of the update of the indication at the certain determined period.

Another purpose of the present invention is to provide a digital information indication system quite suitable as the digital information indication system for a camera.

Other further purposes of the present invention will be disclosed from the detailed explanation to be made below in accordance with the accompanying drawings.

FIG. 1 shows a block diagram of an embodiment of the digital information indicating system in accordance with the present information.

FIG. 2 shows time charts for explaining the operation of the embodiment of FIG. 1.

FIG. 3 shows a circuit diagram for showing a concrete circuit arrangement of the embodiment of FIG. 1.

FIGS. 4(a) and 4(b) show logic diagrams of the circuit diagram of the fuller adder means ADD of FIG. 3.

FIGS. 5(a) and 5(b) show logic diagrams of the circuit diagram of the full subtractor means SUB.sub.1 of FIG. 3.

FIG. 6 shows logic diagrams of the circuit diagram of the full subtractor means SUB.sub.2 of FIG. 3.

FIG. 7 shows logic diagrams of the circuit diagram of the full subtractor means SUB.sub.3 of FIG. 3.

FIG. 1 shows a block diagram of an embodiment of the digital information indicating system in accordance with the present invention, wherein the block "exp" is a conventional light measuring circuit consisting of a photovoltaic element, processing amplifiers and so on, designed so as to receive the light beam from the object to be photographed in such a manner that the circuit produces an analog electric quantity corresponding to the intensity of the light beam of the object to be photographed. AD is an analog-digital converting device for converting the analog electric quantity produced by exp. into a digital quantity. REG.sub.1 is the first register for storing the digital information (of 4 bits) coming from the above mentioned A-D converting device AD in parallel fashion, being synchronized with the trailing edge of the clock pulses .phi..sub.o coming from the pulse generating circuit CPG for producing clock pulses with a certain determined period. REG.sub.2 is the second register for storing the content of the above mentioned first register REG.sub.1, being synchronized with the trailing edge of a pulse at the terminal CP.sub.2. DEC is a decoder for decoding the output of the above mentioned second register REG.sub.2 for indication. DIS is an indication device for digitally indicating the digital information stored in the above mentioned second register in accordance with the output of the above mentioned decoder. Dref is the constant value setting circuit for producing a certain predetermined digital constant of 4 bits as a fluctuation tolerance value of the information not necessary, for correction for indication. ADD is the full adder means for producing the summation of the content of the above mentioned second register REG.sub.2 with the above mentioned digital constant at the terminal S. SUB.sub.1 is the full subtractor means for subtracting the above mentioned constant value from the above mentioned second register REG.sub.2 so as to produce the result at the terminal G. SUB.sub.2 is the full subtractor means for subtracting the content of the first register 1 from the output information at the terminal S of the above mentioned full adder means ADD so as to produce a high level output at the terminal B.sub.2 when, after subtraction, a borrow output takes place. SUB.sub.3 is the full subtractor means for subtracting the output information appearing at the terminal G of the above mentioned full subtraction means SUB.sub.1 from the content of the above mentioned first register REG.sub.1 so as to produce a high level output at the terminal B.sub.3 when, after subtraction, a borrow output takes place. AND.sub.1 is the AND-gate into which the output at the carrier output appearing terminal C of the above mentioned full adder means through the inverter IN.sub.1 and the output appearing at the borrow output terminal B.sub.2 of the above mentioned full subtractor means SUB.sub.2 are supplied. AND.sub.2 is the AND gate into which the output appearing at the borrow output terminal B.sub.2 of the above mentioned full subtractor means SUB.sub.1 through the inverter IN.sub.2 and the output appearing at the borrow output terminal B.sub.3 of the above mentioned full subtractor means SUB.sub.3 are supplied. OR is the OR-gate into which the output of the above mentioned AND-gate AND.sub.1, that of the above mentioned AND-gate AND.sub.2, and the indication information updating pulse T.sub.ST produced by the dividing circuit for dividing the pulse produced by the above mentioned pulse generating circuit CPG are supplied. AND.sub.3 is the AND-gate into which the output T.sub.OR of the above mentioned OR-gate and the pulse .phi..sub.o obtained from the clock pulse go through the inverter IN.sub.3 are supplied and whose output is, in turn, supplied into the terminal CP.sub.2 of the second register REG.sub.2. OR.sub.2 is connected with the output terminal of the above mentioned AND-gate AND.sub.1 and that of the above mentioned AND-gate AND.sub.2. The output of OR.sub.2 is connected with the reset input terminal of the above mentioned dividing circuit T.sub. STC in such a manner that the dividing circuit T.sub.STC is reset by means of the output of OR.sub.2.

Below the operation of the embodiment described above will be explained in accordance with the timing charts of FIG. 2.

The continuously varying brightness of the object to be photographed is converted into an analog electric quantity corresponding to the brightness of the object to be photographed by means of the light measuring circuit exp. The analog electric quantity is then converted into digital information by means of an analog-digital converting means AD. Because the digital information converted by the above mentioned AD corresponds to the above mentioned brightness of the object to be photographed, its value varies continuously corresponding to the brightness of the object to be photographed. The digital information is supplied to the input terminal of the first register REG.sub.1 in such a manner that the information is stored in the first register REG.sub.1, being synchronized with the trailing edge of the timing pulse .phi..sub.o supplied to the terminal CP.sub.1. .phi..sub.o has a very short period and comes from the pulse generating circuit CPG. Because the storing operation of the digital information coming from the above mentioned AD into the register REG.sub.1 is carried out every time the above mentioned pulse .phi..sub.o is supplied, the continuously varying digital information is stored in the register REG.sub.1, being synchronized with the pulse .phi..sub.o. Since the pulse .phi..sub.o is supplied to the register REG.sub.1 with a very short period the digital information almost corresponding to the actual variation of the brightness of the object to be photographed enters the register REG.sub.1. The digital information stored in the register REG.sub.1 is supplied to the register REG.sub.2 and then to the indication means DIS through a decoder DEC in order to be digitally indicated. The storing operation of the information from the register REG.sub.1 into the register REG.sub.2 is carried out every time, the pulse T.sub.CP is supplied to the terminal CP.sub.2. Accordingly, the above mentioned pulse T.sub.CP is supplied to the terminal CP.sub.2 of the register REG.sub.2, the information corresponding to the brightness of the object to be photographed, being stored in the register REG.sub.1 with a very short period, is not supplied to the register REG.sub.2. Thus, the indication means DIS would still indicates the content stored in the register REG.sub.2 by means of the preceeding pulse T.sub.CP. The above mentioned pulse T.sub.CP is the pulse obtained by the pulse signal through the OR-gate of the data updating pulse T.sub.ST produced by the dividing circuit T.sub.STC with a very long period compared with the period of the above mentioned .phi..sub.o and by the AND logic through the AND gate AND.sub.3, of the above mentioned pulse T.sub.ST and of the inverted pulse .phi..sub.o of the above mentioned timing pulse .phi..sub.o through the inverter IN.sub.3. Accordingly, the pulse T.sub.CP substantially possesses the same period as the above mentioned pulse T.sub.ST and therefore the information of the register REG.sub.1 is stored in the register REG.sub.2 at a longer interval compared with the period of the pulse .phi..sub.o. Thus, the indication made by the indicating means DIS is updated in its content with the period of the pulse T.sub.SC of the dividing circuit. Therefore, even if the brightness of the object to be photographed always varies continuously, the content of the register REG.sub.1 is stored in the register REG.sub.2, being synchronized with the pulse T.sub.SC of the above mentioned dividing circuit T.sub.SC. The content of the register REG.sub.2 does not vary until the next storing pulse T.sub.CP is supplied to CP.sub.2, and during the period of the pulse T.sub.SC. The indication, therefore, does not vary during the period of the above mentioned pulse T.sub.SC so that the flickering of the indication due to the variation of the brightness of the object to be photographed can be avoided even if the output AD varies with a very short period due to the variation of the brightness of the object to be photographed. During a series of the above mentioned processes, the content of the second register REG.sub.2 is supplied to the full adder means ADD and the full subtractor means SUB.sub.1 at the same time. Now, assume that the data produced by the second register REG.sub.2 is .chi.. A constant value .alpha., as the variation tolerance value is put in the above mentioned addition means ADD and the above mentioned subtraction means SUB.sub.1 from the constant value setting circuit Dref. The arrangement is so designed that the above mentioned adder means ADD carries out the addition of the constant .alpha. to the data X produced by the second register REG.sub.2, so as to produce the result X +.alpha. at the terminal S. The above mentioned full subtractor means SUB.sub.1 carries out the subtraction of the constant .alpha. from the data X produced by the second register REG.sub.2, so as to produce the result X-.alpha. at the terminal G. If result X+.alpha. is so much more than the capacity of the above mentioned full adder means ADD to produce a carry, the full adder means ADD produces a high level output at the terminal C. If the result X-.alpha. becomes so negative so as to produce a borrow output, the full subtractor means SUB produces a high level output at the terminal B.sub.1. The output X+.alpha. at the terminal S of the full adder means ADD is entered into the full subtractor means SUB.sub.2, in which the content X' of the first register REG.sub.1, representing the then brightness of the object to be photographed is also supplied at the same time. The subtraction of the data X' from the data X+.alpha. occurs, so that when the result X+.alpha.- X' is negative, the borrow output terminal B.sub.2 of the full subtractor means SUB.sub.2 produces a high level output. This high level output means that X+.alpha.- X' is smaller than 0 or X'-X is larger than .alpha.. That is, the variation of the content X' of the first register REG.sub.1 representing the instantaneous brightness in comparison to the content X of the second register REG.sub.2 representing the brightness at the preceeding sampling is larger than the variation tolerance value. Thus, the output produced at the terminal B.sub.2 of the total subtraction means SUB.sub.2 is supplied to the AND-gate AND.sub.1. In the above mentioned AND-gate AND.sub.1 the output produced at the carrier output terminal C of the above mentioned addition means ADD is entered through the inverter IN.sub.1, whereby so long as the output produced at the above mentioned carrier output terminal C is at the low level, the above mentioned AND-gate AND.sub.1 is kept open so that in case a high level borrow output is produced at the terminal B.sub.2 of the above mentioned total subtraction means SUB.sub.2, the AND-gate AND.sub.1 produces a high level signal T.sub.A. This is supplied to the AND-gate AND.sub.3 through the OR-gate OR. In consequence the output is supplied to the terminal CP.sub.2 of the second register REG.sub.2 as the pulse T.sub.CP obtained as the AND-logic of the pulse and the inverted pulse .phi..sub.o of the timing pulse .phi..sub.o, when the data X' stored in the first register REG.sub.1 is stored in the second register REG.sub.2, at the same time varying the indication of the indication means DIS into X'. When the then brightness of the object to be photographed is higher than that at the time when it was stored in the above mentioned second register REG.sub.2 by means of the preceeding pulse T.sub.CP beyond the certain determined tolerance, the content of the above mentioned register REG.sub.2 is updated and immediately indicated independently of the updated pulse T.sub.ST produced by the above mentioned dividing circuit T.sub.STC at a certain determined period. Further, the output X-.alpha. produced at the terminal G of the above mentioned subtraction means SUB.sub.1 is supplied to the total subtraction means SUB.sub.3, whereby at the same time, the content X' of the first register REG.sub.1 is supplied to the above mentioned full subtractor means SUB.sub.3. Here, the subtraction of the data X-.alpha. from the data X' is carried out in such a manner that, when the result X'- X+.alpha. is negative, a high level output is produced at the borrow output terminal B.sub.3 of the full subtractor means SUB.sub.3. This high level output means that the result X'-X+ .alpha. is smaller than 0, namely, X- X' is larger than .alpha.. In other words, the variation of the content X' of the first register REG.sub.1 in contrast to the content X of the second register REG.sub.2, namely, the instantaneous indicated information, is larger than the variation tolerance value .alpha.. Under these circumstances output produced at the terminal B.sub.3 of the full subtractor means SUB.sub.3 is supplied to the AND-gate AND.sub.2. Because the above mentioned AND-gate AND.sub.2 is kept opened so long as the output produced at the borrow output terminal B.sub.1 of the above mentioned full subtractor means SUB.sub.1 is at a low level, when a high level borrow output is produced at the terminal B.sub.3 of the above mentioned full subtractor means SUB.sub.2, a high level signal T.sub.B is produced by the AND-gate AND.sub.2 and is entered in the AND-gate AND.sub.3 through the OR-gate OR. In consequence, the output is supplied to the terminal CP.sub.2 of the above mentioned second register REG.sub.2 as the pulse T.sub.CP obtained as the AND logic of the output and the inversed pulse .phi..sub.o of the timing pulse .phi..sub.o, when the data X' stored in the first register REG.sub.1 is stored in the second register REG.sub.2, at the same time varying the indication by the indication means DIS into X'.

In other words, when the variation of the data X' stored in the first register REG.sub.1, synchronized by the trailing edge of the timing pulse .phi..sub.o from the information X stored in the second register REG.sub.2 and indicated by the indication means DIS, is within the range of .+-..alpha., the content X' of the first register REG.sub.1 is stored in the second register REG.sub.2 synchronized by the trailing edge of the data updating pulse T.sub.ST so as to update the indication. The content X' of the first register REG.sub.1 is stored in the second register REG.sub.2 so as to renovate the indication at the time when it is determined that the variation of the data X' stored in the first register REG.sub.1 from the indicated information X is without the range of .+-..alpha..

Thus, when a borrow output T.sub.A or T.sub.B is produced by the full subtractor means SUB.sub.2 or SUB.sub.3, it is detected by the OR-circuit OR.sub.2, resetting the dividing circuit T.sub.STC in such a manner that the timing of producing the next pulse T.sub.ST is determined starting from the time point when T.sub.A or T.sub.B is produced. Accordingly, the situation can be avoided that immediately after the indication is updated by the borrow output T.sub.A or T.sub.B the data updating pulse T.sub.ST is produced and the indication must immediately be updated.

FIG. 3 shows the circuit diagram for showing the details of the block diagram shown in FIG. 1. In FIG. 3, the same components as those shown in FIG. 1 present the same figures. Below, the embodiment will be explained in accordance with FIG. 3. exp. and AD are the light measuring circuit and the A-D converting means shown in FIG. 1. The above mentioned REG.sub.1 consists of Flip-Flops FF.sub.1 -FF.sub.4 here, the input terminal of each Flip-Flop being connected with respective output terminal D.sub.o -D.sub.3, representing a respective bit of the A-D converting means A-D and at the same time, with the pulse generating circuit CPG for generating the clock pulse for storing the output of AD. This is done in such a manner that the content of each Flip-Flop is produced by AD, being synchronized with the pulse .phi..sub.o. Similarly to REG.sub.1, REG.sub.2 consists of Flip-Flops FF.sub.1 '-FF.sub.4 ', whereby the input of each Flip-Flop is connected with the respective output of the above mentioned Flip-Flops FF.sub.1 '-FF.sub.4 ' in such a manner that the content of each Flip-Flop FF.sub.1 '-FF.sub.4 ' is stored in the respective Flip-Flop FF.sub.1 '-FF.sub.4 ' by means of the signal T.sub.CP coming from the above mentioned AND.sub.3. Each output R.sub.10 -R.sub.13 of the above mentioned Flip-Flop FF.sub.1 '-FF.sub.4 ' is put in the above mentioned addition means ADD and the above mentioned subtractor means SUB.sub.1. A constant supplied to ADD from the above mentioned Dref is added to the respective output in ADD or a constant supplied to SUB.sub.1 from the above mentioned Dref is deducted from the respective output in SUB.sub.1. The output S.sub.o -S.sub.3 of the above mentioned ADD is supplied to the above mentioned SUB.sub.2 so as to be deducted from the output R.sub.oo -R.sub.o3 put in the above mentioned SUB.sub.2, of the above mentioned REG.sub.1. This is done in such a manner than B.sub.2 produces a borrow output when the result of the subtraction is negative. Further, the output d.sub.o -d.sub.3 of the above mentioned SUB.sub.1 is supplied to the above mentioned SUB.sub.3 so as to be deducted from the output R.sub.oo -R.sub.o3 of the above mentioned Flip-Flop FF.sub.1 -FF.sub.4 in SUB.sub.3. This is done in such a manner that B.sub.3 produces a borrow output when the result of the subtraction is negative. The operation of the embodiment shown in FIG. 3 is the same as that of the embodiment shown in FIG. 1, so that its explanation is omitted. The full adder means ADD shown in FIG. 3 consists of adder means AD.sub.1 -AD.sub.4, each consisting of the exclusive OR-gate EXOR, the AND-gate AND and the OR-gate OR for each bit as is shown in FIGS. 4a and 4b. The output R.sub.10 -R.sub.13 of the Flip-Flop FF.sub.1 '-FF.sub.4 ' of the above mentioned second register REG.sub.2 and the output of Dref is applied to the respective input terminal of the addition means AD.sub.1 -AD.sub.4. Further, the full subtractor means SUB.sub.1 consists of the subtractor means SU.sub.1 -SU.sub.4, each consisting of the exclusive OR-gate EXOR, the AND-gate AND, the OR-gate OR and the inverter IN for each bit as is shown in FIGS. 5a and 5b. Further, as to the composition of the total addition means SUB.sub.2 shown in FIG. 3, the subtraction means SU.sub.1 '-SU.sub.4 ' is provided for each bit as is shown in FIG. 6, whereby the output S.sub.o -S.sub.3 of the above mentioned addition means ADD and the output R.sub.oo -R.sub.o3 of the register REG.sub.1 are supplied to the respective input terminal of the subtraction means SU.sub.1 '-SU.sub.4 '. Each subtraction means consists of the logic shown in FIG. 5b. Further as to the composition of the full subtractor means SUB.sub.3, the subtractor means SU.sub.1 " -SU.sub.4 " is provided for each bit as is shown in FIG. 7, whereby the output d.sub.o -d.sub.3 of the subtraction means SU.sub.1 -SU.sub.4 of the above mentioned SUB.sub.1 and the output R.sub.oo -R.sub.o3 of the above mentioned register REG.sub.1 are supplied to the input terminal of the respective subtraction means. Each subtractor means consists of the logic shown in FIG. 5b.

As explained above in detail, by means of the digital information indicating system in accordance with the present invention, the digital information in which a continuously varying analog quantity is converted is sampled at a certain determined period and indicated. When, however the analog quantity varies excessively from the sampled information, the variation is detected. The information is then immediately indicated independently of the sampling period. Accordingly, the system is very useful for indicating information which varies quite often, such as the digital indication of the photographing information for a camera.