Satellite Controlled Clock

A unique service has recently become available throughout the whole of the Americas and even portions of Oceania and Europe with the launching of the GOES (Geostationary Operational Environmental Satellite) of the United States National Oceanic and Atmospheric Administration. Through cooperation with the United States National Bureau of Standards, a satellite disseminated time code is relayed from Wallops Island, Virginia to two stationary or synchronous satellites approximately 36,000 kilometers above the equator and geostationary. Time and data code signals along with observed satellite position information are transmitted by both satellites, the eastern and the western satellites. The time codes and information are available to any receiver capable of detecting and decoding the transmission.

The operational characteristics of the GOES satellites are described in Publication TFS-602 and titled NBS TIME VIA SATELLITES issued by the United States Bureau of Standards Boulder, Colorado 80302 on Jan. 1, 1978. Described in that publication and in the description below is the signalling format used by the satellites.

The operation of the satellite time system and a receiver capable of detecting, decoding and displaying time signals from the satellites is described in U.S. Pat. No. 4,014,166 issued on Mar. 29, 1977 to Joseph V. Cateora et al and assigned to the U.S. Government.

The receiver disclosed in U.S. Pat. No. 4,014,166 receives and decodes the time codes but has no provision for correcting for satellite errors or for time error corrections for the receivers actual position or to obtain true local, zone or UTC time. The net result is that the accuracy available via satellite time is significantly degraded in any known receiver with which we are familiar.

Given the foregoing State of the Art, we have determined that the value of satellite time can be greatly enhanced if the receiver can calculate the total transmission path delay incorporating the effects of actual transmitter, satellite and receiver position. Since the satellite position is transmitted as part of the code sequence and the transmitter and receiver positions are known it is possible employing our invention to provide continuous, accurate time display with these parameters and any changes which occur in satellite position or receiver position to be introducable into time corrections.

We have also found it possible to decode and display the one pulse per second signal provided by the GOES satellites and to generate a local similar signal which acts as a local clock for local use in controlling other equipment and to maintain a display during periods of non-operation of the GOES satellite or interference conditions. We have also developed circuitry which will continuously compare any local external clock 1 pulse per second time with satellite 1 pulse per second signal and to generate and display a deviation signal if it exists between the two.

We have also discovered that it is possible to generate and introduce offset signals to provide for the local time zone and for daylight savings time to allow these corrections to be made in the display without otherwise interfering with the operation of the receiver or local clock.

Basically our invention involves a coherent synchronous digital ultra high frequency receiver which receives signals from a broad band antenna having its own preamplifier stage and providing satellite signals at -120 dbm or greater to the receiver in the 468.8 MHz range. This frequency range includes signals at 468.8375 MHz from the Eastern Satellite and Western Satellite signals at 468.8250 MHz.

The receiver includes automatic tuning circuitry which scans the selected frequency band for the Satellite chosen. When the receiver detects the Satellite signal it shifts to a synchronization mode employing the synchronizing circuitry of the receiver. The receiver also includes delay path calculation circuitry which is enabled after the receiver is synchronized with the satellite signal.

Signal calculation processor circuitry includes a self-check circuit which requires that the delay path calculation be repeated if an error is detected. The selfcheck circuitry also compares received time signals from the satellite with the displayed time of the receiver to correct the display if it is incorrect.

Our receiver also includes provision for introducing an offset for time zones to provide local time as well as standard or daylight savings time. Our receiver further includes provision for locking out erroneous satellite time and position information.

Our receiver additionally includes a time interval measurement circuit for measuring the time deviation of a user supplied 1 pulse per second external clock with respect to the satellite time. This circuitry drives a deviation display which continuously represents any deviation of the local signal from the received standard clock pulses from the satellite.

This invention may be more clearly understood from the following detailed description and by reference to the drawing in which:

FIG. 1 is a pictoral representation of the typical operational situation found for this invention;

FIGS. 1a and 1b are simplified graphical presentations of the geometric relationships involved in the operation of this invention;

FIG. 2 is an interrogation channel format diagram of satellite signals of FIG. 1;

FIG. 3 is time code format diagram;

FIG. 4 is a front elevational view of the receiver of this invention;

FIG. 4a is a rear elevational view thereof;

FIG. 5 is a block diagram of this invention;

FIG. 6 is an electrical schematic diagram of the RF amplifier, voltage controlled oscillator and mixer of this invention;

FIG. 7 is an electrical schematic diagram of the IF amplifier and phase detector thereof;

FIG. 8 is an electrical schematic diagram of the voltage controlled oscillator thereof;

FIG. 9 is an electrical schematic diagram of the data detector and data clock synchronizer thereof;

FIG. 10 is an electrical schematic diagram of the phase detector slew control thereof;

FIG. 11 is an electrical schematic diagram of the processor thereof;

FIG. 12 is an electrical schematic diagram of the processor input and output circuitry thereof;

FIG. 13 is an electrical schematic diagram of the time delay calculator thereof;

FIG. 14 is an electrical schematic diagram of the time delay counter;

FIG. 15 is an electrical schematic diagram of the display thereof;

FIG. 16 is an electrical schematic diagram of the output buffer thereof;

FIG. 17 is an electrical schematic diagram of the IRIG-B amplitude modulator; and deviation analog circuitry;

FIG. 18 is an electrical schematic diagram of the receiver position delay switch;

FIGS. 19, 20 and 21 constitute a flow chart for the tuning, synchronization and delay path compensation operation of this invention; and

FIG. 22 is an arrangement diagram for FIGS. 19, 20 and 21.

Now referring to FIG. 1, an operational situation involving this invention is illustrated employing the Eastern Satellite 10 and the Western Satellite 11 each relative geostationary above the equator respectively at 135 and 75 degrees west longitude. These satellites are approximately 36,000 kilometers above the surface of the earth and at their relatively stationary orbits may be received by appropriate radio receivers over the North American continent and most of South America while the Eastern Satellite 10 may be received throughout the North and South Atlantic oceans, parts of Europe and Africa. The Western Satellite 11 has coverage of virtually the entire Pacific Ocean. Time information, date information and Satellite position information is transmitted to both of these Satellites from an installation at Wallops Island Virginia represented by antennas 12 and 13 each directed towards a respective Eastern or Western Satellite. As described in the National Bureau of Standards document the time code, data code and satellite position is transmitted employing phase shift modulated carrier and are right hand circularly polarized. The data rate is 100 bits per second and band width of the transmission 400 Hz. The time code is time division multiplexed (interlaced) with interrogation messages. Once every half-second, a time code word, 4 bits, is transmitted. A complete time code is transmitted every 30 seconds beginning on the half-minute giving the day of the year, hour, minute, and second. The format and location of each time code word as well as relative length is illustrated in FIG. 2. The time code frame consists of the synchronization word e.g. 40 bits of alternating ones and spaces followed by encoded day, hours, minutes and seconds. The universal time correction, plus satellite position, latitude, longitude and radius, complete the entire code frame which is transmitted for a period of thirty seconds. This is illustrated in FIG. 3. Referring again to FIG. 1, a receiver 14 and its associated antenna 15 is shown as located within the field of view of both satellites 10 and 11 and thus can receive time code signals from either of the satellites. The entire continental United States falls within this dual satellite area. The antenna 15 and the receiver 14 are shown as located at North 34.45 degrees latitude and West 119.83 degrees longitude a location approximating Santa Barbara, California.

The geometric relationship of the earth and either satellite is illustrated in FIG. 1a, which is derived from the National Bureau of Standards Technical Note 638, "A Synchronous Satellite Time Delay Computer", July, 1973, to which reference should be made for further explanation.

Suffice it to say the path delay calculations accomplished by this invention involve the solution of the geometric relationship there described. Referring now to FIG. 1a, the method used in calculating the path delay is to first solve the triangle formed by straight lines joining the satellite 10, the center of the earth and the antenna 15 site This solution from plane trigonometry is ##EQU1## where r is the range from the antenna 15 to the satellite, R is the distance from the satellite 10 to the center of the earth, h is the distance from the receiver to the center of the earth and .beta. is the central angle between the sub-satellite point and the receiver. The quantity R is a component of the satellite's position and is available via the satellite broadcast. The quantity h is related to the geodetic latitude, .psi., of a site by the following equation ##EQU2## where a=6378.2064 km, the earth's semi-major axis; and b=6356.5838 km, the earth's semi-minor axis.

For use in the equations below, the geocentric latitude, .phi.', is computed from the geodetic latitude, .phi., by the following equation. ##EQU3## The sub-satellite latitude is already referenced to the center of the earth and does not need to undergo this transformation. In the following discussion, .lambda. is longitude and subscripts s and r denote sub-satellite point and receiver site respectively.

All that is left then is the computation of cos .beta.. The direct solution may be obtained from the triangle consisting of the sub-satellite point, the site, and the intersection of the z axis with the spherical earth (i.e., the North Pole) using spherical trigonometry as follows:

Using equations (1) through (4), the "down-link" free space propagation delay from the satellite to the receiver is easily determined by dividing the range by the velocity of free space propagation (0.2997925 km/.mu.s). The procedure must be repeated substituting the transmitter for the receiver location to determine the "up-link" delay. The total free space propagation delay, then is the sum of the delays computing using the transmitter and receiver locations. The change in signal velocity through the troposphere and ionosphere and the accompanying ray bending can be shown to introduce only a few microseconds difference in the roundtrip free space propagation time when operating above 100 MHz [2].

The receiver of this invention and its operational controls may be seen in FIG. 4 as including the power switch 16 and a satellite selector switch 20 having two positions, East and West. A plurality of thumb wheel switches 21 are used to introduce the latitude information and a similar set of thumb wheel switches 22 are used to introduce longitude of the receiver into the receiver logic circuitry. The front panel receiver includes a jack 23 for introducing a one pulse per second input.

The receiver includes a display panel 24 including three LED displays indicating the status of the receiver operation.

LED display 25 is illuminated during the period in which the receiver is automatically tuning through the band which includes the satellite selected by selector switch 20. LED 26 is illuminated after tuning has been terminated and the satellite detected. The synchronizing of the local clock with the time code signals is signaled by the illumination of LED 26. After satellite detection and synchronization is accomplished the LED 25 and 26 are no longer lighted but LED 30 is illuminated to indicate that the delay path calculation is in process. Once each of these steps have been completed each of these displays 25, 26, and 30 are no longer illuminated and the correct day, hour, minute and second are displayed. One further display is present in the form of micro-seconds deviation between a user supplied external 1 PPS clock input and the 1 PPS signal as received from the satellite. Normally the deviation signal input is not illuminated if a local clock 1 PPS input is not present.

FIG. 4a shows the rear of the receiver including cooling fan 27, air inlet 28 and jacks for the input of signals from antenna 15 of FIG. 1 and output of 1 pulse per second, one MHz timing or clock signal and time data in IRIG-B format from the data out jack. A line cord unshown supplies 115 v 60 Hz power to the receiver.

For an understanding of the operation of the receiver with the inputs and displays illustrated in FIG. 4, one should now direct their attention to the block diagram of the receiver FIG. 5.

Now referring to FIG. 5 the antenna 15 is shown with its associated preamplifier 35 normally physically associated with the antenna and typically composed of two low noise tuned RF stages with associated bias control circuits in order to provide the required signal level to the receiver to follow. The receiver includes a receiver Section 36 composed of an RF amplifier 40, a mixer 41 and voltage control oscillator 42, an IF amplifier 43, and a phase and data detector 44 and 45 respectively, the latter of which includes clock synchronizing circuitry. The data phase detector also includes clock slew control circuitry. VCO control circuit 59 completes this section.

The next section of the receiver is the logic section 50 comprising a data decoder 51 and control processor 52, a time delay calculator 53, a time delay generator 54 and an output buffer stage 55 as well as a time delay generator and time deviation control circuit 54.

A display section 60 includes the receiver status display 25, 26, and 30 and the date and time display 61 and the clock deviation 62. A switch section 70 includes each of the control switches including the satellite select switch 20 a reference select switch 71, a local time switch 72, a receiver delay switch 73 and the longitude and latitude control switches 21 and 22 as shown in FIG. 4.

For a better understanding of this invention, each of the circuits are described as to their makeup in the preferred embodiment including actual component values and designations which appear on the drawing and which are actually used in the commercial embodiment of this invention. In the following schematic diagrams integrated circuits also include reference to pin numbers and Reference J refers to jumper and pin numbers as assistance to the reader.

Referring now to FIG. 6, the RF amplifier voltage controlled oscillator and mixer section may be seen in detail therein. The RF amplifier 40 includes two tuned amplifier stages Q1 and Q2 with their associated tuning networks with the output of the tuned amplifier 40 applied to a mixer stage 41 employing Q3 as its active element. The other input to the mixer stage is driven from the 438.8250 MHz or 438.8375 MHz output of the VCO section which is made up of voltage control oscillator 42 including a crystal XTL1 and two stages Q4 and Q5 which operate at one/eighth the VCO output frequency. The frequency multiplier amplifier composed of stages Q6 and Q7 is used to develop the final VCO output which is supplied to mixer 41.

The schematic of the IF amplifier and phase detector 43 appear in FIG. 7 in which the output of the mixer 41 is coupled to the crystal filter 1 of FIG. 7 via inductor L14 which is tuned by the mixer output tuning capacitor for 30 MHz resonance. After filtering, the signal is amplified by linear amplifier IC1. A tuned interstage coupling network composed to capacitors C43, C44, and inductor L16 is used to couple the amplifier output to limiter stage IC2. The output of the limiter of IC2 is then applied to the input logic interface stage IC3 for conversion to emitter-coupled logic levels. A high speed phase detector IC4 is employed to detect phase differences between the 30 MHz signal derived from the satellite transmission and the crystal controlled 30 MHz reference oscillator OSCl. The phase detector pulse outputs are integrated by RC networks R25, C53, and R26, C54, before they are applied to the inputs of operational amplifier IC5. This amplifier produces the resultant phase detector output containing data encoded modulation signal on lead labelled .phi.. A divide by two stage IC6 reduces the reference oscillator frequency output to 15 MHz for operation of the processor circuitry described below.

The VCO control circuitry of FIG. 8 receives the phase detector output and produces a control voltage which tunes the VCO crystal oscillator for reception of the desired satellite signal. The control output labeled VCO on FIG. 8 is developed by operational amplifier IC11A in response to the combined inputs from the satellite select 20, the digitally stepped automatic tuning voltage from operational amplifier IC11B and the integrated phase detector output developed by operational amplifier IC10B. The integrator circuit correctively adjusts the VCO output frequency so that there is minimum average phase difference output from the phase detector. A counter IC15 and digital to analog converter R48 are used to develop the automatic tune voltage whenever called upon by control circuitry actions or whenever the integrator output approaches a limit in its operating range.

A phase reference voltage, labeled .phi.REF is developed for use in the data recovery section of the receiver. The voltage is developed by a switching filter composed of IC8 and IC9 in combination with the RC network R34, C56, and C57 and R37, R38 and C58. A buffer amplifier IC10A produces the desired reference output.

The satellite modulation signal as produced by the phase detector contains self-clocked Manchester encoded data. It is necessary to develop a nonreturn-to-zero (NRZ) bit pattern and separate precisely synchronized data clock for operation of the data decoding and timing circuitry located on the main logic panel.

FIG. 9 shows the circuitry for performing the data and data clock recovery functions. The .phi. and .phi.REF signals from the phase detector 43 and VCO control sections 46 of FIG. 8 are applied to the input of a comparator IC18A to yield logic level voltage excursions representing the input modulation data pattern. Since the phase modulation data may contain considerable noise, it is necessary to filter the digital output of the comparator IC18A in order to provide reliable digital data. The filter function is accomplished by a recirculating shift register IC19 in combination with RC network R70, C68 and comparator IC18D. Decoding of the Manchester data is performed by the output shift register IC33A and B in concert with the synchronized timing pulses developed in the data clock synchronization circuitry. Decoding errors are detected by IC34 and exclusive-or gate circuitry IC35. The error signal output is utilized by the processor-decoder to eliminate processing errors due to improperly decoded Manchester data.

Data clock synchronization is accomplished by comparison circuitry located on the main logic circuitry operating in response to clock pulses derived from the receiver 100 Hz data transitions and from a 100 Hz clock derived from the reference oscillator of FIG. 7. The 100 Hz data transition pulses, labeled RCVR 100 Hz, are developed from comparator IC18A, pulse generator IC20, and decode counter Ic21. The synchronized 100 Hz clock, labeled 100 Hz, is the output obtained from countdown circuits IC128, IC29, IC25B and IC30. This 100 Hz signal provides the basic timing of the clock time and data circuits.

Synchronization is achieved in two steps with coarse synchronization to within 100 or 200 microseconds occuring during initialization and secondly close synchronization to within a few microseconds occuring through the operation of the 100 Hz phase detector and slew control of FIG. 10. During the initialization procedure, counter circuits 31, 24B, and 32 activates gate 37A whenever the 100 Hz clock persistently deviates from synchronization with the receiver 100 Hz by more than 500 microseconds. This gate permits direct synchronization to occur by allowing receiver data transition pulses to pass to the reset circuitry of the countdown chain.

Fine synchronization of the 100 Hz clock is achieved by the action of the phase detector and slew control circuit shown in FIG. 10. A phase detector, 73, detects phase differences between the 100 Hz clock and the received 100 Hz from the satellite transmission. The phase difference signals actuate counters 80 and 82 depending upon whether a leading or lagging phase error exists. The phase errors are counted over a 1 second time period and the resulting counter accumulations are compared by comparator 81. If the counts are equal no action occurs. If one counter exceeds the other, then a corresponding output is passed to the shift registers 83. A majority logic circuit 84 monitors the shift register outputs and develops a lead or lag output provided 3 out of 4 of the previous shift register inputs have the same value. The lead or lag outputs actuate D flip-flops 87 and 89 to respectively subtract or add one count to the 1 MHz pulse stream produced at gate 76. The remaining control circuitry provides sampling pulses and internal/external clock reference control.

The data and 100 Hz synchronized data clock produced by the previous circuitry is decoded by the processor circuit shown in FIG. 12 to produce the desired time and calculator control outputs. The received data message is in the form shown in FIG. 2. FIG. 11 shows the processor and memory circuitry and FIG. 12 shows the I/O circuits. Data inputs from the receiver and switch circuitry are entered via IC25. The calculator is driven by output 27 and the time outputs are driven by outputs 28 and 29. The IRIG controls are produced by decoder 16, gates 11 and 12 and counters 13, 14, 20, and 21, of FIG. 12.

The 8080 clock signals are generated by clock generator 2 of FIG. 11 and synchronized to 15 MHz derived from the receiver 30 MHz reference oscillator of FIG. 7. A one MHz reference clock is developed by divide by 15 counter 5 for use by the 100 Hz slew control circuitry.

FIG. 13 shows the time delay calculator. Keying signals for operation of the calculator are developed by gates 33 and 35 in response to commands from the processor section. These signals are applied to the calculator composed of integrated circuits IC34, IC39, and IC40. The calculator output is decoded to BCD digits by decoder circuit 42 and then fed to shift register 48, 49, and 50 for return to the processor, of FIG. 11.

The calculations performed by the time delay calculator of FIG. 13 consistently a part of the program set forth as Appendix A hereof in carrying out the significance of FIGS. 19-21 of the drawing.

The 1 PPS pulse developed from the satellite signal must be delayed by the amount determined in the path delay calculation. FIG. 14 shows the delay circuitry and includes shift register (IC58, IC59, and IC60) that receives the calculation result from the processor. This number is applied to down-counter IC55, IC56, IC56 each time a satellite derived 1 Hz pulse is received. The down-counter produces an output pulse after counting by the applied number to produce the desired delay corrected 1 PPS signal.

Time difference between an external 1 PPS input and the corrected 1 PPS output is developed by the remaining circuitry. Latches IC68 are operated by the delay corrected 1 PPS and external 1 PPS. Their outputs are applied to exclusive-or gate 66 and flip-flop 64 to produce a 1 MHz pulse train whose duration equals the time difference between the two 1 PPS signals. Counters IC52, IC53, and IC54 and flip-flop 64 produce the time difference sign information. The pulse train and sign signals along with strobe and reset signals are generated for use by the time deviation display.

FIG. 15 shows the display circuitry. The time digits D4 through D11 contain latches and 7 segment decoders and drivers along with the 7 segment display.

Multiplexed time data from the processor is applied to the time displays D4-D11 and entered into the appropriate display digit according to the time strobe pulses.

A 3-digit display to the right contains decimal counters as well as 7 segment encoders, drivers and display elements for generation and display of the deviation data. The deviation pulse train is counted by the decimal counters to produce the desired output. Gating circuits 3 stop the counting at 999 to indicate over-range if the pulse train is 1 millisecond or longer. Display 31 indicates the sign of the time deviation of the local 1 PPS internal or external reference as compared with corrected satellite 1 PPS signals.

FIGS. 16, and 17 show the output buffer, IRIG-B modulator, and deviation analog circuit respectively. Pulse stretchers 90 of FIG. 16 are used to provide 1 millisecond pulses from the 1 PPS and data valid pulses generated by previous circuitry. The multiplexed time data lines from the processor are buffered to drive the output lines.

Amplitude modulated IRIG-B signals are produced by modulator 100 of FIG. 17 in conjunction with operational amplifiers 101 and 102. A digitally synthesized sine wave with a 3 to 1 amplitude modulation pattern is developed.

Digital to analog converter 98 produces an output proportional to the decimal number developed by the deviation display. Operational amplifier 99 produces a positive output equal to the converter output when the sign data is positive and produces a negative output when the sign data is negative.

The receiver is ready to operate once power is supplied and the antenna 15 is connected. It is necessary to set the front panel longitude and latitude switches 21 and 22 to the values representing the receiver location. These may be obtained from an accurate map, and should be determined to 0.01.degree. for maximum accuracy in time recovery. Receiver operation is fully automatic once power is applied and the satellite switch 20 is set to receive the desired satellites 10 or 11, Eastern or Western. Operation of the front panel satellite switch 20 initiates the tuning and synchronization functions and in addition resets the processor controller to accept new data. The status lights 25, 26, and 30 will indicate the particular mode of operation. Initially the Tune light is illuminated and remains "on" during the tuning operation, and the seconds display begins to count seconds. The tuning operation is slow in terms of electronic speed and may require tens of seconds to complete. The tuning operation is illustrated in the flow diagram of FIG. 19.

Referring now to FIG. 19, the first block of flow diagrams involves the initiation of operation by power on or satellite selection, next setting all logic to zero state and then commencing tuning by control voltage of FIG. 6 applied to voltage variable capacitor CR1 of FIG. 6. Automatic tuning involves stepped voltages applied to CR1 of FIG. 6, tunes the VCO to the satellite frequency where the receiver locks to satellite carrier. Meanwhile logic data hold function is performed until tuning is accomplished.

The data hold step is accomplished specifically by an error signal at terminal 20 of FIG. 9. This prevents interpretation of any data appearing in the data channel prior to tuning and synchronization.

The Sync light will illuminate when the tuning function is complete. Clock synchronization occurs during this phase of operation. Again tens of seconds may be required to accomplish synchronization and depends upon successful readout of the satellite synchronization signal. This signal occurs during a 5 second period once each 30 seconds, at zero seconds and at 30 seconds UTC. The receiver ignores data during reception of interfering signals. In areas where interference is frequent it is possible for a number of synchronization periods to pass before successful synchronization occurs. If strong interference is experienced, the Tune light may reappear indicating loss of signal, and the receiver will retune. Synchronization is accomplished in accordance with the flow diagram of FIG. 20 Synchronization is achieved when the Sync and Tune lights 25 and 26 are extinguished. The time display 24 should then indicate the correct time.

Referring again to FIG. 19, after the satellite is received as represented by a yes output of the satellite received decision box, the tune light is extinguished, the sync light is illuminated and logic data hold is reset. The receiver then proceeds to read data bits until the Maximum Length Sequence (MLS) bit sequence. When detected, data is read until 31 more bits have been received and then the receiver begins to read the 4 bit time characters. The receiver looks for A's or 5's until found, and increments or restarts until detecting either 10 A's or 10 5's denoting either a 0 or 30 second time period. When either sequence is detected, the receiver is in synchronism and the sync light is turned off and the time in the internal registers is set.

As FIG. 19 shows at the lower left, the receiver continues to read data. The next 10 characters are time data which are written in the memory setting in the days, hours, minutes and seconds of a comparison step where stored time is performed. After the first cycle, the receiver proceeds to increment through 10 characters without an error flag set (FIG. 20 at bottom).

Next, the receiver continues to read data bits which are the satellite position bits. Satellite position bits are compared with stored satellite position and if a change is registered, the satellite position change counter is initialized. If no change, the receiver proceeds to read the receiver position switches which were set on the face of the instrument. If the receiver change counter is zero, denoting no movement of the receiver, the receiver switch position is read.

The calculate light is illuminated when the position change counter is decremented to zero.

The receiver next reads but does not record the next 37 characters of the satellite signal. These characters are unrelated and so are not used. Reading of the next block of 50 bits including the 37 bits causes resetting of the time write function back at FIG. 19.

Referring again to FIG. 20, bottom if in reading time characters, four successive errors are noted, denoting probable loss of synchronization, the synchronization step is again initiated from the 4 error decision box at the Sync Light On box of FIG. 19.

The procesor of FIG. 11 senses calculation errors. In the rare event that such an error occurs the processor will reinitiate the delay calculation after approximately one minute and again check the results for errors. If necessary the calculation will be repeated until a satisfactory result is obtained. Similarily, if incorrect time is displayed after initialization, the error will be detected during data comparison with the satellite time messages. The initialization procedure is automatically restarted to correct the error if is persists for more than 4 satellite time messages.

The clock 1 PPS output normally will be on time or within tens of microseconds of satellite time immediately after initialization is complete. Under some conditions, however, there can be as much as 300 or 400 microseconds time differences at this point in the operation, and additional time should be allowed for corrective actions to take place. The correction circuitry is designed to slew the local clock into agreement with satellite time at the rate of 1 microsecond per second (10 microseconds per second for large discrepancies and in the absence of interference). Thus some 300 or 400 seconds may be required to reduce the error to zero.

From time to time the Sync light may blink indicating an interference condition. The circuitry is arranged to transfer clock operation to the standby mode during the interference period. Clock slew controls and satellite data decoding functions are disabled in the standby mode.

UTC time as received from the satellite can be offset in the receiver to yield local time by setting the offset value into the Local Time Switch, Sl, and Daylight Savings Time Switch, D/S of FIG. 12.

Switch settings for switches Sl and D/S of FIG. 12 are determined by considering the local time zone in relation to the UTC reference zone through the Greenwich meridian. For example, Los Angeles is located in standard time zone U (Pacific Standard Time) which is -8 hours from the UTC zone. The operator sets the switches so that the values associated with the "on" switches when added equal the number of hours time difference. In this case the 5th switch with a value of 8 is turned "on" and the others turned "off". Since the hours are to be subtracted, the sign switch must be in the "off" position. If Daylight Saving Time is in effect the first switch should be "off", and if it is not in effect the switch should be "on". It is necessary to set the Daylight Saving switch to the "off" position if remote operation of this feature is desired.

The path delay calculation is initiated after the synchronization function is complete. Calculation begins either at 16.5 seconds or at 46.5 seconds depending upon whether synchronization occured on the minute or half minute. The Calc light 30 will illuminate during the approximately 40 seconds time required to perform the path delay computation. Initialization is complete when the calculation period ends.

Calculation of delay path is in accordance with the flow diagram of FIG. 21. Referring now to FIG. 21, whenever the data read function is performed, the delay path calculation is performed. Data is read and whenever the 100 Hz clock appears the receiver advances the stored time in the registers by 0.01 seconds. Next, the receiver checks to see if the second's digit is one, and when it occurs a 1 second pulse is outputted.

The next decision is whether local time switches are set. If so, the offset for local time (zone and daylight savings time) is introduced into the time display values which are then displayed. The IRIG B output is additionally serviced.

Delay path calculation is next commenced, completed and compared with the previous stored value of path delay. If within 100 micro seconds of the previous value, the new value is stored and outputted. If greater then 100 micro seconds, the calculation decision is followed by initiation of the position change counter to start the calculation again.

The actual calculation of path delay involves the solution of the geometric relationships illustrated in FIGS. 1a and 1b employing the calculator of FIG. 11. It is performed as a part of the calculations made by the type 8080 calculator chip of FIG. 1 in carrying out the program of Appendix A.

One may see that we have invented a satellite responsive time receiver which is capable of scanning for GEOS Satellite Signals, synchronizing with such signals, tracking the signal, automatically computing the signal path delay given the receiver position coordinates, compensating for the delay and displaying the corrected time. The receiver is further capable of introducing a correction for local and daylight time and for maintaining local internal clock time display during periods of loss of satellite signal. The receiver further provides an external 1 MHz clock signal and further compares satellite 1 pulse per second signals with similar local signals and displays any deviation. Thus a complete virtually automatic satellite clock is disclosed.

The above described embodiments of this invention are merely descriptive of its principles and are not to be considered limiting. The scope of this invention instead shall be determined from the scope of the following claims, including their equivalents. ##SPC1## ##SPC2## ##SPC3## .