Capture System for an Electronic Musical Instrument

Capture systems, or combination actions, were introduced ages ago in pipe organs to enable the organist to store a number of different combinations of stop settings for ready recall during a performance. The first of such systems were entirely mechanical, but these later gave way to electromagnetic operation with mechanical latches providing the memory. Present day electronic instruments pose a similar problem to the player by providing a larger array of controls than the player can handle easily during a performance. The problem is compounded by the fact that these controls are mainly potentiometer type, rather than the simple on-or-off stop switches provided in pipe organs.

One of the commercial synthesizers presently on the market provides a quadruple set of controls with a gang selector switch to allow instant selection of any one of the four set-ups. Besides being very expensive, this approach also takes a great deal of panel space, making the instrument very bulky.

The embodiment chosen to illustrate the invention is a polyphonic synthesizer employing a digital type keyboard where the playing keys are scanned repetitively by a microcomputer to detect changes in key states and idle note generators are assigned to playing keys in response to their depression. There are 25 preset controls, most of which are potentiometer type controls. The voltage control circuits that effect the desired tonal responses are each provided with a simple clamp-and-hold circuit to enable them to be controlled in a dynamic fashion by the microcomputer.

Between each scan of the keyboard, the microcomputer processes a different one of the presets. Normally a preset control is selected by an input selector switch, commonly called an analog multiplexer; converted to a 4 bit digital word, representing 16 equally spaced positions of the potentiometer slider, in the microcomputer; converted to an 8 bit digital word in accordance with a desired non-linear scale using a look-up table, when required; and output through an output selector switch to the corresponding clamp-and-hold circuit.

One or more CMOS type memories are provided and are made accessible to the microcomputer. They are effectively non-volatile by the provision of battery back-up power. When the player wishes to store a set-up for future recall, he selects a block of memory in which he wants the set-up stored, then operates a mode switch to the store position momentarily. The 4 bit digital words representing the slider positions of each preset control are then stored in sequence in the memory as they continue to be processed in the normal way.

When the player wishes to recall a previously stored set-up, he selects the desired memory block and operates the mode switch to the read capture memory position. The 4 bit digital words stored previously are read out sequentially and processed in exactly the same way as the corresponding words derived from the presets are processed normally. This action continues as long as the mode switch is left in the read capture memory position to maintain the clamp-and-hold circuits at the desired setting in a dynamic manner.

One of the principal objects of the invention is to provide a simple and economical capture system for an electronic musical instrument that can be easily implemented in a microcomputer that also services a digital type keyboard.

Another object of the invention is to minimize the amount of memory required, both external to and within the microcomputer.

Still another object of the invention is to provide a capture system which allows data to be stored in a linear form and converted to a non-linear form before being transferred to the utilization circuits, so as to minimize the required memory word length.

Other objects of the invention will be apparent from the following description and the accompanying drawings. While illustrative embodiments of the invention are shown in the drawings and will be described in detail herein, the invention is susceptible of embodiment in many different forms and it should be understood that the present disclosure is to be considered as an example of the principles of the invention and is not intended to limit the invention to the embodiments illustrated.

FIGS. 1a and 1b, when placed side by side, form a unitary functional block diagram of one preferred embodiment of a digital polyphonic music synthesizer using the invention;

FIGS. 2a and 2b, when placed side by side, form a unitary flow chart of the program used in one microcomputer, shown in FIG. 1a, that services the keyboard and voice controls;

FIGS. 2c and 2d, are flow charts of subroutines used in the above keyboard microcomputer;

FIG. 3 is a flow chart of the program used in a second microcomputer, shown in FIG. 1b, that generates five envelopes simultaneously; and

FIGS. 4a, 4b, 4c and 4d, are flow charts of subroutines used in the above envelope computer.

FIG. 5, is a block diagram showing a modification of the system shown in FIGS. 1a and 1b to provide for simultaneous outputs of envelopes in both nominal amplitude and pitch scaled amplitude forms.

FIG. 6, is a flow chart showing a modification of the envelope computer program depicted in FIG. 3.

I. Organization of the Music Synthesizer

As shown in FIGS. 1a and 1b, two microcomputers (Intel 8048 or 8748) are provided. The keyboard computer 100 interfaces the keyboard 150; capture memory control switches 155 and 156; voice controls 153, 154, 157; intercom registers 102, 202 and 203, capture memories 103-104; five note generators, such as 300, through decoder 105; clamp-and-hold circuits 111; and discrete registers 109 and 110.

The envelope computer 200 interfaces intercom registers 102, 202 and 203; and five voltage controlled filters (VCFs), such as 350, 370, 380, through a D/A ladder network 206 and analog multiplexer 205.

Since the 8048 and 8748 microcomputers are standard devices that are well known in the art and are fully described in the MCS-48 User's Manual, published by Intel Corp., their architecture and circuit operation are not described herein. The two computers 100 and 200 may each be provided with its own 6 mhz crystal, as shown, or they may be operated in synchronizm from a common source.

The principal function of the keyboard computer is to scan the keyboard contacts about once every millisecond, detect any changes in contact states, measure the travel time of a key being depressed, assign an idle envelope generator to a key when it has been fully operated, and transmit pitch and key velocity (touch response) information to the envelope computer. Pitch information is also transmitted to the appropriate note generator, such as 300.

An auxiliary function, performed at a much slower rate, is to scan the voice, or preset, controls; convert each one to digital form; convert the digital value to a new value, when required, using a look-up table; and then output the original, or new, value to a ladder network 115, thence to a corresponding clamp-and-hold circuit 111 via the analog multiplexers 107-108.

If the player wishes to store the voice, or preset, control setup in use; the STO mode is entered briefly, by operation of switch 152, causing the digitized values of the voice control settings to be stored in a capture memory 103-104 at a location selected by operation of switches 155 and 156. Conversely, if the player wishes to recall a previously stored voice control set-up; the RCM mode is entered, by operation of switch 152, causing the digitized values of the desired settings to be read from the capture memory; converted by the look-up table, if necessary, and output to the clamp-and-hold circuits.

Some of the voice controls 157 are used to vary the attack/decay parameters of the envelope generators. In an analog system these controls would be connected directly to corresponding inputs of a set of analog type envelope generators. In the present system these inputs are digitized and stored in registers in the keyboard computer 100. Wherever a change occurs in these input values, the new values are stored internally and are also transmitted to the envelope computer 200.

Additional voice controls are provided in the form of switches, such as 153 and 154, which may be individual or combinatorial. In either case they are input as 4-bit nibbles, to conform with the 4-bit words used in the captive memory, and are output to corresponding 4-bit registers, such as 109 and 110.

The envelope computer 200 is dedicated to the generation of five envelopes simultaneously. Updated digital amplitude values are output repetitively in sequence to the 16-bit ladder 206, thence via an analog multiplexer 205 to corresponding voltage controlled filters such as 350, 370, 380.

II. Operation of the Keyboard Computer

The 8048 or 8748 computer provides 1024 words by 8 bits of read-only (ROM) program memory and 64 words by 8 bits of resident data memory (RAM). All data memory locations are indirectly addressable through either of two RAM pointer registers which reside at addresses 0 and 1 of the register array. In addition, the first 8 locations (0-7) of the array are designated as working registers and are directly addressable by several instructions. By executing a register bank switch instruction RAM locations 24-31 are designated as the working registers (R0'-R7') and are then directly addressable. RAM locations 8-23 contain the program counter stack; which is addressed by the stack pointer, during subroutine calls, as well as by pointer registers R0 and R1.

A memory map showing the allocation of the 64 registers (0-3F in hexadecimal notation) is shown in Table I. An "x" in any bit column signifies that either a 0 or a 1 may be stored in that bit position, while a "0" signifies an unused bit that is set to 0 during initialization.

When power is applied to the computer 100 an internal reset pulse is generated to clear critical working registers, such as the program counter. After the capacitor connected to the RESET input has charged to the threshold of an internal Schmitt trigger, the reset pulse is terminated and operation under program control commences at location 0 in the program memory. The program memory listing is shown in Table IX, which appears at the end of the specification, but for simplicity the operation will be described with reference to the flow chart shown in FIG. 2. A modified program listing is shown in Table XI. Operation with the modified program is described separately in Section IV.

In block B1: port 21 (port 2, bit 1) is set to zero to reset the envelope computer and hold it disabled until the keyboard computer has initialized the clamp-and-hold circuits 111 (FIG. 1). Flag F0, which is set to 1 in block B1, will be set to 0 when the initialization of these circuits is completed, as described hereinafter. F3 designates a flag, but is actually bit 0 of R16. It is set to 1 in block B1 and is reset to 0 in B13 after initialization operations are completed.

In block B2: the states of mode select switch 152 and the block selection switches 155 are stored in register 3F. If the block selection has changed since the last program cycle the program branches through block B15 to compute a new block starting address, which is the actual address in the capture memory at which the selected group of voice control set-up values starts. The desired capture memory chip, such as 103 or 104, is selected independently by means of switch 156. Since F0=1, the program omits B16 for the present and proceeds to B6 or B17, depending on the mode selected. Assume that RSC (read slide controls) has been selected for now, in which case RCM (read capture memory) is false. Since the current parameter number (CPN) stored in R38 is set=0, the program branches from B5 via B17 to B18.

In block B18: register 119 is set to zero by the program. The three LSBs (least significant bits) of 119 are connected in parallel to all of the input/output analog multiplexers, such as 112 and 107. The effective higher order bits of 119 are decoded by 118 to select a corresponding one of these multiplexers. Assuming that slide control 158 is selected, its setting is applied to the input of comparator 114. The program now implements a successive approximation D/A conversion routine, using register 116 and ladder 115 to generate the trial values, to convert the slide control setting to a 4 bit digital value which is generated in the MSN (most significant nibble) of R5. Since STO=0, the program skips B20 and goes via B7 to B8.

In block B8: CPN (R38) is tested and, since it is initially 0, the program enters block B9 where the data in R5 is output to register 116. The first two voice control parameters are the vibrato rate and vibrato depth. These parameters vary linearly with slide control position, hence are output without modification.

In block B10: one of the high order bits of register 119 is set to 1 to enable the output analog multiplexer, such as 107, which connects to the clamp-and-hold circuit 111 for the parameter in process. Since F3 is set to 1, the program proceeds to block B12.

In block B12: since CPN is initially 0, the program branches to B26 where CPN is incremented by 1. The program then returns to B5 and repeats the above described minor loop with the following variations.

As mentioned previously, the first two voice control parameters are linear functions of the slide control position, hence are output to the clamp-and-hold circuits without modification other than the quantization resulting from the A/D conversion. In other words, the input/output transfer function is linear in this case. The next 16 parameters are the desired amplitudes of four pulse waveforms (16'P, 8'P, 4'P, and 2'P); nine harmonic components (SH, 1H, S3, 2H, 3H, 4H, 5H, 6H, and 8H); two filter frequency controls (FC1 and FC2); and a filter Q, or resonance, control (FQ). These output amplitudes should vary approximately exponentially with the slide control position. Although slide controls having so called logarithmic, or audio, tapers could be emloyed; their use would require digitizing to eight bits, rather than four, hence would double the size of the capture memory. Furthermore, the taper and uniformity obtainable in such controls leave much to be desired. These difficulties are overcome in the present embodiment of the invention by using slide controls of the linear variety and converting the linear input to an exponential output, or other desired output shape, by the use of a look-up table included in the program memory section of the keyboard computer. In this case the input/output transfer function is changed to an exponential form by the look-up table. This programmed shaping system also allows use of commercially available 4-bit binary coded switches in lieu of the analog controls if desired.

Whenever CPN is between 2 and 11H (17 in decimal notation), the program branches form B8 via B21 to B22.

In block 22, the 4 bit data in R5 is used to address a linear to exponential conversion table stored in every 4th location of the program memory commencing with 303 and ending with 33F. Every 4th location is used to fill voids in the key assignment-to-pitch conversion table which starts with location 300 and ends with 33E. The converted data (8 bits) is output to register 116 and the program then returns to the original minor loop at B10. On the nineteenth pass through the minor loop CPN=12H, hence the program branches from B21 via B28 to B29.

In block B29: the new data in R5 is compared with the corresponding prior data (which is practically random data following initialization) stored in R3A-R3F. If the data is unchanged the program returns to the original minor loop at B11, otherwise it proceeds to B30. In block B30: the old data in R3A-R3F is replaced with the new data in R5 and flag F0 is set=0 before the program goes to B11.

The parameters B, A, D1, D2 and R stored in R3A-R3E require some explanation since they differ from the customary ADSR parameters provided by conventional synthesizers. The A, D1 and R parameters of the present envelope generator correspond to the conventional A, D and R parameters. In lieu of a sustain mode, the present synthesizer provides a breakpoint (B) control that establishes the level at which the initial decay (D1) is terminated and is replaced by a second decay (D2.) If the second decay is set to infinity, then the breakpoint control becomes the equivalent of the conventional sustain (S) control. The provision of two decay rates permits a much more realistic piano sound to be achieved.

After the B, A, D1, D2 and R parameters have been processed, CPN=16H. On the following pass the program branches from B17 to B27.

In block B27: the computer 100 outputs a code on port 2-MSN (most significant nibble=bits 4-7) corresponding to the set of four discrete switches 153 and inputs data corresponding to the switch settings via port 1-MSN. This data is held temporarily in R5, just as all the other control parameters are. When B28 is reached the program branches to B23.

In block B23: the data in R5 is output as a 4 bit nibble to the first discrete register 109. On the next pass the status of switch 154 is transferred to the second discrete register 110 in like manner. Only two discrete registers are needed in the synthesizer described; but it should be apparent that additional switches, such as 153 and 154; and registers, such as 109 and 110, can readily be provided for simply by changing the constants in the instructions that control program branching as a function of CPN.

On the 25th pass through the minor loop CPN=18H, which causes the program to exit at B12 to B13.

In block B13: port 21 is set=1 to enable the envelope computer 200, registers R0-R32 are cleared to 0, and the built-in timer is started. Computer 100 then enters a wait loop if its INT input is low. After computer 200 sets INT high; computer 100 enables its interrupt, sets F0=0, and sets R0=38H. The builtin timer runs continuously and sets a timer flag, TF, when it overflows. This flag is tested in block B24, causing R33 (Time) to be incremented if it is true. The flag is reset automatically when it is tested.

In block B14: CPN (R38H) is set=0. The program now returns to B2 to start its major loop. F0 is invariably set=0 during the initial minor loop operations, hence the program branches from B4 to B16.

In block B16: the flag F0 is set=1 and a software interrupt of the envelope computer is initiated by setting port 20=1. During the execution of this interrupt the breakpoint parameter stored in R3A is complemented before being transmitted to the envelope computer via register 102. The attack parameter A (R3B) is converted to an 8 bit byte, using a table stored in locations 3D0-3DF of the program memory, before being transmitted. Similarly, the D1, D2 and R parameters are converted to 8 bit bytes using a different table stored in locations 3E0-3EF. These conversions, which are shown in Table II below, are performed for the benefit of the envelope computer; but are located in the keyboard computer to conserve memory space in the other computer. The purpose of the conversions will be explained in the description of the envelope computer operation. At the end of the interrupt sequence the data in R26, which is 0 at this point, is output to register 102. The envelope computer inputs this register repetitively to ascertain the status of the playing keys to which its five envelopes are assigned, if any. The program then returns to the major loop at B5 and proceeds as described previously until B11 is reached. Since F3 is now 0, and will remain so until the power is turned off, the program now always brances to B24.

In block B24: the envelope status is input from R202 and is stored in R27. The envelope computer repetitively outputs the status of its five envelopes to register 202, setting the corresponding bit to a "1" when an envelope is initiated and restoring it to "0" when the envelope has decayed to zero. As described above, the timer flag is tested and Time (R33) is incremented if it is true.

In block B31: R1 is set=28H, which is the first location in the group R28-R32 where the keyboard contact status is stored. R2 is set=1 to identify the current key group as F3-G3#. The 44 note keyboard contains 11 groups, as shown in Table I. There are two contacts per key; the "A" contacts (FIG. 1a) close near the beginning of a keystroke and the "B" contacts close near the end. Hence it takes two bits to define the status of each key. Thus a group of four keys requires eight bits of data, or a pair of nibbles, to define its status.

In block 32: R3 is set=0 to identify the current bit pair (bits representing the "A" and "B" contacts of a playing key). Since the keyboard status is manipulated as data bytes in which the LSN represents the "A" contacts and the MSN represents the "B" contacts, the value 0 in R3 identifies the current bit pair as bits 0 and 4. For masking purposes, the current bit pair is also identified as a 1 in the corresponding bit position 0-3 of R4; hence R4 is set=1. The current nibble pair is input from the keyboard by setting port 2MSN=R2 and then inputing port 1. The decoder 151 translates the four bits from port 2 into a 1 of 16 selection eleven of which correspond to the commoned contacts of four adjacent keys. The individual contacts of all of the keys are connected through isolating diodes to corresponding terminals of port 1. The input data is sorted @R1, i.e. at the location pointed to by R1, and the exclusive-or function of the previously stored data with the newly stored data is placed in the accumulator ACC (not shown).

In block 33: if there has been no change in any of the eight contacts associated with the first group of four keys, the ACC=0 and the program proceeds to B34.

In block B34: R1 and R2 are both incremented to point to the next key status storage location and the next group of keys respectively.

In block B35: R1 is tested to determine whether the entire keyboard has been scanned. If not, the program returns to B32 to input the status of the next group of keys. If so, the program continues the major loop at B54, processes the control parameter identified by CPN, and returns to the keyboard branch at B31.

Assume now that playing key C.sub.5 is depressed. The keyboard scanning operation proceeds as previously described until R1=2CH and block B33 is reached. At this point R2C=00001000 and ACC=00001000, hence the program branches to B36.

In block B36: bit 0 of ACC is tested to see if the "A" contacts of note A.sub.4 have changed state, and

In block B37: bit 4 of ACC is tested to see if the "B" contacts of note A.sub.4 have changed state. Since neither contact of note A.sub.4 has changed the program proceeds to B42.

In block B42: ACC is rotated right one bit, hence ACC now=00000100. R3 is incremented and R4 is left shifted to identify the bit pair in process as bits 1 and 5 of the original input data.

In block B43: R3 is tested to see if processing of the pair of nibbles has been completed. If so, the program returns to the keyboard input loop at B34; otherwise it loops back to B36.

In block B36: on the fourth pass ACC=00000001, hence the program branches to B44.

In block B44: the contents of ACC are saved in R17.

In block B45: ACC is set=R2C and is masked with R4 to test the "A" contact status of the playing key in process. If the test indicates these contacts are closed the program branches to B48.

In block B48: bits 0 and 1 of R3 are moved to bits 4 and 5 of ACC, then R2 is added to obtain a bit and group key identifier which is then compared with the key assignments stored in R1B-R1F in sequence. If a match is found a mask identifying the corresponding note generator is placed in R6. Thus when a playing key is operated repetitively the same note generator is selected each time.

In case no match is found; R26 and R27 are examined in search of an idle note generator; defined as one that has been released by the playing key to which it is assigned and whose envelope amplitude has decayed to 0 (or other predetermined minimum value). Hence an idle note generator has 0's in its corresponding bit position in both R26 and R27. If one or more idle note generators exist, the first one encountered is selected by placing a corresponding mask in R6.

In case no idle note generator is found, a search is made for a vulnerable note generator; defined as one that has been released by the playing key to which it is assigned and whose envelope amplitude has not decayed fully. R26 and R27 are again examined, this time for a 0 in R26 and a 1 in the same bit position in R27, and a mask of the vulnerable note generator is stored in R19 if one is found. If there is only one such note generator, the key in process is assigned to it; but if there is more than one, a software interrupt of the envelope computer is initiated by setting port 20=1. The envelope computer then identifies the vulnerable note generator having the lowest envelope amplitude and the keyboard computer assigns that note generator to the key in process.

In the event that there is no note generator available, as when the player depresses more that five keys, the program branches to B51.

In block B51: the "A" contact status of the key in process is set=0 @R1 so that the attempt to find an available note generator for this note will be repeated on subsequent scans of the keyboard. If a note generator is available, the program proceeds to B50.

In block 50: the "A" contact status in R25 corresponding to the assigned note generator is set=1. The present time from R33 is stored in the register of group R20-R24 that corresponds to the assigned note generator. The key identifier is stored in the register of group R1B-R1F that corresponds to the assigned note generator. ACC is then restored from R17 and the program returns to the previous loop at B37. Ordinarily, a change in state of the "B" contacts will not be detected in the same pass as the "A" contacts, but it is possible. In any event, the change in state of the "B" contacts will be detected in block B37, sooner or later, and the program will then branch to B38.

In block B38: the ACC is saved in R17.

In block B39: ACC is set=R2C, the MSN and LSN are interchanged and the result is masked with R4 to test the "B" contact status of the playing key in process (assumed to be C.sub.5 in the present instance). If the test shows the contacts are open, the program branches to B47, restores A from R17, and returns at B42. If the contacts are closed, the program proceeds to B40.

In block B40: R2 and R3 are combined to form the note identifier which is then compared with R1B-R1F successively to find the note generator assigned to the key in process. The time stored in the corresponding register in the group R20-25 is then subtracted from the present time, from R33, to obtain the elapsed time between closure of the "A" and "B" contacts of key C.sub.5. The number of leading zeros in the elapsed time are counted and multiplied by two. The result is increased by one if the first bit following the leading 1 is a 0. The result is complemented and stored in the register of group R20-R24 associated with the assigned note generator. This value is the touch response date (TRSP) and it replaces the start time, which is no longer needed. The object of the algorithm described above is to produce a touch response value that varies in an exponential relation to the travel time of the playing key. The "B" contact status of the assigned note generator is set=1 in R26 and is also output to register 102 to notify the envelope computer of the action. ACC is registered from R17 in B41 and the program continues, as previously described, at B42.

In response to the 1 output to register 102, described above, the envelope computer in due time sets the INT input of computer 100 low via register 203. The normal operation of the keyboard computer ceases upon completion of the instruction in process and the program counter is pointed to location 3, where the interrupt subroutine INT, shown in FIG. 2d, starts.

In block B53: the keyboard computer acknowledges the interrupt by setting port 20=1, saves ACC and three general registers as indicated, inputs an interrupt instruction from computer 200 via register 202, sets a 1 in R27 in the bit position corresponding to the note generator being serviced, transmits pitch and touch response data from the corresponding pair of registers in the group R1B-R24, and transmit pitch data as a serial data stream on port 00 to all shift and store registers, such as 303. Following the serial data stream, the strobe input of the shift and store register in the note generator being serviced is selectively pulsed via the RD output of computer 100, gate 106 and decoder 105. The serial data transmission allows use of the shift and store register 303 (RCA Type 4094) which saves components since it stores eight bits in one standard 16 pin package. Register 303 controls the pitch of the voltage controlled oscillator (VCO) 301 and selects the appropriate output from counter 304 via multiplexer 305 to drive computer 306 in accordance with the octave containing the note to be played. Finally, the registers saved at the start of the interrupt are restored and the program resumes at the point where it was interrupted. In the following, the operation of the keyboard computer in response to release of a playing key, C.sub.5 in the present example, is described.

As long as there is no change in state of the keyboard contacts the program loops through B32-B35 eleven times, with no branches to B36, then traverses the branches of FIG. 1a to process one control parameter before resuming the keyboard scan. This interleaving of the control parameter processing with keyboard scans provides more frequent scanning of the keyboard and still provides adequate processing speed for the control parameters.

As the C.sub.5 playing key is released, the "B" contacts open first. This causes the program to branch from B33 through B36, B37, B38, B39, B47, B42 and B43 without effect. When the "A" contacts open, the program branches from B36 to B44 and from B45 to B46.

In block B46: the note generator assigned to C.sub.5 is located as described previously for blocks B40 and B48. The corresponding bits in R25, R26 and register 102 are set =0. A wait loop is then entered until the envelope computer inputs the changed state of register 102. The program then returns to its normal loop via B47 and B42.

The operation of the capture system will now be described. In the illustrated embodiment there are 25 voice control parameters. They are vibrato rate and depth, pulse type tones at four pitches, nine harmonic components, five attack/decay parameters, two voltage controlled filter (VCF) frequency parameters, one VCF resonance (or Q) control, one switch set to select the VCF roll-off rate, and one switch to select the operating mode of the second VCF. When the player has found a set of these 25 parameters that he wishes to capture for future recall, he merely selects a two digit block location, using switches 155 and 156, and operates switch 152 to the STO position momentarily. Switch 156 selects one of any desired number of capture memories, each of which has 256.times.4 storage cells. These may be type 5101 (CMOS) memories which will retain data for one to two years when powered by a two cell hearing aid type battery. When the synthesizer is being played the capture memories are supplied with 5 volts through one diode and the two primary cells are isolated by a second diode. Each memory chip can store ten set-ups; or data blocks, of 25 parameters. As explained previously, the program converts the block select input from switch 155 into a block starting address in B15. When the STO mode is selected, the program proceeds from B19 to B20.

In block B20: port 23 is set =1 to select the capture memory and the digital value of the current parameter, held temporarily in R5, is stored in the corresponding location of the selected block in the selected memory chip, such as 103. During each pass through the major loop a different one of the 25 control parameters is stored in the selected block in like fashion. In a few tens of milliseconds, the entire block is stored.

Now suppose the player wishes to recall a set-up previously stored in the capture memory. In this case the mode switch 152 is operated to the RCM position. The program consequently proceeds from B5 to B6.

In block B6: port 23 is set=1 to select the capture memory and inhibit the decoder 105. The digital value of the current parameter is read from the selected block of the selected chip and is held temporarily in R5. During each pass through the major loop a different one of the 25 control parameters is read from the capture memory, converted to an eight bit byte when an exponential output is required; and is cyclically transferred to the corresponding clamp-and-hold circuit 111, or to the data memory at R3A-R3E. This cyclical operation continues as long as the selected set-up is in use, thus avoiding the need for any additional storage internal to computer 100 to provide the recall function.

Each time that the capture memory is accessed in B6 or B20, CPN must be added to the block starting address, R37, to obtain the capture memory address; and the indirect addressing register R1 must be pointed at the capture memory. To conserve instructions, the subroutine CM shown in FIG. 2c is employed to perform these operations.

III. Operation of the Envelope Computer

A memory map showing the allocation of the 3FH (64 in decimal notation) registers in the envelope computer is shown in Table III. Registers R0-R17 are common to all five of the envelope generators (EG1-EG5) implemented by this computer. Registers R18-1F are dedicated to EG1, R20-R27 are dedicated to EG2,--and R38-R3F are dedicated to EG5.

When power is applied to the computer 200 an internal reset pulse is generated to clear critical working resisters, such as the program counter. After the keyboard computer 100 has completed its initialization routine, it sets port 21=1 which terminates the reset pulse in computer 200 and allows operation under program control to commence at location 0 in the program memory. The program memory listing is shown in Table X, which appears at the end of the specification, but for simplicity the operation will be described with reference to the flow charts shown in FIGS. 3 and 4. A modified program listing is shown in Table XII. Operation with the modified program is described separately in Section IV.

In block C1: O1H is output to register 203 to initialize the INT and TO inputs of computer 100 to 1 and 0, respectively. Register 202 is set =0 to indicate all EG's are idle. RF and R11 are set=0 so as to cause the random initial envelope amplitudes EA.L and EA.H in R1E-R3E and R1F-R3F to be set =0 by the program, as described later.

In block C2: R10 is set =RF and RF is then set=register 102.

In block C3: the test input TO is checked to see if the keyboard computer is requesting a software interrupt. This is invariably the case turn-on, hence the program branches to C10.

In block C10: the software interrupt is acknowledged by setting the TO input of the keyboard computer=1 via register 203. A transfer instruction is then input via register 102.

In block C11: bit 5 of ACC is tested to interpret the instruction. Bit 5 is invariably false upon turn-on, requiring a block transfer of attack/decay parameter control data. Hence the program proceeds to block C12.

In block C12: the five quantities BC,A,D1,D2 and R are input in sequence from register 102 and are stored in R13-R17. These quantities have all been modified in form from the data that is input to the keyboard computer from the manual controls so as to take into account the manner in which the envelope computer implements the desired functions. These conversions were mentioned previously in the description of the keyboard computer and are shown there in Table II. The quantities D1,D2 and R, in particular, take the form of a preset count value located in the 5 LSBs used as a counter and the same preset value, expressed as a power of two, located in the 3 MSBs for use in resetting the counter. The quantity A takes either of two forms. In the first form A has a value between 0 and 5 (attack parameter=0 to A in Table II) corresponding to powers of two by which the attack slope is to be varied. Quantities of A in this range are moved to the MSN of R7 for use as the attack common exponent, as explained later. In this case R14 is set=21H to cause the A counter to recycle on every pass, as explained later. In the second form of A, (attack parameter =B to F in Table II) as output from the keyboard computer, the input quantity is similar to the D1,D2 and R form, but is increased by 6 to compensate for the effects of processing the data to obtain the attack common exponents. The program now skips over block C4 and returns to the main loop at block C5. Normally, the main program proceeds from block C3 to block C4.

In block C4: the A,D1,D2 and R counters, comprising the five LSBs of R14-R17, are each decremented by one. If any counter reaches 0, a corresponding bit position in R7 is set=1 and the counter is reset in accordance with the control parameter stored in the 3 MSBs of the same register. These three bits may represent any value from 1-6. The corresponding values to which the counter is preset are 00001, 00010, 00100, 01000, 10000, and 00000. The effect of these different preset values is to cause the flag bit in R7 to recur in every pass, every 2nd pass, every 4th pass, every 8th pass, every 16th pass, or every 32nd pass. Each flag remains set for only one pass following that in which the corresponding counter reaches 0.

In block C5: R0 is set=18H to point to the first register in the set dedicated to EG1. R6 is set=1 for use as a mask corresponding to EG1. The subroutine EGS is then called. Upon completion of the subroutine the program proceeds to Block C6 (not shown).

In blocks C6-C9: RO is set=20,28,30 or 38 on successive returns from subroutine EGS and R6 is set=2,4,8 or 10H for use as a mask. Upon the fifth return the program loops back to C2 and repeats the above sequence.

The operation of the EGS subroutine, shown in FIG. 4a, is described next.

In block C20: RF is exclusive-or'ed with R10 and masked with R6 to test for a change in state of the "B" contacts of the key to which the current EG is assigned. Before any keys are depressed, the result is always 0 and the program proceeds to C21.

In block C21: the accumulator ACC is set=R11, which holds the envelope status of EG1-EG5.

In block C22: ACC is masked with R6 to test the envelope status of the current EG. Assuming that the result is 0, the program proceeds to C23.

In block C23: the 16 bit envelope amplitude EA held in register pairs R1E,R1F-R3E,R3F; of the EG in process is cleared to 0.

In block C24: the analog multiplexer 205 is disabled via register 204. The 16 bit envelope amplitude is scaled down inversely with the pitch of the current note, held in R18-R38 and graduated in half-octave intervals. This scaling adjusts the envelope amplitude to make the output of the first voltage-controlled filter (VCF-1), such as 370, associated with the EG in process independent of the pitch of the selected note. Ports 1 and 2 in their entirety are then set=EA. Ladder network 206 converts the 16 bit digital envelope to an analog voltage that is buffered by an operational amplifier 207 before being directed to the analog multiplexer 205. Finally this multiplexer is pointed to the current note generator and is enabled to drive the corresponding clamp-and-hold circuit, such as 351. A two stage RC filter is employed for this circuit to smooth the steps in the envelope waveform so as to render them inaudible. Applicant has found that abrupt steps as small as 0.25 db are distinctly audible with long decay times. The program finally returns to the main loop, where it either advances to the next EG or returns to the beginning at C2.

Now assume that a playing key has been depressed fully and the keyboard computer has assigned EG1 to the note, which may be C.sub.5 as assumed previously. It will be recalled that the keyboard computer set register 102=1 in response to closure of the "B" contacts of playing key C.sub.5. Hence when the envelope computer calls EGS from block C5 (FIG. 3), the subroutine program branches from C20 to C31 (FIG. 4a).

In block C31: RF is masked by R6 to test the present state of the "B" contacts. Finding them closed, the program branches to C37.

In block C37: bit 0 of R11 is set=1 to mark EG1 busy. The keyboard computer is interrupted via register 203 and the mask in R6 is sent via register 202 to identify the EG requesting data. The keyboard computer responds to this request by sending the pitch and touch response data via register 102, which is input to R18 in the present instance. An attack characteristic is then calculated as described in the following.

It is desired that the attack waveform be a ramp implemented by incrementing a register by a selectable amount at periodic intervals until a level set by the touch response data is reached. Hence the size of the selectable increment is a function of both the attack time and the touch response. It is further desired that the attack time vary from a normalized value, selected by the parameter control, in accordance with the pitch of the note being played.

6 db intervals in touch response can readily be allowed for by shifting the normalized value of the increment; but, since it is desired that touch response intervals of 3 db be provided, the pitch data is right normalized, left-shifted one bit, and incremented by one if the touch response data is odd (i.e. includes a 3 db increment). The combined pitch and odd/even touch response data is then used to establish an initial envelope increment valua (INTB) by Table IV (located at 304-313 in the program memory) which is scaled to provide the desired relation between pitch and attack time.

The remaining touch response factor TRS (bits 1-3 of TRSP) is combined with the attack common exponent. The 16 bit length of the envelope amplitude and envelope increment registers is insufficient to allow determination of the attack slope solely by right shifting the increment INTB obtained from Table IV. Hence, a counter is used to vary the step width as well as the heigth. The attack common exponent, held in the MSN of R7, is the number of right shifts to be performed on the value of the increment derived from Table IV. The remaining touch response parameter TRS has a range of 0-7. corresponding to an audible range of 0-42db. Higher values of TRS require correspondingly higher values of the attack increment, hence correspondingly fewer right shifts of the increment value (INTB) read from Table IV.

TRS is complemented, with respect to 7, and the complement, CTRS, is added to the attack common exponent ACE from R7. If the result is <8, INTB is right-shifted (ACE+CTRS) bits and the individual AKC counter, R1A-R3A, is set=21 to minimize the step width. If the result is .gtoreq.8, INTB is right-shifted 7 bits and the remainder (ACE+CTRS-6) is set into R1A-R3A, in the same form as the common A,D1,D2 and R counters in R14-R17, to increase the step width accordingly. The required value of INTB is placed in EA, in the corresponding register pair R1C,R1D-R3C, R3D. Finally, the branch pointer (R19-R39) is set=B7H so that the program will branch to block C26 on the next pass.

In block C24: the output of the analog multiplexer 205 is inhibited. The envelope amplitude EA is scaled to the pitch stored in the MSN of R18-R38 and ports 1 and 2 are set=EAs, the scaled value of the envelope. The program shown in Table X is arranged to optionally omit this scaling of amplitude with pitch when the T1 input (not shown) of the envelope computer is set to a logic 1 level (see instruction 0A4). The analog multiplexer 205 is then pointed to the VCF controller of the current note generator and enabled via register 204. Finally the EGS subroutine returns to the main program. EA is usually=0 when block 24 is entered from block C37, hence the scaling operation has no effect. However, when a note is repeated before it has fully decayed, the value in EA when the key is struck again is preserved and the attack resumes from that value at a rate controlled by the new key velocity, or touch response. EA is always=0 when block C24 is entered from block C23. In this case the function of block C24 is to maintain the clamp-and-hold inputs of inactive note generators at their minimum level to prevent ciphers.

When note C.sub.5 is again serviced by EGS on the next pass of the program through its main loop, the program proceeds from C20 through C21, C22, and C25 to the attack branch at C26.

In block C26: The A counter flag in R7 is tested, if it is=0 the program branches directly to block C24, otherwise the individual attack counter AKC is decremented before branching to C24. If AKC reaches 0, it is reset using AK; and .DELTA.EA is added to EA to increase the envelope amplitude one step on the attack ramp. The touch response data TRSP is then used to obtain the corresponding final envelope value, using the look-up table shown in Table V and located at 314-323 in the program memory, which is compared with the present envelope value in block 27.

In block C27: if the present envelope value is below the final value the program branches to C24. When the final value is reached, following a number of passes through the main loop, the program proceeds to C28.

In block C28: the branch pointer R19-R39 is set=BAH to cause a branch to block C33 on the next pass. If the LSB of TRSP is 0, LNEXP (R1B-R3B) is set=OCH; if it is 1, LNEXP is set=18H. LNEXP is the address of a linear-to-exponential table shown in Table VI and located at 324 to 33B in the program memory. The contents of the table increase in 0.25 db intervals from 84H (132D) at 324 to FFH (225D) at 33B. The 3 MSBs of TRSP are right normalized and subtracted from 7 to obtain TE, which is stored in R1D-R3D since .DELTA.EA is no longer needed. During decay and release modes the envelope amplitude is obtained by reading the linear-exponential table at the address LNEXP and double right-shifting the data TE bits, hence TE is the power of two by which the data from the table is divided to obtain the envelope. The right-shifted value of the data read from the table at OCH or 18H is stored in EA.

Pitch (R18-R38) is used to form the address of Table VII, located at 33C-345 of the program memory, from which the data for counter DRC (R1A-R3A) is obtained. This data provides the desired variation in decay/release times, from the nominal value selected by the manual parameter controls, in accordance with the pitch of a selected note.

The present envelope amplitude EA is the final amplitude value established by TRSP and Table V. The breakpoint level B is with reference to this maximum value. B has a range of 0-F with a resolution of 1.5 db. To detect variations in envelope amplitude of 1.5 db during its decay, the current envelope level and envelope level counter held in R1C-R3C is provided. This register is initially set=F6H when the envelope is at its peak. The counter is decremented by 1 each time the envelope is attenuated by 0.25 db until the counter reaches 0. It is then reset to 6 and the current envelope level is decremented by 1. Accordingly, R1C-R3C is now set=F6H. The break level complement BC is then tested. If B.noteq.F, the program branches to C24. If B=F, the program proceeds to C30.

In block C30: the branch pointer R19-R39 is set=BDH to cause the program to skip the decay 1 branch and instead branch to block C35 on the next pass.

In block C33: the D1 counter flag in R7 is tested. If it is=0 the program branches directly to C24, otherwise DRC is decremented before branching to C24. If DRC reaches 0 it is reset, using a subroutine DRS described later, and LNEXP is decremented. The data is read from the LNEXP table at the new address. This data is 0.25 db less than the previous location. It is then double right-shifted as before by TE bits and stored in EA. ELC is also decremented. In the event ELC reaches 0 it is reset to 6 and EL is decremented. The new value of EL is compared with B by addition and testing for a carry.

In block C34: if EL>B the program branches to C24, otherwise it branches to C30 where the branch pointer R19-R39 is set=BDH to cause a branch to C35 on the next pass, instead of C33.

In block C35: the operations in the decay 2 mode are identical to those in the decay 1 mode; except that EL, ELC are not involved since no further envelope level testing is required, and the D2 flag in R7 is tested instead of D1 to determine when the individual DRC counter is to be decremented. The program continues to branch to C35 as long as the playing key remains depressed. When the "B" contacts are opened upon release of the key the program branches from C20 to C31 and thence to C32.

In block C32: the branch pointer R19-R39 is set=COH to cause the program to branch to C36 on the next pass. The program branches to C24 in the current pass.

In block C36: the operations in the release made are identical to those in the decay 2 mode, except that the R flag in R7 is tested instead of D2 to determine when the individual DRC counter is to be decremented. The program continues to branch to C36 until EA reaches 0, or until this envelope generator is reassigned by the keyboard computer. When EA reaches 0 the envelope status is set=0 in R11 by the PUEA subroutine described in the following. This causes the program to branch from C22 to C23 instead of C25 on subsequent passes.

There are many repetitive operations occurring in the preceding description. To conserve program memory space, several additional subroutines are used to perform these operations within the primary envelope generator subroutine EGS.

The first of these subroutines is CYLE, shown in FIG. 4b, which is called whenever the LNEXP table address R1B-R3B reaches 0. CYLE recycles the table address to 18H and increments TE in R1D-R3D, then returns control to EGS. CYLE is located at 2E6-2EE in the program memory.

The next subroutine PUEA, shown in FIG. 4C, is called to process and update EA whenever the envelope is incremented or decremented.

Before PUEA is called the data to be processed (such as data read from the LNEXP table) is loaded into R3 and the exponent of 2 by which the data is to be divided is loaded into R2. PUEA then double right-shifts the 8 bit data by R2 places and stores the 16 bit result in EA. The result is tested and if EA=0, the envelope status of the note in process is set=0 in R11. PUEA is located at 2CO-2E5 in the program memory.

Another subroutine DRS, shown in FIG. 4d, is used to recycle the counter DRC in the D1, D2, and R branch operations. DRS converts the pitch R18-R38 of the note in process to a corresponding preset value obtained from Table VII (shown above) and stores it in DRC. The DRS subroutine is located at 2EF-2FB.

It was previously noted in the description of the keyboard computer that in the event that there is no idle note generator, but there are two or more vulnerable note generators; the keyboard computer interrupts the envelope computer and requests it to identify the vulnerable note generator having the lowest amplitude. It was also previously noted that a software interrupt of the envelope computer results in a branch from C3 via C10 to C11 (FIG. 3) where the transfer instruction is interpreted. In the previous description of the interrupt, bit 5 of the instruction was a 0, signifying that a block transfer of B,A,D1,D2 and R data was required. When bit 5 is a 1, the program branches to C13.

In block C13: ACC is set=last status of "B" contacts, R10. R0-R3 are initialized for the vulnerability test. The status of the "B" contacts of the first note generator are then examined in C14.

In block C14: if the note generator being tested has not been released the program skips to C16, otherwise it proceeds to C15.

In block C15: TE (R1D-R3D) of the note generator under test is compared with the previous maximum value, which is held temporarily in R3. If the present TE is greater it is placed in R3 and a mask of this note generator is placed in R4.

In blocks C16 and C17: the program loops back to C14 until all five note generators have been tested, then proceeds to C18.

In block C18: the mask of the vulnerable note generator having the highest TE (lowest amplitude) is output to register 202 to identify it to the keyboard computer.

The above described method of selecting the most vulnerable note generator is limited in accuracy to the resolution of TE, but has been found adequate for this purpose. For greater accuracy, the absolute values of the envelope EA can be used in lieu of TE, but this requires more instructions, more free registers, and more execution time.

IV Computer Operation With Modified Programs

The operations described in the preceding sections occur when the program shown in Tables IX and X are used in the keyboard and envelope computers. Alternative versions of these programs are shown in Tables XI and XII, respectively. The changes in operation which occur when using the modified programs are described in the following.

One object of the alternative programs is to provide the envelopes with both nominal and pitch scaled amplitudes simultaneously, rather than optionally. This requires the use of additional output circuitry, as shown in FIG. 5, which is also described in the following. Another object is to provide finer gradation of the envelope time constants by the AD.sub.1 D.sub.2 BR presets. Still another object is to cause the envelope amplitude to vary as the square of the key velocity, rather than linearly, so as to obtain the desired dynamic range with less variation in key velocity; which facilitates rapid playing of soft passages.

The first object is easily accomplished because the envelope amplitudes EA are stored in normal amplitude form and are scaled in accordance with the pitch only when they are being output to ladder 206, as described previously under block C24. In the revised envelope computer program the nominal value of EA is output to register 204A via port 0 in block 24 before the scaling procedure takes place. Register 204A is set from port 0 and drives ladder 206A, having its output connected to analog multiplexer 205A through buffer 207A. The logic inputs to 205A are driven by the original register 204 to direct the nominal envelopes to the five note generators in synchronizm with the pitch-scaled envelopes.

The last object is attained by revising the algorithm implemented by instructions 08F-0BB of the keyboard computer program, described previously under block B40. In the revised algorithm TRSP is set=F if the elapsed time between key contact closures is.ltoreq.4, or is set=0 if the elapsed time is.gtoreq.40. If neither of these conditions is true, the leading zeros are counted, decremented by 1, and then multiplied by 4. The result is then decremented by 2 if the first bit following the leading 1 is=1 and by 1 if the second bit following the leading 1 is=1. The resulting value of TRSP is an approximation to the desired exponential and consists of three linear segments. The first algorithm required a 64:1 change in key velocity to produce a 36 db change in envelope amplitude, whereas the revised algorithm requires only an 8:1 change in key velocity.

Another change made in the keyboard computer program affects the block transfer of the B,A,D1,D2 and R parameters described previously under block B16. With the revised program the B parameter is complemented as before, but the other parameters are transmitted unaltered. Hence the conversions shown in Table II are not applicable. An alternative conversion is performed in the envelope computer, as later described herein. The keyboard program modification is effected by inserting NOP's in locations 225-228 23C-244, and 257-25A.

The remaining object of providing finer gradations in envelope control is accomplished in one manner for the attack phase and in a second manner for the decay/release phase. Considering the attack phase, as previously described under block C37 the pitch data is combined with the odd/even touch response data to establish an initial envelope increment value INTB by Table IV. Since the data stored in the odd locations of this table are 3 db greater in value than that stored in the next lower even location, this approach allows the slope of the attack ramp to be varied in 3 db steps, i.e. by a factor of .sqroot.2, to compensate for 3 db variations in the final amplitude, which is selected by the touch response value TRSP, but does not provide for 3 db variations in slope by the attack parameter A. In the revised envelope computer program this table is rearranged by interchanging the odd and even data values and then doubling the values in the odd locations, as shown in Table IVA. To use this table, the program complements bit 0 of the attack parameter and exclusive-ors it with bit 0 of the touch response data. The pitch of the selected note is right normalized and left shifted one place as before and the exclusive-or term (A.sub.o .sym.TRSP.sub.o) is then introduced in the 0 bit position. The result is used to address Table IVA to obtain INTB. Assuming, for example, that note C.sub.5 has been selected, then the pitch=9 and either 80 or B6 is read from the table depending on the state of the exclusive-or term. A.sub.o is then added to TRSP and the sum is right shifted one place to obtain TRS as before; but TRS now has a range of 0-8, rather than 0-7, as a result of the addition of the attack bit A.sub.o.

TRS is complemented, with respect to 8 now rather than 7, and the complement CTRS is added to the attack common exponent ACE from R7 as before to determine the number of right shifts to be performed on INTB. The resulting value is placed in EA in the corresponding register pair R1C,R1D--R3C,R3D as before. This value is "80" if the attack parameter A=0 (minimum attack time) and TRSP=F (maximum envelope amplitude), since A.sub.o =1 and TRSP.sub.o =1 result in no right shifting of INTB. If A is increased to 1 or TRSP is decreased to E, but not both, then "B6" is read from the table as INTB; which is then right shifted one place to become EA="5B". If A=1 and TRSP=E, then "80" is read from the table as INTB; which is then right shifted one place to become EA="40".

Now considering the decay and release phases D1,D2 and R, as shown in Table VI and described under blocks C28 and C33, the envelope amplitude is decremented in increments of 0.25 db by incrementing the table address LNEXP by 1. Gradations in decay rate are produced by varying the range of the common and/or individual counters that control the time duration between increments. The program provides for selection of time intervals in 6 db steps; i.e. in multiples of 2.sup.n where n is an integer. To provide finer gradation, Table VII could be enlarged to provide a second set of preset values for DRC ranging from 3 to E in addition to the 2 to A range shown. This would provide for variations in step width of approximately 3 db. A preferable approach is employed in the modified program, shown in Table XII, in which provisions are made for incrementing LNEXP by 2,3,4,6,8 or 12 steps at a time. This enables the desired finer gradation to be obtained and also allows faster decay rates to be achieved at times with no change in computer speed. The values of step size to be employed in each of the three decay modes is designated .DELTA.D1, .DELTA.D2 and .DELTA.R.

A table is added to the envelope computer program to aid in establishing the required values for .DELTA.D1-.DELTA.R. This table is located at addresses 344-34D and is shown in Table VIII, in which column .DELTA.DDR shows the data stored in the first four locations and column XPS,XCTR shows the data stored in the next six locations. Following a block transfer of B,A,D1,D2 and R parameters, described previously under block C12, bit 0 of A (or A.sub.o) is complemented and stored in the bit 7 position of R7. D1 is then tested and if .ltoreq.4 the corresponding value of .DELTA.D1 is read from the table and is subsequently stored in the LSN of R13 along with BC. "21" is stored in R15 to cycle the D1 counter at its maximum rate. If D1>4 the corresponding value of XPS,XCTR is read from the table and stored in R15. "3" is stored in .DELTA.D1 if D1 is even, or "2" is stored in .DELTA.D1 if D1 is odd. D2 and R are operated on in like fashion to obtain corresponding values of .DELTA.D2 and .DELTA.R2, which are stored in the LSN and MSN halves of RE, respectively. The corresponding values of XPS,XCTR are stored in R16 and 17, as before.

Another modification in the program shown in Table XII is made to prevent premature release due to key contact chatter or player error. The operations described under block C32 are deleted, hence the program flows from block C31 directly to C24 in the first pass following opening of the "B" contacts. (see FIG. 4a). On subsequent passes the program branches in block C22; but now goes to block C40, in lieu of block C25, as shown in FIG. 6.

In block C40: with the "B" contacts closed the program flows to block C41 in lieu of block C25.

In block C41: the branch pointer is tested and, if found set to attack, the program branches to C26 to continue execution of the attack phase until it is completed and the decay 1 phase is entered. On the next pass following the completion of attack the program flows from block C41 to block C36 to initiate execution of the release phase.

V. Operation of the Note Generator

The note generator 300, shown in the lower half of FIG. 1b, is an improvement on the note generator previously disclosed by the present inventor in U.S. Pat. No. 4,070,943, entitled "Improved Organ Keying System", issued Jan. 31, 1978. Harmonics of sine wave form having sufficient purity for use in additive synthesis of musical tones were provided therein by a novel circuit arrangement that also functioned as a keyer. The circuit arrangement comprised a resistive path between a square wave tone source, in the form of a binary divider, and a tone utilization circuit; and a transistor switch connected in the resistive path so as to increase the absolute value of tone current during the second and third quarters of each half-cycle. The transistor switch was operated by an exclusive-or gate having its inputs driven by divider stages one and two octaves above that used as the square wave tone source. By appropriate choice of the relative magnitudes of the steps in the resulting waveform, the third and fifth harmonics were effectively eliminated. The remaining harmonics were effectively eliminated by a low pass filter, or integrator, in the utilization circuit. In the improved system there is no need for the transistor switches; instead a ROM (read-only memory), or equivalent logic circuitry, with a unique bit pattern and appropriately weighted resistive outputs provides the desired waveshape. The size of the ROM used in the illustrative embodiment was determined in part by what is commercially available. Texas Instruments type 74S470 (256W.times.8B) was chosen for ROM 307 and type 74S188 (32W.times.8B) was chosen for ROMs 308 and 309. These are read-only memories that are programmable by blowing fusible links (PROMs).

There must be an integral number of cycles of each harmonic for each pass through the memory. Thus there must be 3 cycles of S3H (sub-third harmonic), 6 cycles of 3H, 10 cycles of 5H, and 12 cycles of 6H programmed in ROM 307. Since the top note of the keyboard is C.sub.7 with a fundmental pitch of 2093 hz, the memory must be accessed (2093.div.2)W times per second, where W is the number of words in the memory. For W=256, the access rate is 268 k/sec. The circuitry has been arranged to access alternate locations for the top octave, effectively making W=128, which reduces the oscillator frequency to a value more suitable for the preferred VCO (Teledyne 9400).

Referring now to FIG. 1b, VCO 301 operates continuously at a selected one of 12 frequencies between 70,969 hz and 133,952 hz. The frequency is determined by a network of precision resistors 302 which are switched between -5 volts and +5 volts by the shift-and-store register 303. A low frequency VCO, common to the five NG's, is provided to produce a vibrato effect. Register 303 also controls a dual multiplexer 305 to select octave submultiples of the VCO frequency from counter 304 to drive the second counter, or divider, 306 and ROMs 307 and 308. For the top octave, the LSB of the address input of these ROMs is held constant and the 2nd LSB is connected directly to the top output of counter 304. Since there is then one memory access for each VCO cycle, this connection provides the required 134 k/sec access rate of 128 locations for the highest note, C.sub.7. For the next lower octave the LSB is connected to the top output, thereby providing a 134 k/sec access rate of 256 locations for the next highest note, C.sub.6. For each succeeding lower octave the LSB is connected to correspondingly lower stages of counter 304. ROM 309 produces output signals at 1/4 the frequency of ROM 308, hence its address inputs are connected to correspondingly lower frequency outputs of counter 306.

The four pulse type waveshapes each require only one bit of each memory word. Two locations of the 16'P bit store 1's and 30 locations store 0's. The 16'P output, (all are open-collector type) is connected through resistor 314 to an output of clamp-and-hold 111 and through a diode 315 to a resistive divider network 316-318. The divider network scales the inputs to preamp 319 so as to compensate for the roll-off of VCF-1 (370), which is a tracking type of damped integrator. The diode 315 can be replaced by a resistor, but the diode is preferred because it provides a threshold above the V.sub.SAT output of the ROMs, which are bipolar devices. If ROMs having field-effect type output transistors are used there is no need for this diode.

The nine sine type waveshapes each require two bits of each memory word. One of these bits is programmed with a square wave pattern; for example, the SH has one bit with 16-1's followed by 16-0's. The other bit is programmed with the inverted exclusive-or function (f.sym.2f.sym.4f), where f is the frequency of the square wave. Thus the other bit of SH has 4-1's, 8-0's, 4-1's, 4-0's, 8-1's, and 4-0's in succession. If the first bit is designated A and the other B, the sequence of logical combinations occurring in one cycle is AB, AB, AB, AB, AB, and AB.

The two ROM outputs for a given harmonic are each connected through a resistor, such as 310 and 311, to a single output of clamp-and-hold 111, and through a diode, such as 312 and 313, to the resistive divider 316-318. The resistors 310 and 311 are chosen to have a ratio of approximately 2.5:1, whereby the ratio of the peak signal to the first step in the resulting AC waveform at the output of amplifier 319 is approximately 2.3:1. As fully described in the prior U.S. Pat. No. 4,070,943, mentioned earlier, this waveshape is practically devoid of 3rd and 5th harmonics and contains no even harmonics. Alternatively, the resistors 310 and 311 may be equal and the desired weighting may be accomplished by connecting diodes 312 and 313 to different points on the resistive divider 316-318. The amplitudes of each of the harmonics, SH-8H, and each of the pulse waveshapes, 16'P-2'P, is independently controlled by a corresponding output of the clamp-and-hold 111.

The harmonics produced by ROM 307 are not identical to that described above for the SH since these harmonics are not related to SH by a factor 2.sup.N, where N is an integer. However, ROM 307 is programmed to provide waveshapes having 8 steps/cycle with step changes as near the desired 1/8 cycle intervals as possible with the 256 memory words available. The results have been found to be perfectly satisfactory for the intended purpose.

An alternative allocation of memory words which provides uniform width steps for the S3H, 3H, and 6H is possible if two different waveshapes are used. If the 8H has 6 steps/cycle and the 6H has 8 steps/cycle, both can be provided in a 48 word memory with no variations between the cycles of either one. Their submultiples may have proportionately more steps, or proportionately fewer words. The same sequence of logical combinations (AB, AB, AB, AB, AB, and AB) is produced for the six steps/cycle waveform, the only difference being that each combination has a duration of 1/6 cycle. The reason the embodiment described above is preferable is because the 6 step waveform cannot be proportioned so as to effectively cancel both the 3rd and 5th harmonics. By choosing resistors 310 and 311 to have a ratio of 3:1 the 3rd harmonic is cancelled in the 6 step waveform. The ratio of the peak signal to the first step in the resulting AC waveform at the output of amplifier 319 is 2:1 in this case.

The signals developed across divider 316-318 are amplified and level-shifted by preamp 319 before reaching the input of VCF-1. VCF-1 is a conventional damped integrator (a low-pass filter with 6 db/octave roll-off), which may use a type 3080 variable transconductance amplifier for 371 and a type 3240 amplifier having MOSFET inputs for 372. The cut-off frequency f.sub.co1 of filter 370 varies directly with the current supplied to the control input of 371 by another variable transconductance amplifier 355 in the VCF controller 350. The current output of 355 is in turn proportional to the product of the current supplied to its transconductance control input by transistor 353 and the voltage produced at its--input by an output of clamp-and-hold 111. The latter is the FC1 signal produced by one of the parameter controls, or its equivalent from the capture memory. The current from transistor 353 is directly proportional to the envelope signal maintained on clamp-and-hold 351. Amplifier 352 (type 3240) developes a matching voltage across resistor 354 and thereby produces a proportional current in the collector of 353.

The circuit constants of controller 350 are chosen so that when FC1 is at its minimum value, a playing key is struck forcefully enough to produce the maximum touch response signal, and the envelope signal is at its peak; f.sub.co1 is near the subharmonic frequency of the selected note. The envelope signal is scaled to the pitch of the selected note by the program, hence the above statement holds true irrespective of which note is played. All of the signals above f.sub.co1 are attenuated by the filter in inverse proportion to their frequency, hence the pulse waveforms become sawtooths and the harmonic waveforms become practically pure sine waves. The resistive divider 316-318 pre-weights the digital signal representations to compensate for the attenuation of the desired harmonic signals. As the envelope decreases from its peak value, f.sub.co1 decreases proportionately. The output of filter 370 accordingly decreases proportionately with no change in the waveform of the signals since they all lie on the constant slope of 6 db/octave. Hence, under these circumstances, filter 370 actually performs the function usually performed by a VCA in addition to its filter function. The same thing occurs if the amplitude of the envelope is reduced as a result of a less forceful operation of the playing key. The envelope shape is unchanged, it is simply scaled down; hence the signal output of filter 370 is scaled down without effect on the waveshape.

The FC1 control enables the maximum value of f.sub.co1 to be increased from near the subharmonic to near the eighth harmonic, or anywhere in between. In this way the pulse input waveforms can be made to vary from sawtooths to pulse output waveforms as the envelope increases, either due to the force with which the playing key is struck or due to the envelope shape created by the ADR controls. Harmonic mixtures are likewise caused to vary in composition with the envelope amplitude.

The output of VCF-1 is connected to the input of VCF-2 (380), which is a modified two-pole Butterworth filter. A variable gain stage, comprising FET 386 and amplifier 387, is provided in a feedback path from the output of 385 to the capacitor 382 of the first stage to allow a variable amplitude peak to be produced at the cutoff point. The gate of FET 386 is connected to the output of clamp-and-hold 111 that is associated with the Q control. Amplifiers 383, 385 and 387 may be type 3240's and the variable transconductance amplifiers 381 and 384 may be type 3080's. The transconductance control inputs of 381 and 384 are connected in parallel to another variable transconductance amplifier 356 which is connected to the output of clamp-and-hold 111 associated with FC2 and a transistor 357, in like manner to 355, when transmission gate 359 is selected by operating switch 154 to one of its closed positions. The cutoff frequency f.sub.co1 of VCF-2 is then varied in accordance with the envelope waveshape as modified by the FC2 control.

When switch 154 is operated to its other closed position, gate 358 is selected to connect the transconductance control of 356 to the resistor net 302 so as to vary f.sub.co2 solely in accordance with the pitch of the selected note. In this case VCF-2 affects the timbre of all notes under control of the FC2 and Q controls, but independently of the signal amplitude. The gate 358 and resistor net 302 are low impedance relative to the control input of 356 so that linear voltage signals from net 302 produce exponential current inputs to 356.

When switch 154 is operated to its open position, transmission gate 360 is selected by logic gate 361. In this case a fixed current is supplied to the control input of 356 so that VCF-2 operates as a simple formant filter with a variable f.sub.co2 controlled manually by the FC2 parameter control.

An analog multiplexer 388 controlled by register 109 connects the audio output 390 through mixing resistor 389 to either the output of 372 in VCF-1, or the first stage output of VCF-2 at 383's output, or the second stage output of VCF-2 at 385's output. This selection of output points allows the final roll-off rate of the filter to be varied from 6 db/octave to 18 db/octave. The FC1 and FC2 controls allow the corresponding cut-off frequencies f.sub.co1 and f.sub.co2 to be made equal, if desired, or to be separated by many octaves; whereby a wide range of tone colors and tone color variations with amplitude can be achieved.

The programs listed in Tables IX through XII each require less than 1024 words of ROM, hence each can be implemented in an Intel 8048 microcomputer. It should be apparent to those skilled in the art that a single microcomputer, such as Intel's 8049, can be programmed to perform the functions of both the keyboard and the envelope computer. The 8049 has a 2048 word ROM, a 128 word RAM, and will operate at an 11 mhz clock rate, which is practically twice the speed of the 8049.

Consequently a single 8049 could perform the combined programs at the same rate as the two 8048s do. Although one microcomputer would be eliminated with this approach, additional peripheral components, such as a port expander, would be needed to compensate for the reduced input/output of a single 8049 compared to the two 8048s.

Although the invention has been described and illustrated in detail, it is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the invention being limited only by the terms of the appended claims.