Means for Reducing Current-Gain Modulation Due to Differences in Collector-Base Voltages on a Transistor Pair

This invention relates to circuits using a transistor pair and more particularly to improvements designed to reduce current-gain modulation arising from differences in the collector-base voltages of the two transistors.

Some high precision circuits that use transistor pairs operating at high voltages often suffer from what is termed current-gain modulation. This is also known as Early effect. When the collector-base voltage of a transistor changes, for example, due to varying load conditions, the current gain, particularly the alpha, changes, as does the base emitter voltage that is required to produce a particular current. When two such transistors are operated in a current mirror configuration where the two load currents should always be equal and track each other, such operation is difficult to achieve, particularly where the two transistors operate with different base-collector voltages.

The invention is particularly directed to improvements in transistor circuits of the kind in which a pair of transistors having their bases connected in common are fed substantially equal constant currents in their respective emitter paths. A load is coupled separately to each collector of the transistors.

In accordance with the invention, means are provided for maintaining the collector-base voltages of the two transistors equal, thereby maintaining their current gains (alpha) equal at all times even under conditions of varying load. In a specific embodiment of the invention, an operational amplifier is coupled between the collectors of the two transistors with current feedback to the collector of the transistor normally having the higher collector-base voltage.

FIG. 1 is a block diagram showing the circuit according to the invention.

FIG. 2 is a schematic diagram showing the circuit of the invention in greater detail.

In FIG. 1 a pair of PNP transistors Q.sub.1 and Q.sub.2 have their bases connected in common to a bias supply V.sub.BIAS. A first constant current source 10 is connected in the emitter circuit of the first transistor Q.sub.1 providing a first current I.sub.1. A second constant current source 12 is connected in the emitter circuit of the second transistor Q.sub.2 providing a second current I.sub.2. The two currents I.sub.1 and I.sub.2 are equal.

A first load 14 is connected in the output collector circuit of the first transistor Q.sub.1, and a second load 16 is connected in the output collector circuit of the second transistor Q.sub.2. The second load voltage V.sub.3 is assumed to be more negative than the first load voltage V.sub.1. Under these conditions and in the absence of the invention the voltage V.sub.2 at the collector of the second transistor Q.sub.2 would be greater than the voltage V.sub.1 at the collector of the first transistor Q.sub.2, the two base voltages being equal. Since the transistors Q.sub.1 and Q.sub.2 would have different collector-base voltages, they would also have different alpha current gains, thereby giving rise to the current gain modulation effects already discussed.

In order to overcome these objectional effects, an operational amplifier 18 is connected to the collector outputs of the transistors Q.sub.1 and Q.sub.2 and the output of the amplifier 18 is fed back to the collector of the second transistor Q.sub.2, which has the higher collector-base voltage V.sub.cb. In particular, the collector of the first transistor Q.sub.1 is coupled to the inverting or negative input of the amplifier 18, and the collector of the second transistor Q.sub.2 is coupled to the non-inverting or positive input. The output of the operational amplifier 18, is coupled to the base of the buffer amplifier Q.sub.3, the emitter of which is coupled to the second load 16, and the collector of which is coupled to the collector of the second transistor Q.sub.2.

The operational amplifier 18 serves to maintain the collector voltages V.sub.1 and V.sub.2 equal and thus equalizes the respective current gains (alpha). Thus even though the base collector voltages and current gains may vary, the amplifier 18 forces them to track each other and keep them equal.

The collector current of the buffer amplifier Q.sub.3 will be equal to the current in the collector of the second transistor Q.sub.2 since the input bias current of the operational amplifier can be made so small as to be negligible. The emitter current of the buffer amplifier Q.sub.3 will differ from its collector current, but the so-called early effect of an NPN transistor such as Q.sub.3 is much less than that of a PNP transistor such as Q.sub.2. The overall effect of this circuit arrangement is that the output current fed to the second load 16 from the emitter of the buffer amplifier Q.sub.3 is independent of the second load voltage V.sub.3.

FIG. 2 is a schematic diagram showing the circuit of the invention in greater detail. An input control current I.sub.SIG from a current generator 20 is fed to a PNP bias transistor Q.sub.4 and emitter resistor R.sub.1. The voltage on the base of the bias transistor Q.sub.4 provides the bias for the PNP transistors Q.sub.1 and Q.sub.2, whose bases are connected in common with the base and collector of transistor Q.sub.4. The equal emitter currents I.sub.1 and I.sub.2 of transistors Q.sub.1 and Q.sub.2 flow through emitter resistors R.sub.3 and R.sub.2 respectively.

The output of first transistor Q.sub.1 is fed to a buffer amplfier consisting of three NPN transistors Q.sub.10, Q.sub.11, Q.sub.12 to provide the high output current by the first load 14. The bases of transistors Q.sub.11 and Q.sub.12 are connected together and to the emitter of buffer transistor Q.sub.10. The emitters of transistors Q.sub.10, Q.sub.11 and Q.sub.12 are coupled through resistors R.sub.8, R.sub.7 and R.sub.9 to the first load 14. The collectors of transistors Q.sub.10 and Q.sub.12 are connected together and to ground. The base of transistor Q.sub.10 and the collector of transistor Q.sub.11 are coupled to the collector of the first transistor Q.sub.1 to receive the collector current of the first transistor, the voltage V.sub.1 at that point being the collector voltage of the first transistor Q.sub.1.

In the buffer amplifier the majority of the output current of the first transistor Q.sub.1 is sunk by transistor Q.sub.11 and resistor R.sub.7. The voltage on the base of Q.sub.11 provides bias to the high current transistor Q.sub.12. This causes the majority of the current in the output current mirror, which consists of transistors Q.sub.10, Q.sub.11 and Q.sub.12, to flow through transistor Q.sub.12 and resistor R.sub.9. The buffer transistor Q.sub.10 serves to keep the base current of transistors Q.sub.11 and Q.sub.12 from loading the collector current of the first transistor Q.sub.1.

The collector outputs of the transistor pair Q.sub.1 and Q.sub.2 are coupled to transistors Q.sub.9 and Q.sub.6, respectively, which at their respective inputs have their bases and collectors connected together. The transistors Q.sub.9 and Q.sub.6 provide the differential input for the operational amplifier 18 shown in FIG. 1. Transistor Q.sub.9 provides the negative or inverting input, and transistor Q.sub.6 provides the positive or non-inverting input. The output of the operational amplifier is taken from the collector current of a transistor Q.sub.7, whose base is connected to the base of transistor Q.sub.6 which is the positive input. A transistor Q.sub.8 having its base connected to the base of transistor Q.sub.9, which is the negative input, serves as a balancing transistor. Resistors R.sub.4, R.sub.5, R.sub.5 ' and R.sub.6 are coupled from a common connection to the respective emitters of transistors Q.sub.6, Q.sub.7, Q.sub.8 and Q.sub.9 and provide emitter ballasting.

Three transistors Q.sub.16, Q.sub.17 and Q.sub.18 provide bias current to the operational amplifier. A current source 22 supplies bias current to the common bases of the transistors Q.sub.16, Q.sub.17, Q.sub.18. Resistors R.sub.13, R.sub.14, R.sub.15 connect the respective emitters of the transistors Q.sub.16, Q.sub.17, Q.sub.18 to a source of potential, such as a battery, which in the case of the NPN transistors is a negative supply.

The equivalent of the buffer amplifier Q.sub.3 of FIG. 1 is provided by three transistors Q.sub.13, Q.sub.14, Q.sub.15. Resistors R.sub.10, R.sub.11 and R.sub.12 couple the respective emitters of the transistors Q.sub.13, Q.sub.14, Q.sub.15 to the second load 16.

The output collector current of the transistor Q.sub.7 of the operational amplifier is coupled to one collector and base of a PNP transistor Q.sub.5, which serves as a level shifter; that is, by means of transistor Q.sub.5, the positive voltage at the collector of transistor Q.sub.7 is shifted down to the negative voltage at the base of transistor Q.sub.15 and the collector of transistor Q.sub.16. The collector output of the transistor Q.sub.5 in turn drives the base of transistor Q.sub.15 in the buffer amplifier. The emitter output of transistor Q.sub.15 in turn drives the bases of the output transistor Q.sub.14 and the feedback transistor Q.sub.13. The emitter currents of the output transistor Q.sub.14 and the feedback transistor Q.sub.13 are fed to the second load 16. The collector current of the feedback transistor Q.sub.13 is fed back to the collector of the second transistor Q.sub.2 and to the base of transistor Q.sub.6, which is the positive input of the operational amplifier.

The collector current of the feedback transistor Q.sub.13 is approximately equal to the collector current of the second transistor Q.sub.2. More importantly, the voltage V.sub.2 on the collector of the second transistor Q.sub.2 is equal to the voltage V.sub.1 on the collector of the first transistor Q.sub.1, thereby rendering the alpha current gains of the transistors Q.sub.1 and Q.sub.2 equal and avoiding the Early effect mismatch.