Binary Output Processing in a Digital Computer Using a Time-Sorted Stack

This invention is related to the inventor's commonly-assigned and copending applications Ser. No. 48,201 entitled "IMPROVED BINARY INPUT PROCESSING IN A DIGITAL COMPUTER" and Ser. No. 48,200 entitled "IMPROVED BINARY INPUT/OUTPUT PROCESSING IN A DIGITAL COMPUTER."

This invention relates to improved binary output processing in a digital computer.

Digital computers use a plurality of bits of binary input data to produce binary output data in response to a program operating, at least in part, on or in response to the binary input data.

Microprocessors and other digital computers perform programmed mathematical and other operations in response to binary input data supplied to the digital computer. A plurality of data input lines may be continuously monitored for the purpose of detecting transitions in any of the input lines. The transitions are a change from one state to another of any of the bits of binary input data represented by the signals applied to the digtal computer input lines. The binary data inputs to the digital computer may, either alone or in combination, represent a quantity, a time or the occurrence of an event.

Input data received by the digital computer is supplied to its central processing unit which, under program control, manipulates and processes the input data. As a result, binary output data is produced.

In a prior art digital computer system having a multiple binary data input line, the digital computer sequentially observes the voltage level on each of the input lines on a repetitive basis. A real time counter keeps track of the time and, if a transition occurs on one of the input lines, the transition is stored in a register along with the time at which the transition occurred. Interrupt logic is provided which, upon the occurrence of the transition, causes the digital computer to process information represented by the binary input data on that line, perhaps along with data on the other data input lines.

Prior art control of digital computer binary output data has been achieved through use of a compare register. The compare register holds both a single command or data byte to be put out by the digital computer along with a time at which the command is to be executed. The computer compares the command time in the register with real time obtained from a clocked counter. The command is sent out to a device to be actuated or to a recoring device when a predetermined comparison result is achieved. Each command or data byte to be outputted must be sent out at a different time. The commands or data bytes are sent out serially.

U.S. Pat. No. 4,048,625 to Harris et al. teaches the use of a first-in, first-out (FIFO) memory in conjunction with a RAM to provide improved data throughput in a printing control system. Input characters are applied to the FIFO memory and the characters to be printed are then sent to the RAM. The FIFO memory is said to increase the throughput of the print control system by the elimination of the use of "fill characters" or the aternative need to suspend the receipt of input characters. It appears that the FIFO memory allows input data received by the memory to be put out therefrom at a constant range even though the rate of receipt may vary.

U.S. Pat. No. 4,062,059 to Suzuki et al. discloses a FIFO stack acting as a buffer and connected between first and second information processing units. A control circuit detects the full and empty states of the FIFO stack, and programmed information from the digital-computer central-processing unit establishes interrupt conditions with respect to the full and empty states of the FIFO stack.

U.S. Pat. Nos. 3,815,096 to Nahon; 3,952,289 to Baligant; 3,990,559 to Martin et al.; 4,024,508 to Bachman et al.; and 4,034,349 to Monaco et al. teach or disclose FIFO memories, buffers, stacks, or control devices therefor such as empty/full flags for the registers in a FIFO stack.

U.S. Pat Nos. 3,794,981 to O'Connor; 4,003,031 to Kashsio; 4,030,077 to Florence et al.; and 4,031,520 to Rohner all are of general interest with respect to sorting of information or its arranging.

In a search of the prior art, no patent reference was located that teaches the concept of a self-sorting output stack which time-sorts or time-orders its own entries by comparison of a real time count with an output digital byte. However, U.S. Pat. No 3,713,107 to Barsamian appears to teach the concept of an internally programmed "firm ware" sort processor that performs a sort routine outside of the computer's central processing unit. The sort processor uses the main memory of a central processing unit on a lower priority basis and includes a search memory which has a sector designated for storing and searching key words. A logics section is also incorporated in this sector for comparison of key words, but these key words are not specifically related to a time-ordering concept. Also, U.S. Pat. No. 4,021,779 to Gardner is relevant for its teaching of the use of a microprogram controlled unit and an interactive processor which produces system control signals. The processing elements may be self-sequencing store configurations. U.S. Pat. No. 4,027,291 to Tokura et al also is relevant because of its disclosure of an access control unit for controlling memory device having a plurality of memory units for storing data. Comparison is accomplished through addressing means.

In the prior art, it has been typical to provide in the output structure of a digital computer a single "compare" register that holds a time at which a single command or date byte is to be sent out. The command or data byte is in a separate register as pending output data. When the real time becomes equal to the desired output time stored in the compare register, the pending output data is sent out. Each byte of pending output data must be outputted before the next byte of output data is transmitted by the computer central processing unit to the output register. The central processing unit must handle the assignment of output times to the bytes of output data and must manipulate these output bytes under computer program control. This generally interrupts program calculations and limits computer throughput.

In accordance with the present invention, a digital computer has a real time counter and a memory/address bus. The digital computer generates binary output data comprising bytes having at least one bit of output information. The binary output data is generated in response to a program operating on binary input data. Improved processing of the output data comprises the steps of entering bytes of binary output data in a stack. Each byte is assigned a desired output time by the digital computer, and these are entered in the stack together with the associated bytes. The bytes and their desired output times are made available on the memory/address bus. The entered bytes of binary output data and their corresponding output times are time-sorted. The desired output time of the binary output data byte in the stack having the earliest desired output time is compared with the count in the real time counter. When the real time count and the desired output time correspond, the binary output data byte, whose desired output time was compared, is made available as an output. One-by-one in this manner the desired output times of the stack entries are compared with the real time and their corresponding data bytes put out.

A self-sorting stack is utilized to provide time-ordering of the bytes of output data. Each time the comparison of the desired output time of a byte of output data with a binary number count in the real time counter produces a predetermined result signifying correspondence of the real time with the desired output time, the output data byte is made available by the digital computer to whatever item of circuitry or equipment is to utilize the output data.

The invention improves the reliability of digital computer calculation and output. Also, the throughput of the digital computer is improved because the central processing unit thereof no longer is required to control the actual transmission to external circuitry or equipment of calculated output data. Instead, with the present invention, the output data transmission is controlled automatically with the use of a self-sorting output stack. This allows the computer central processing unit to proceed with its calculations uninterrupted in general by any need to control the transmission of binary output data.

The invention may be better understood by reference to the detailed description which follows and to the drawings.

FIG. 1 illustrates the input and output circuitry of a digital computer. FIG. 1 does not show the central processing unit, memories, and master clock conventionally associated with digital computers, but these are understood to be connected directly or indirectly with the memory/address bus 10 shown in the drawing. The digital computer input/output circuitry depicted in FIG. 1 and described herein is suitable for use in motor vehicle engine control applications and is described to some extent accordingly. Of course, the general purpose digital computer and input/output circuitry may be used, with or without modification, in many other applications as well.

FIG. 2 is an alternate embodiment of a self-sorting output stack and associated circuitry. The FIG. 2 embodiment is generally identical to the FIG. 1 output circuitry, but differs in detail therefrom.

With reference now to the drawing, it may be seen that the various blocks depicted therein are interconnected by lines, both narrow and heavy. The heavy lines indicate a plurality of electrical lead wires each of which may transmit binary electrical data. Unless otherwise indicated, the heavy lines may be regarded as comprising 16 separate electrical lead wires or lines. The narrow lines interconnecting the blocks in the drawing may be regarded as single electrical signal transmission lines.

In FIG. 1, there is shown a memory/address bus 10 that may be regarded as being connected to a central processing unit and its associated memories and master clock (not shown). The central processing unit typically includes a real time information transmission system, circuitry for the calculation and processing of the real time information received on the memory/address bus from input circuitry, and circuitry for use in performing any required calculations with the assistance of program information in the memory and any data that may be stored or placed therein as well. In addition to the binary input data obtained from the circuitry illustrated in FIG. 1, the digital computer may receive other input information used in performing calculations or control functions.

As a partial example of computer function in engine control, it may be assumed that the binary input data received by the central processing unit contains input information concerning current air/fuel ratio of a mixture being supplied to an internal combustion engine as well as the amount of air flow into the engine. This information may be placed on the memory/address bus 10 and may be used by the computer central processing unit (not shown) in the calculation of the duration of the fuel injection pulses that are to be used in controlling intermittently operated electromagnetic fuel injectors that supply fuel to the engine. The pulse width or duration represents the amount of open time for the injectors. The central processing unit would produce an output pulse for example, a change of a binary signal from a logic zero level to a logic one level, at the time a fuel injection from an injector is to begin and would produce a change from the logic one level to a logic zero level when the fuel injection is to terminate and the injector be shut off. Other engine functions, such as ignition timing and exhaust gas recirculation, also may be controlled by the computer and its program. The program in the central processing unit and memory that controls the processing of input data itself may be controlled by a master clock (not shown) have a frequency of, for example, 5 MHz. The performance of instructions by the computer may require at least one and perhaps several pulses of the master clock for execution, depending upon instruction complexity.

The input/output circuitry illlustration in the drawing includes an input/output real time counter 11 having an input of secondary clock pulses that have a repetition frequency less than that of the master clock pulses. A divider circuit supplied with master clock pulses can be used to provide the reduced-frequency secondary pulses applied to the real time counter 11. If a 5 MHz master clock frequency is used, the secondary clock pulses may have a frequency of, for example, 5/12 MHz. In other words, the counter 11 receives one pulse at its input for every 12 pulses of the master clock associated with the central processing unit of the digital computer in the example given herein. The 16 bit count stored in the input/output real time counter 11 appears on each of its output lines 12, 15, and 80. The count on line 12 is supplied via line 13 to the memory/address bus 10 for use by other digital computer components as required. Also, the count on line 12 is applied via line 14 to the output stack controller 60. The count on line 15 is applied to a switch 24 and the count on line 80 is supplied to a number comparator 77.

The previously-described binary input data is available on line 16, which may comprise eight lines, although more or less may be used as required. The binary input data information bits on the eight lines 16 are applied to input latches 17. Except in connection with the generation of an interrupt, the binary input data in the input latches 17 is supplied on lines 22, eight in number, to an input holding register 20 having eight output lines 26 connected to a gate 30.

A single line 23 from the input latches 17 is connected to the switch 24. The switch 24 is gated by any input transition, that is, it is actuated by any change from one state to another of any of the bits of binary input data applied via lines 16 to the input latches 17. When such a transition occurs, the binary input data in the input latches 17 is transferred on lines 22 to the input holding register 20 and the count in the input/output real time counter 11 is transferred through the switch 24 and its associated lines 15 and 25 to a capture-time holding register 21. The capture-time holding register 21 thereby contains within it a count corresponding to the real time at which a transition took place in one of the bits of binary input data applied on lines 16 to the input latches, and the input holding register contains the entire eight bits of binary input data contained on lines 16 as of the occurrence of such transition. In other words, a byte of binary input data is placed in the input holding register whenever a transition occurs on one of the lines 16 from which such byte is obtained, and the capture-time holding register 21 stores the time of occurrence of the transition.

If the transition occurs in an input line that has been given interrupt capability, then the binary input data in the input latches 17 is supplied immediately to the memory/address bus 10 upon the next request for input data from the computer central processing unit. This occurs when lines 38 transitions that are detected by interrupt logic 37. When a data transition with associated interrupt capability occurs, a signal appears on line 39 and is applied to gates 30 and 31. Gate 30 has input lines 26 from the input holding register and gate 31 has input lines 27 from the capture-time holding register that allow transfer to the address decoding logic 50 via lines 40 and lines 41. The interrupt logic 37 also provides a signal, via a line not shown in the drawing, to the central processing unit so that a "service routine" or special program can be used to process the new input immediately.

In the absence of an interrupt condition, gate 30 is in a condition to allow transfer of the binary input data in the input holding register 20, via lines 32, to the pending-input-data side 35 of a first in/first out (FIFO) input stack 34. The FIFO input stack 34 also has an input-time side 36 which, from gate 31 and lines 33, receives the contents of the capture-time holding register, which contents are representative of the time at which a transition occurred in one of the bits of the binary input data stored in the pending-input-data side 35 of the stack.

As illustrated in FIG. 1, the FIFO stack 34 has six pending-input-data slots 35 and a corresponding six input-time slots 36. The pending input data and times in the upper slot are the last information placed in the stack, and the pending input data and input times stored at the bottom of the stack are the first placed therein. The pending input data is removed on lines 43 from the bottom of the stack and the associated input times are removed on lines 44 from the bottom of the stack. This information is applied to lines 42 connected to address decoding logic 50. The address decoding logic 50 interfaces with the memory/address bus 10 in relation to bus acquisition of input data and data transition times. Upon the placement by the computer central processing unit of the input circuitry address on the memory/address bus 10, the address decoding logic allows the data on lines 42 at the time to be placed on the memory address bus. An input stack controller 45 causes the pending input data in the bottom slot (1) of the side 35 of the FIFO stack to appear on lines 42 one pulse or state of a pulse from the master clock. On the next state or occurrence of a master clock pulse, the input stack controller 45 causes the input time from the bottom slot (1) of the input-time side 36 of the FIFO stack to appear on lines 42.

The input stack controller 45 causes the information entering the FIFO stack 34 to progress from top to bottom as it progressively enters via lines 32 and 33 and exits via lines 43 and 44. Leads 47 connected to the various slots provide signals used to set the empty/full (E/F) flags 46 for each of the slots. As pending input data and input time information is used or removed from the slots via lines 43 and 44, the flags 46 are set to so indicate. FIFO input stacks and input stack controllers are, of course, well known in the art. In the operation of the digital computer input processing thus far described, it is clear that simultaneous transitions of the binary input data on more than one of the lines 16 may occur without loss of any of the transition data. The binary input data on lines 16 is supplied as a byte of binary input data to the input holding register and then is transferred to the pending-input-data side 35 of the FIFO stack 36. A subsequent transition on one or more of the binary data input lines 16 causes the sequence of events previously mentioned to be repeated and adds another byte of binary input data to the pending-input-data side 35 of the FIFO stack. The respective times at which the transitions occurred in the bytes in the pending-input-data side of the stack are contained in the portion 36 of the stack. Both the pending input data and the associated input time are removed substantially simultaneously from the bottom slot of the stack on a first-in, first-out basis. The number of bytes of information in the data and time portions 35 and 36 of the FIFO stack at any one time depends upon the rate at which transitions occur in the binary input data and upon the rate at which data and associated time bytes are removed by the digital computer from the bottom of the stack. Preferably, a sufficient number of slots are provided in the stack so that no binary input data transitions are lost as a result of stack overflow.

With respect to the manner in which the output data from the computer is handled, reference is now made to the address decoding logic 52 interconnecting the memory/address bus 10 with the lines 53 associated with a self-sorting output stack 54. In basic function, the output circuitry receives binary output data from a digital computer central processing unit. The output data is supplied to a self-sorting stack in the output circuitry. Prior to its being put out to external circuitry or devices, the binary output data, stored as bytes within the stack, is time-ordered with the aid of a stack controller and other circuitry. This allows the digital computer to provide output data to the self-sorting stack without its central processing unit being required to implement the actual transmission of such data to external devices or circuitry. In other words, binary input data stored as pending output data bytes in a self-sorting stack are time-ordered by the self-sorting stack in accordance with output times assigned to the bytes of data by the digital computer central processing unit.

The self-sorting output stack 54 has a pending output data portion 55 containing six slots and a desired output time portion 56 containing a corresponding six slots. For each pending output data item in the portion 55, there is a corresponding desired output time for such output data contained in the portion 56 of the stack. Each slot has an E/F flag 57 associated with it which is used to set and control the time-ordering of information stored or removed from the stack 54. The output stack controller 60, which receives a five MHz master clock signal on line 61, continually goes through the stack to time-order the removal and utilization of the bytes of pending output data.

In the preferred form of the self-sorting output stack and related circuity, the output stack controller 60 continually goes through the six slots of desired output times making successive comparisons of desired ouput times in two selected, and preferably adjacent, slots in the stack. The desired output times are binary numbers that subsequently will appear in the input/output real time counter 11. Upon each comparison of desired output times, the pending output data and desired output time closest to the real time are moved or switched to the compared-slot that is closer to the stack location from which pending output data is removed. If it is assumed that pending output data is always used or removed from the bottom slot of the self-sorting output stack and that pending output data and associated desired output times move progressively from the upper slots toward the lower slots in the stack as output data is used or removed, then time ordering of the pending output data in the stack 54 may be accomplished by the output stack controller 60 and associated circuitry between changes in the count in the input/output real time counter 11.

There are twelve pulses from the master clock applied to the output stack controller for every change in count in the real time counter. Also, a maximum of twelve comparisons are required to interchange data in the various slots of the stack 54 for the purpose of completely timeordering the desired output times and pending output data. Alternatively, the master clock pulses that occur between changes in count of the real time counter may be used with circuitry able to determine which of the pending output data bytes in the self-sorting stack has the earliest desired output time.

In the preferred time-sorting method, the output stack controller 60, having pulses from the master clock supplied on line 61, makes successive comparisons via lines 62, of the desired output times in selected adjacent pairs of slots in the output stack 54. For example, on a first master clock pulse a comparison would be made of the desired output time (6) with the desired output time (5). If the desired output time (6) is earlier than the desired output time (5) then the associated pending output data bytes of slots (6) and (5) are interchanged along with their desired output times. The output stack controller then causes a comparison to be made between the desired output time in slot (5) with that which is in slot (4) makes an interchange if necessary. Comparisons then are made with the desired output times in slots (4) and (3), slots (3) and (2), and slots (2) and (1) with pending-output-data and desired-output-time interchanges being made with each comparison as required to place the pending output data having the earliest desired output time in the slot (1) bottom location of the stack. A second pass through the stack assures that all of the pending output data is time sorted according to desired output time.

To make a comparison of the desired output times in adjacent slots in the portion 56 of the stack 54, the output stack controller 60, via leads 62, accesses the desired output times in the adjacent slots and subtracts from them the count in the real time counter, which is supplied to the output stack controller via lines 14. The difference between the desired output time in the upper slot involved in the comparison and the count in the real time counter is placed in a register 65, whereas the difference between the desired output time in the lower slot involved in the comparison and the real time count is placed in a register 67. The difference binary number temporarily placed in register 65 is received from the output stack controller 60 via lines 63, and the difference binary number in register 67 is received via lines 64. Lines 63 and 74, respectively, may also be used to set E/F flags 66 and 68 as the difference numbers are placed in the resistors 65 and 67 and used by a number comparator 72. The binary numbers in the registers 65 and 67 are applied, respectively and via lines 70 and 71, to the number comparator 72 which products a difference on lines 73 that indicates which of the desired output times in the compared slots of the stack was earlier in real time. If as a result of the comparison, a slot closer to the top of the stack was found to contain a desired output time earlier than that in the adjacent but lower slot in the stack, the desired output times and pending output data bytes associated therewith are interchanged for the reason previously described.

The desired output time in the bottom slot of the portion 56 of the self-sorting stack 54 is applied via lines 74 to a compare-time holding register 75. Upon the occurrence of a change in the count in the input/output real time counter 11, the binary number in this counter 11 is applied via lines 80 to a 16-bit number comparator 77. At this time a comparison is made with the desired output time on lines 76, the output of the compare-time holding register 75. The comparator 77 determines if there is correspondence between the real time count in the counter 11 and the desired output time on lines 76. If such correspondence exists, then a signal appears on line 81 and is applied to exclusive-OR gates 82. The exclusive-OR gates 82 compare each of the bits in the pending output data byte in the bottom slot of the portion 55 of the self-sorting stack 54 with each of the corresponding bits in the output data holding register 85. The current output data holding register 85 has within it those binary data output bits which represent what is being then outputted by the output latch 87 on its lines 88. The exclusive-OR gates 82, on a bit-by-bit basis, will change any of the bits in the binary data byte stored in the output data holding register 85 if these are different than that which is held in the pending output data slot at the bottom of the stack 54. Otherwise stated, exclusive-OR gates are used to change those bits held in the current-output-data-holding register to bits corresponding to those pending in slot (1) of the self-sorting output stack 54. The change occurs at the time the comparator 77 indicates that the pending output data byte in slot (1) of the stack 54 has a desired output time equal or corresponding to the real time represented by the binary number count in the real time counter 11.

With reference now to FIG. 2, there is shown an alterative form for the output circuity illustrated in FIG. 1. In FIG. 2, some numerals are identical to those identifying elements of FIG. 1. Other numerals in FIG. 2 differ from those in FIG. 1 by the amount of 100. For example, in FIG. 2 the pending output data portions 155a and 155b of the self-sorting output stack 154 correspond to the pending output data portion 55 of the self-sorting stack 54 in FIG. 1.

In FIG. 2, the input/output real time counter 11 is connected by lines 13 to the memory/address bus 10 and by lines 180 to a 16-bit number comparator 177. Address decoding logic 152 allows output data and desired output times from the memory/address bus to be transferred over lines 153 to the self-sorting output stack 154. The desired output times are applied on lines 159 to the desired-output-time portion 156 of the stack which in the illustration contains five slots. The corresponding pending output data is applied on lines 158a and 158b to the respectively corresponding five slots in the portions 155a and 155b of the stack. Each slot of the portion 155a of the stack contains a bit of pending output data (P.O.D) that is either a logic zero or a logic one respectively corresponding to whether a controlled device is to be turned on or off or the like. Each of the slots in the portion 155b of the stack contains four bits of data that designate a particular output line that is to be set in accordance with the pending output data bit held in the corresponding slot of the portion 155a of the stack. In other words, the portion 155a contains data in each of its slots regarding the on or off state of an output-controlled device, and the portion 155b of the stack contains data regarding which output line is to be set in accordance with the state establishd in the portion 155a. With four bits of binary data in the slots of the portion 155b of the stack sixteen different output lines can be controlled.

The output stack controller 160 on lines 161 receives 5 MHz pulses from the master clock. Through the use of lines 162 and the master clock pulses, the controller 16 scans the desired output times in the portion 156 of the self-sorting output stack. Each output time is transferred on lines 174 to a compare-time/output-data holding register 100. This process is completed once for each count of the real time counter 11. Register 100 in essence is a part of the self-sorting output stack. In location 185a it contains the pending output data bit next to be put out by the computer. Location 185b holds the four-bit code that determines which of the sixteen computer output lines is to be controlled in accordance with the on/off state designated by the P.O.D. bit in location 185a of the register. The desired output time is retained in location 175 of the register 100.

For data from each slot in the output stack in turn, the desired output time in location 175 of the register 100 is supplied on lines 176 to the 16-bit number comparator 177. When the real time represented by the count in the counter 11 corresponds with the desired output time on lines 176, the number comparator 177 products a signal on its output line 181a which causes the corresponding empty/full bit (E/F) 157 in the output stack 154 to be adjusted by the output stack controller in order to empty the appropriate slot. In addition, the number comparator 177 produces a signal on its output line 181b that is applied to an output line number decoder 182a. The output-line number-decoder decodes the four-bit designation held in location 185b of the register 100 and places an appropriate logic level on one of its sixteen output lines 183b coupled to latches 182b. Which of the bits in 182b is set is determined by the set output line of the decoder 182a. In other words, one of the 16 bits in 182b is set to a logic zero or logic one level in accordance with the pending output data bit at location 185a and in accordance with the four-bit designation in the pending output data location 185b upon the occurrence of correspondence between the real time as indicated by the count in the counter 11 and the desired output time held in the portion 175 of the register 100. This process is completed for each output whose desired output time corresponds with the time on the real time counter 11. When the real time counter 11 is incremented, the results of these comparisons are allowed to pass along the lines 184 through the gates 187 to the output lines 188.

The embodiment illustrated in FIG. 2 is somewhat advantageous with respect to the embodiment of FIG. 1 in that less circuitry may be required for its implementation. However, it may in some applications represent an undesirable compromise with respect to the FIG. 1 embodiment. In the FIG. 1 embodiment, the time ordering of the pending output data occurs in the stack itself; in the FIG. 2 embodiment, the stack is repetitively searched for the pending output data byte having an output time equal to the real time represented by the count in the counter 11 and pending output data and its desired output time is each repetitively placed in the holding register. Both implementations, however, represent the utilization of a self-sorting output stack that receives bytes of output data, as they are generated by the central processing unit, together with associated desired output times assigned to the data bytes. An output stack controller is permitted to handle the actual removal and outputting of the pending output data independently of the central processing unit of the digital computer.