Semiconductor Integrated Circuit for a Timepiece

This invention is directed to a semiconductor temperature compensation circuit for use in an electronic timepiece and, in particular, to a semiconductor temperature compensation circuit comprised of semiconductor elements that are each integrated into the same monolithic substrate and produce a temperature compensation signal that can be utilized to effect adjustment of the timing rate of an electronic timepiece.

Electronic timepieces and, in particular, small-sized electronic wristwatches utilize a high frequency time standard to establish a very accurate timing rate. One commonly utilized time standard is flexural mode tuning fork quartz crystal vibrators having a resonant frequency on the order of 32.768 KHz. It is noted, however, that one disadvantage of quartz crystal vibrators is that the temperature characteristics thereof vary in response to temperature changes and aging.

Heretofore, these changes in frequency as a result of temperature, aging and the like have been compensated for in different ways. For example, one approach is to utilize a capacitor having a temperature compensation characteristic in the oscillator circuit utilized in combination with the quartz crystal vibrator. Another approach is to utilize two quartz crystal vibrators vibrating at distinct frequencies in order to compensate for changes in temperature. These approaches have not yielded sufficiently high accuracy due to the stability of the vibrator, the considerable expense in achieving such temperature compensation and in the large number of components required to achieve such temperature compensation. Accordingly, a temperature compensation circuit for use in an electronic wristwatch that avoids the above noted disadvantages is desired.

Generally speaking, in accordance with the instant invention, a semiconductor temperature compensation circuit for use in an electronic timepiece is provided. The temperature compensation circuit includes a temperature detection circuit having a first subcircuit comprised of a plurality of MOS transistors and a second subcircuit identical to said first subcircuit, each of said subcircuits having the threshold voltage of the same like polarity transistor shifted with respect to each other. One of the respective like polarity transistors in each circuit have a shifted threshold voltage further having a distinct conductance coefficient with respect to each other, in order to produce a temperature detection signal representative of changes in temperature. A temperature signal converter circuit also includes MOS transistors and, in response to the temperature detection signal applied thereto, is adapted to produce a temperature compensation signal that is to be processed in a processing unit comprised of MOS transistors and adjusted therein by a predetermined coefficient and applied to an electronic timepiece to vary the timing rate thereof. The temperature signal converter circuit is formed of MOS elements that are integrated onto the same monolithic substrate as each of the MOS transistors in the first and second subcircuits of said temperature detector circuit and the processing unit.

Accordingly, it is an object of the instant invention to provide an improved semiconductor temperature compensation circuit for use in an electronic timepiece.

A further object of the instant invention is to provide a semiconductor temperature compensation circuit that is comprised of semiconductor elements including MOS transistors that can be monolithically integrated into the same substrate as the semiconductor circuit elements comprising the timepiece circuitry.

Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.

The invention accordingly comprises the features of construction, combination of elements, and arrangement of parts which will be exemplified in the construction hereinafter set forth, and the scope of the invention will be indicated in the claims.

For a fuller understanding of the invention, reference is had to the following description taken in connection with the accompanying drawings, in which:

FIG. 1 is a block circuit diagram of an electronic timepiece circuit including a semiconductor temperature compensation circuit constructed in accordance with the instant invention;

FIG. 2 is a graphical illustration of the temperature-frequency characteristic and temperature compensation characteristic of a flexural mode quartz crystal vibrator;

FIG. 3 is a circuit diagram of a semiconductor temperature compensation circuit constructed in accordance with the preferred embodiment of the instant invention;

FIG. 4 is a graphical illustration of the temperature compensation signal produced by the semiconductor compensation circuit depicted in FIG. 3;

FIG. 5 is a wave diagram illustrating the manner in which the timing rate adjustment of an electronic timepiece is affected by the semiconductor temperature compensation circuit depicted in FIG. 3; and

FIG. 6 is a graphical illustration of the compensation flexural mode frequency-temperature characteristic of a quartz crystal vibrator in an electronic wristwatch including the semiconductor temperature compensation circuit of the instant invention.

Reference is first made to FIG. 1, wherein a block circuit diagram of an electronic timepiece, having incorporated therein a semiconductor temperature compensation circuit constructed in accordance with the instant invention, is depicted. The electronic timepiece includes a quartz crystal vibrator X coupled to a C-MOS oscillator circuit 1 in order to produce a high frequency time standard signal on the order of 2.sup.16 Hz. A variable tuning capacitor C.sub.T is coupled to the quartz crystal vibrator X in oscillator circuit 1 in order to effect a fine tuning of the high frequency time standard signal produced by the oscillator circuit 1. A divider circuit 2 comprised of a plurality of series-connected binary divider stages is coupled to the oscillator circuit in order to receive the high frequency time standard signal produced thereby and produce a low frequency timing signal. The low frequency timing signal is applied to a plurality of series-connected timekeeping counters, which counters are adapted to produce low frequency timekeeping signals 11 representative of hours, minutes, seconds and the like. The low frequency timekeeping signals 11 are, thereafter, applied to a conventional digital display 13 comprised of decoders, drivers and seven-segment digital display digits that effect the display of the timekeeping information in response to the timekeeping signals applied thereto.

Additionally, the low frequency timing signals produced by the divider 2 are applied to a processing unit incorporated into the electronic timepiece, which unit is adapted to effect timing rate adjustment of either the division ratio of the divider circuit or, alternatively, the frequency of the high frequency time standard signal produced by the oscillator circuit in response to a temperature compensation signal produced by temperature compensation circuit 4. The processing unit is conventional and includes a central processing unit 3 (CPU) having control logic that includes a programmable logic array for generating address data and control data to effect programming of the processing unit, an arithmetic logic unit 5 (ALU), a random access memory 6 (RAM), a temporary register 7 for effecting operations, a read only memory 8 (ROM) for providing a constant, and a programmable read only memory 9 (PROM), which programmable unit effects transfer of information along buses 14 and 15 in a conventional manner. Coupled to the buses 14 and 15 is the semiconductor temperature compensation circuit for transferring to the programmable unit a temperature compensation signal so that same may be processed by the processing unit a manner to be discussed in greater detail below. The manner in which the respective elements of the processing unit effect information transfer, storage, processing and retrieval are well known in the art, are without the scope of the invention defined herein, and, hence, a detailed description thereof is not necessary for an essential understanding of the instant invention.

As illustrated in FIG. 2, the temperature-frequency characteristic of a flexural mode quartz crystal vibrator is illustrated by the curve A. Curve B, defined by dashed lines, illustrates the compensation or correction curve for a quartz crystal vibrator having this characteristic and, accordingly, the instant invention is particularly characterized by the semiconductor temperature compensation circuit, depicted in FIG. 3, for generating a temperature compensation signal that can be readily adjusted by the processing unit to correspond to the curve B, illustrated in FIG. 2.

Reference is now made to FIG. 3, wherein the temperature compensation circuit 4 for use in the timepiece illustrated in FIG. 1, is depicted in detail. A temperature detection circuit is defined by two MOS transistor subcircuits: The first subcircuit including MOS transistors 30 through 33 and the second subcircuit including MOS transistors 34 through 37. Specifically, a P-channel transistor 31, in the first subcircuit, and P-channel transistor 35, in the second subcircuit, are adapted to have a sample pulse .phi..sub.S applied to the gate electrode thereof. Moreover, both P-channel transistors 31 and 35 of the first and second subcircuits are respectively formed in a C-MOS pair with N-channel transistors 32 and 36, with the respective drain electrodes of both P-channel transistors being commonly coupled with the drain terminal and, additionally, the gate terminal of the N-channel transistors in the C-MOS pair. A second C-MOS pair, in each subcircuit, is respectively defined by P-channel transistors 30 and 34 and N-channel transistors 33 and 37 with the N-channel transistors having their gate electrode coupled to the common drain of the other C-MOS pair of transistors in the subcircuit. P-channel transistors 30 and 34 are illustrated in FIG. 3 of the drawings as having their threshold voltage shifted by ion implantation channel doping and this shift in threshold voltage is illustrated by a dashed line between the gate electrode and the connection of the source and drain electrodes.

The respective outputs V.sub.S1 and V.sub.S2 respectively produced by the first and second subcircuits are representative of the differences in the threshold voltage shifts of the P-channel transistors 30 and 34, since the remaining elements in the respective subcircuits are coupled together in the same manner and, hence, have the same characteristics. It is noted, however, that if the conductance coefficient .beta. of the P-channel transistors 30 and 31 are identical to the conductance coefficients of P-channel transistors 34 and 35, the respective output voltage V.sub.S1 and V.sub.S2 of both subcircuits will not vary as a result of variations in the supply voltage or temperature.

In order to avoid this result, and obtain a temperature compensation characteristic, the instant invention is directed to providing the pair of P-channel transistors 30 and 31 of the first subcircuit with a conductance coefficient that is distinct from the conductance coefficient of the P-channel transistors 34 and 35 of the second subcircuit. Specifically, in the exemplary semiconductor temperature compensation circuit, depicted in FIG. 3, the output V.sub.S1 of the first subcircuit varies in response to changes in temperature although not considerably, whereas the output voltage V.sub.S2 of the second subcircuit has substantially no variation (temperature coefficient of 0). Thus, by providing the like polarity and like positioned MOS transistors 30 and 34 in the first and second subcircuit with distinct conductance coefficients, the threshold values of the MOS transistors and the respective conductance coefficients thereof obtain a temperature dependent characteristic based on the mobilities of the respective transistors in the first and second subcircuits.

The output voltage V.sub.S1 is applied to a temperature signal converter circuit that includes resistors 38 and 39 forming a voltage divider circuit for applying a divided voltage signal V'.sub.S1 to the positive input of a comparator 57. The output V.sub.S2 of the second subcircuit is applied through a voltage divider network comprised of series-connected resistors 40 through 46 and MOS switching transistors 49 through 56 to the negative input of comparator 57 as a voltage signal V'.sub.S2.

It is noted that the operation of the temperature detection circuit and the temperature converting circuit is controlled by the application of the sample pulses .phi..sub.S thereto. The sample pulse .phi..sub.S is applied once every ten seconds or once each minute and has a pulse width (sampling time) on the order of 1 to 10 m-sec. By applying .phi..sub.S to the P-channel transistors or the complement thereof .phi..sub.S to the N-channel transistors, the LOW binary level sample pulses .phi..sub.S effect a coincident operation of each of the circuits for a small interval of time sufficient to produce a temperature compensation signal in a manner to be discussed in greater detail below.

Specifically, by applying the sample pulse .phi..sub.S to the temperature detecting circuit and to the temperature converting circuit, the comparator 57 continues to compare the voltage divided output V.sub.S1 and V.sub.S2 produced by the temperature detecting subcircuits and causes a gating signal to be applied through a set-reset circuit defined by NAND gates 58 and 59 to a NAND control gate 60. When the value of V'.sub.S1 and V'.sub.S2 are the same, the set-reset flip-flop is reset, thereby applying a LOW level input to control NAND gate 60 to thereby prevent the clock signal CL from being applied therethrough to register 61. The binary value read into the register is then applied to the decoder which squares the data and decodes it without having to perform any further logic operation, the decoded value produced thereby being directly usable as a division ratio adjustment signal of the type illustrated as 20 in FIG. 1.

It is noted that the register 61 operates in combination with MOS transistors 49 through 56 in order to provide an analog-to-digital type conversion. Specifically, the analog-to-digital converson is effected in the following manner. First, MOS transistor 56 is turned ON by the signal .phi..sub.0 produced by register 61 and each of the MOS transistors, 49 through 55, are turned OFF by the signal .phi..sub.1 through .phi..sub.7 produced by register 61. Accordingly, at the time that sample signals .phi..sub.S and .phi..sub.S are applied to the temperature detecting circuit and the temperature signal converting circuit, the signal V'.sub.S1 is applied to comparator 57 and is compared therein with the signal V'.sub.S2, which signal equals the output V.sub.S2 of the second temperature detecting subcircuit divided by resistors 40 through 46. In response to detecting a difference in the voltage levels of V'.sub.S1 and V'.sub.S2, applied to the comparator 57, a HIGH level signal is applied to the set-reset flip-flop thereby permitting a clock pulse to be applied through NAND gate 60 to thereby index register 61 to apply a signal .phi..sub.1 to gating MOS transistor 55 and prevent outputs .phi..sub.0 and .phi..sub.2 through .phi..sub.7 of register 61 from turning on gating transistors 49 through 54 and 56 of the analog-to-digital divider network. By turning ON switching transistor 55 and turning OFF switching transistor 56, the output voltage V.sub.S2 is now divided between resistor 46 and resistors 44 through 45, thereby changing the value of V'.sub.S2 that is compared with V'.sub.S1 by the comparator during the next interval that sampling pulse is applied thereto. As aforenoted, this operation continues until the voltage level of both inputs to the comparator 57 are equal, whereupon the set-reset flip-flop prevents any more clock pulses from being applied to the register 61, hence establishing a temperature compensation value. It is this value which is then applied to the decoder circuit and decoded into a binary coded temperature compensation signal that can be applied to the processing unit for adjusting by a predetermined coefficient stored therein to effect adjustment of the timing rate thereof of the timekeeping circuitry.

It is noted that the analog-to-digital conversion effected by the temperature signal converting circuit, illustrated in FIG. 3, is limited to a distinct detection level. However, it is apparent that the number of detection levels can be increased by increasing the number of switching transistors and series-connected dividers as is deemed necessary. Thus, in light of the operation, discussed above, it is apparent that the instant invention is characterized by the use of the temperature coefficient and mobility characteristic not only in the surface of the MOS transistors but also throughout the bulk thereof.

In the case where the variation in the temperature characteristic of the quartz crystal vibrator is not significant, or where the timing rate is not negatively effected thereby, the temperature coefficient of the quartz crystal vibrator can be written into the ROM 8 as a binary signal utilizing a conventional mask. If a more exacting adjustment is also required, an optimum write-in value WP can be written through the writing control circuit 10 to the PROM 9 in order to cancel out the variations in the temperature coefficient of the quartz crystal vibrator. It is further noted that if FAMOS elements (floating gate avalanche injection MOS) are used to synthesize the PROM, an operating voltage on the order of 20 to 50 V is required. Accordingly, any non-volatile memory elements, such as fusible type memories, diodes, insulation breakdown type memory elements wherein the insulation breakdown occurs on an insulating film, etc., can also be utilized to synthesize the PROM. Other non-volatile devices that can be utilized include mechanical switches, wire bonding and/or laser trimming.

Accordingly, if the temperature coefficient of the quartz crystal vibrator is known, and a temperature compensation signal is obtained, the CPU 3, ALU 5, RAM 6 and temporary register 7 can determine a correction value in accordance with a simple formula. For example, assuming the temperature compensation signal to be linear, it can be multiplied by itself and then multiplied once again by an appropriate coefficient in order to obtain the curve C, illustrated in FIG. 4. Thereafter, a correction signal 20, corresponding to the curve C. would be applied to the divider 2 as a division ratio adjustment signal. As is illustrated in FIG. 5, by applying a frequency adjustment signal to the divider circuit 2, a single pulse, as illustrated by wave train b in FIG. 5, or the two pulses, as illustrated by wave c in FIG. 5, is added to the timing rate of the divider circuit to effect an increase in the timing rate of the timekeeping circuitry of the timepiece. Moreover, since the logic compensation of the absolute timing rate (the compensation of the timing rate is performed by adjusting the division rate of the divider circuit and not by adjusting the tuning capacitor C.sub.T in the oscillator circuit) is performed by the same circuitry utilized to effect temperature compensation adjustment of the timing rate, the number of circuit elements required to effect temperature compensation is reduced. It is also noted that temperature compensation can be performed by applying an adjustment signal to the oscillator circuit to vary the tuning capacitance thereof. Accordingly, in an electronic timepiece, of the type illustrated in FIG. 1, all the functions of the timekeeping circuitry, including the oscillator, divider, etc., are controlled by the ALU and CPU so that only the temperature detecting circuit must be separately provided, the remaining components, such as the RAM, ROM, CPU being used in common with the remaining control circuitry. Thus, a timepiece having the temperature compensation circuit of the instant invention is less expensive to manufacture and can be further miniaturized as a result of the simplicity thereof.

Referring to FIG. 6, the curve D therein illustrates the actual temperature-frequency characteristics of the timing rate of an electronic timekeeping circuit that is compensated by the temperature compensation circuit depicted in FIG. 3. Although the temperature-frequency characteristic is rippled, the accuracy thereof is greatly increased when compared with the curve A, illustrated in FIG. 2, as changes in temperature occur. Since the inside of the timepiece is maintained at a constant temperature and the temperature difference is negligible and, hence, can be ignored, no problems occur in the quartz crystal vibrator and IC.

Accordingly, the instant invention is characterized by the use of the same semiconductor elements that are monolothically integrated into a substrate in conventional electronic timepieces to synthesize the temperature compensation circuit and function as temperature detection elements in accordance with the teachings of the instant invention. This results in miniaturization, reduced costs of manufacture and a highly accurate digital display electronic timepiece. Moreover, utilizing the temperature compensation circuit of the instant invention, a digital display can be utilized to display temperature.

It is noted that if the timepiece is provided with a CPU, the temperature compensation is performed by utilizing the CPU in order to effectively compensate the variations in frequency caused by variations in the timing rate of the quartz crystal vibrator or the timekeeping circuitry that produces the low frequency timekeeping signals. It is noted, however, that the temperature compensation can be effected by utilizing the circuit depicted in FIG. 3 without the necessity of many of the programming circuits in the processing unit, thereby further facilitating the design of an electronic timepiece incorporating the semiconductor temperature compensation circuit of the instant invention.

It will thus be seen that the objects set forth above, among those made apparent from the preceding description, are efficiently attained and, since certain changes may be made in the above construction without departing from the spirit and scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.