Pulse-Forming Circuit for on/Off Conversion of an Image Analysis Signal

The present invention relates to a pulse-forming circuit for on/off conversion of an image analysis signal with reference to a variable comparison threshold signal established by the pulse-forming circuit. The pulse-forming circuit is intended, in particular, to be used for on/off conversion of facsimile signals derived from document analysis in facsimile signal transmission installations.

A document analysis signal is a signal which is modulated in amplitude between two limit levels: a maximum black level and and a maximum white level corresponding respectively to black elements and to white elements in the document being analyzed. Generally speaking, the white level is higher than the black level in the analysis signal as detected, for example, by a photodiode; however, these relative levels may be inverted by analog pre-processing, e.g. using an inverting amplifier.

On/off conversion of an image analysis signal, i.e. its transformation into a two level signal, requires it to be compared with a reference signal that lies between the two modulation limits. In practice, the reference signal is chosen to have a value close to the maximum white level of the image.

When the document being analyzed has a non-uniform background, and/or information-conveying elements of non-uniform tone, it is no longer satisfactory to compare the analysis signal with a constant reference signal. Indeed, in such a case the analysis signal may be of very variable amplitude, and further the amplitude may also be considerably reduced from the maximum modulation levels when closely spaced black-white alternations are being analyzed. It is thus known to vary the value of the reference signal which constitutes the decision threshold for comparison, as a function of the modulation levels in the said analysis signal.

Preferred embodiments of the present invention provide a circuit which determines a decision threshold that varies as a function of the background tone of an image and also as a function of the successive modulation levels of the image signal.

The present invention provides a pulse-forming circuit for on/off conversion of an image analysis signal representative of successive image points along successive image scan lines, the signal being modulated such that its level varies between two limit levels corresponding to image white and to image black, the pulse-forming circuit converting the image analysis signal to an on/off signal by comparing the said image analysis signal with a decision threshold, and the decision threshold being variable as a function of the level of the image analysis signal, wherein the pulse-forming circuit comprises an image background level detector circuit connected to receive the image analysis signal and to operate over a scan line to detect the level .DELTA. of the image background, an average value detector circuit connected to receive the image analysis signal and to operate over a few successive image points to detect the average value .DELTA.' thereof and a circuit for determining the said variable decision threshold, connected to receive the background level .DELTA. and the average value .DELTA.' from the detector circuits and to provide the said decision threshold at a value V.sub.d which satisfies a function having the form V.sub.d =K.DELTA.+K'.DELTA.', where K and K' are two coefficients which satisfy the following relationships:

An embodiment of the present invention is described by way of example with reference to the accompanying drawings in which:

FIG. 1 is a block diagram of a pulse-forming circuit in accordance with the invention;

FIG. 2 illustrates the operation of the circuit in accordance with the invention; and

FIG. 3 is a circuit diagram of one embodiment of the invention.

FIG. 1 is a block diagram of a pulse-forming circuit for processing an image analysis signal to convert it into an on/off signal by comparing it with a variable decision threshold. The input of the pulse-forming circuit is referenced E and receives the image analysis signal V.sub.a. The signal V.sub.a is representative of successive image points along successive image scan lines, and it is modulated to a level which is variable between two limit levels corresponding to maximum image white and to maximum image black. In this particular analysis signal V.sub.a the white level amplitude is higher than the black level amplitude. The output of the pulse-forming circuit is referenced S and provides a signal V.sub.s which is the signal V.sub.a reproduced in binary form.

The image analysis signal V.sub.a is applied to a comparator circuit 1 which is constituted by an operational amplifier. The comparator circuit 1 also receives the decision threshold V.sub.d and its output constitutes the output S of the pulse-forming circuit

To determine the decision threshold V.sub.d, the pulse-forming circuit includes a circuit 2 which receives the signal V.sub.a and detects modulation peaks therein. This circuit includes a device, e.g. a capacitor, for storing the maximum detected peak value .DELTA.. The pulse-forming circuit also includes a circuit 3 also connected to the input E and for detecting the average value .DELTA.' of the signal V.sub.a over a few successive image analysis points. Finally, the pulse-forming circuit includes a circuit 4 for summing the detected values .DELTA. and .DELTA.' to determine the decision threshold in accordance with the relationship V.sub.d =K.DELTA.+K'.alpha.'. It is this decision threshold V.sub.d which is applied as a reference voltage to the comparator circuit 1.

The values of the coefficients K and K' are chosen as a function of the characteristics of the analysis signal. In one embodiment, described by way of example, K is chosen to equal 1/3 and K' is chosen to equal 1/2, thereby giving the relationship V.sub.d =.DELTA./3 +.DELTA.'/2. The choice of the decision threshold V.sub.d substantially according to this relationship favours the appearance of black points on a white image background at the pulse-forming forming circuit output S. Indeed, if white image points follow one another, the average value .DELTA.' becomes very close to the maximum value .DELTA.; and for .DELTA.'=.DELTA., the decision threshold V.sub.d takes the value V.sub.d =5/6.DELTA. which is thus very close to maximum white level. The choice of decision threshold with the value V.sub.d =.DELTA./3+.DELTA./2' also favours the reading of white points on a black background at the pulse-forming circuit output S. Indeed, if the image analysis signal V.sub.a represents widely separated white points the average detected value .DELTA.' is very close to the black image level; and for .DELTA.'=0, the decision threshold takes the value V.sub.d =.DELTA./3 and has thus been brought to a value which is relatively close to the black level, which in practice makes it possible for the pulse-forming circuit still to detect white points on a black background even though their amplitude in the signal V.sub.a is considerably reduced.

In FIG. 2, the values taken by the decision threshold V.sub.d are shown as a function of a signal V.sub.a. FIG. 2 is divided into three zones a, b and c, in which the signal V.sub.a represents respectively: a low density of black image points on a white background in the zone a; and alternation of black and white image points in the zone b; and a low density of white image points on a black background in the zone c. The signal V.sub.a is shown in all three zones with a large loss of amplitude compared with the limiting levels of maximum image black (zone a), of maximum image white (zone c), or of both maximum image black and maximum image white limiting levels (zone b). This results in both the zones a and c by the fact that the black (or white as the case might be) points are rare in the corresponding image zone whose overall tone is white (or black as the case might be), and in the zone b from the alternation of black and white points in the corresponding image zone. On the y-axis the maximum peak value for the set of all three zones is designated .DELTA. while the average values detected in each of the these zones are designated .DELTA.'a, .DELTA.'b and .DELTA.'c respectively. The decision threshold values for each of these zones V.sub.da, V.sub.db and V.sub.dc are also marked on the y-axis.

In the zone a, .DELTA.' a is substantially equal to .DELTA.; the threshold V.sub.da is close to .DELTA. and has a value substantially equal to 5/6.DELTA..

In the zone b, .DELTA.'b is substantially equal to .DELTA./2, and the value of V.sub.db is substantially equal to 7/12.DELTA..

In the zone c, .DELTA.'c is substantially equal to 0, the value of V.sub.dc is brought down towards the black level and becomes extremely close to .DELTA./3.

FIG. 3 is a circuit diagram of one embodiment of a pulse-forming circuit in accordance with the invention. In FIG. 3, the various blocks of FIG. 1 re-appear with the same reference numerals. It can be seen that the comparator circuit is constituted by an operational amplifier receiving the signal V.sub.a on its+input and the decision threshold V.sub.d on its-input, and providing the signal V.sub.s at its output. The circuit 2 for detecting the maximum peak value of the signal V.sub.a is constituted by a resistor 20 and a capacitor 21 connected to earth. The pulse-forming circuit input E is connected to the resistor 20 (which constitutes a charging resistance for the capacitor 21) via a field effect transistor 22 whose drain and source electrodes are connected to the input E and to the resistor 20. The connection between the capacitor 21 and its charging resistance 20 is connected via the drain and source electrodes of another field effect transistor 23 to convey the signal .DELTA. to a circuit for discharging the capacitor 21 (described below) and to a two transistor (24 and 25) output amplifier circuit. In the amplifier, the transistor 24 is an NPN-type transistor with its base connected to the field effect transistor 23, its collector connected to a positive supply +V and its emitter connected to a negative supply -V via a resistor 26; the transistor 25 is a PNP-type transistor and has its base connected to the emitter of the transistor 24, its emitter which constitutes the output of the amplifier connected to the +V supply via a resistor 27, and its collector connected to the -V supply.

The field effect transistor 22 is switched on by detecting a peak value in the signal V.sub.a which is greater than that stored on the capacitor 21. To this end, a comparator formed by an operational amplifier 50 powered from the +V and -V supplies, has a positive input connected to the input E and its negative input connected to the output of the field effect transistor 23. The output signal of the operational amplifier 50 is applied via a resistor 51 to the gate of the field effect transistor 22. The field effect transistor 22 constitutes the circuit for controlling the charging of the capacitor 21. It behaves like a closed switch when the signal V.sub.a has a value greater than the stored peak value and like an open switch otherwise.

The circuit for discharging the capacitor 21 comprises a high value resistor 55 connected to the output of the field effect transistor 23 and defining, together with the capacitor 21, a long discharge time constant for a slow discharge of the capacitor. The resistor 55 is also connected to a two transistor (56 and 57) circuit controlled from the signal delivered by the operational amplifier 50. The transistor 56 is a PNP-type transistor and has its base connected to a resistor 52 which is connected to the output of the operational amplifier 50 and which is connected in series with a resistor 53 connected to the positive supply +V. The emitter of this transistor is connected to a bias supply +V' at a lower potential than the supply +V, its collector is connected via a resistor 58 to the base of the transistor 57 which is an NPN-type transistor whose emitter is connected to earth and whose collector is connected to the discharge resistor 55.

The field effect transistor 23 is itself controlled by the signal delivered by the operational amplifier 50 and applied to its gate via the resistor 51 and a diode 60 connected to conduct from the resistor 51 to the field effect transistor. A diode 61 is connected between the resistor 51 and earth to conduct from the resistor 51 to earth and is associated with resistors 51 and 53 to control both field effect transistors 22 and 23.

Both field effect transistors 22 and 23 are also controlled by a signal indicative of the image scan being in between two successive scan lines, via a control input C which is connected to the gate of the field effect transistor 23 and to the gate of the field effect transistor 22 via the diode 60. This signal is provided between the end of each scan line and the beginning of the next scan line by the same image analysis circuit which delivers the signal V.sub.a. This signal is constituted by a negative voltage between scan lines and turns off both field effect transistors 22 and 23. During scan lines the signal has a positive value which turns on the field effect transistor 23.

In FIG. 3, the circuit 3 for detecting the average value .DELTA.' of the signal V.sub.a over a period of several analysis points, is constituted by a capacitor 31 associated with a charging resistor 30. The circuit 4 for determining the decision threshold V.sub.d is constituted by a resistor network comprising a resistor 40 connected to the emitter of the transistor 25, a resistor 41 connected to the connection between the resistor 30 and the capacitor 31, and a resistor 42 connected between earth and the resistors 40 and 41. The resistance values of the resistors 40, 41 and 42 are defined relative to each other and putting the value of the resistor 40 as R.sub.1, that of the resistor 41 as R.sub.2, that of the resistor 42 as R.sub.3, and that of the resistor 30 as R.sub.4, the resistance values are related as follows:

In order to obtain a decision threshold V.sub.d such that

which is applied to the comparator circuit 1.

When K=1/3 and K'=1/2 as in the chosen example, these relationships become:

to obtain a decision threshold V.sub.d such that

Further, the processor circuit shown in FIG. 3 is completed by a circuit 7 for limiting the decision threshold V.sub.d. The circuit 7 comprises an operational amplifier 70 which receives the decision threshold V.sub.d at its negative input as provided by the output of the circuit 4, and receives a defined fixed voltage at its positive input determining the minimum value of the decision threshold to be applied to the comparator 1. This fixed voltage is taken from an intermediate point of a resistance 71 connected between the +V' supply and earth. The output of the operational amplifier 70 is connected to the +V' supply via a resistor 72. When the signal V.sub.d is lower than the minimum threshold value, the output of the amplifier 70 is connected to the connection between the resistors 40,41 and 42 via a resistor 74 and a diode 73 which then becomes conductive, thereby maintaining the threshold V.sub.d as applied to the negative input of the operational amplifier of the circuit 4 at least at this minimum value.

In operation, the positive voltage supplied at the output of the operational amplifier 50 when the level of the signal V.sub.a appearing at E is greater than the stored peak value .DELTA., causes the field effect transistor 22 to turn on to charge the capacitor to the appropriate value. Simultaneously, the discharge circuit 55, 56 and 57 is turned off and the field effect transistor 23 is conductive.

The negative voltage is supplied from the output of the operational amplifier 50, when the level of the signal V.sub.a present at E is below the stored value .DELTA., and turns off the field effect transistor 22. Simultaneously the diode 60 isolates the gate of the field effect transistor 23 from the negative voltage at the output of the operational amplifier 50 and is connected to a positive potential by the terminal C. Also simultaneously by virtue of the transistors 56 and 57 being turned on, the resistor 55 is connected to earth and the capacitor 21 discharges slowly.

Between two successive image analysis lines the field effect transistors 23 and 22 are turned off by the terminal being connected to a negative voltage: the capacitor 21 neither charges nor discharges.

This pulse-forming circuit thus makes it possible to vary the decision threshold of the image background as detected on an analysis line and as a function of the density of analysis points to be detected on this background.