Automatic Transmission Digital Control System

Cross reference to related applications, assigned to the assignee of this application:

U.S. Ser. No. 621,513, filed Oct. 10, 1975, Bert Wurst et al;

U.S. Ser. No. 882,138, filed Feb. 28, 1978, Sauer et al.

These are hereby incorporated by reference into the present application.

The present invention relates to automatic transmission systems and in particular to automatic transmission systems having a digital control.

Automatic transmission systems are known in which data regarding the actual speed and load of the engine is continually supplied and in which a gear shift is initiated when the actual load and speed signals are outside of the range assigned to the then-present gear. Further, driver operated gear shifts can be carried out if the speed and load are such that these conditions can be accommodated in the new gear. In particular, the speeds must be below the limiting speed of the gear and the engine must be able to develop sufficient torque. Specifically, the automatic transmissions are generally so designed that the engine will be able to furnish a maximum torque for the then-present speed. It is a disadvantage of known automatic transmission systems that the various measurements and computations cannot be carried out with sufficient sensitivity and that the systems are relatively complicated. Further in systems which operate on a mechanical-hydraulic basis the wear of the various parts will result in changes in the characteristic curves and thus in changes in the operating points at which the gear shift can take place. Repair and maintenance may be very complicated and expensive.

It is an object of the present invention to furnish an automatic transmission control system of high precision with nonetheless requires very little space. The system of the present invention is to utilize a large amount of stored data and data derived from the actual operating conditions of the engine and to process this data very accurately so that the operation of the system corresponds very accurately to the then-present operating conditions.

It is a further object of the present invention to furnish a digital control system which is embodied in a special purpose computer and which may later readily be combined with special purpose computers regulating other operations such as fuel injection, ignition, etc.

The present invention comprises a main storage which stores a plurality of sets of constants each set for reconstructing a characteristic upshift or downshift curve of limiting engiine load vs. engine speed by straight line approximations. Inputs signals to this system include a present speed signal and a present load signal having frequencies corresponding, respectively, to actual engine speed and the actual gas pedal position. A speed counter receives the present speed signal and furnishes a corresponding binary speed number, while a present load counter furnishes a present load number corresponding to the frequency of the present load signal. A signal indicative of the actually engaged gear is also furnished and, in combination with the binary speed number controls addressing means which address the main storage at storage locations storing the constants for the applicable shift curve. Computing means including a limiting load counter compute a limiting load number under control of the constants read out from the main storage. A comparator then compares the present load number to the limiting load number and furnishes a comparator output signal if the limiting load number has a predetermined relationship to the present load number. Finally, output logic means furnish a gear control signal initiating an upshift or a downshift under control of the present gear signal and the comparator output signal.

FIG. 1 is a block diagram of the system of the present invention;

FIG. 2 shows a family of characteristic shift curves for a three gear transmission, with load frequency plotted as a function of speed frequency;

FIG. 3 is a curve of speed number as a function of the period of the present speed signal;

FIG. 4 illustrates linear approximation of a characteristic shift curve;

FIG. 5 is a curve showing desired values of main pressure as a function of engine load;

and FIG. 6 shows the count on the counters of FIG. 1 as a function of time during one operating cycle of the system.

The following description will relate to a preferred embodiment having three forward gears and a reverse gear. Although all the figures and diagrams correspond to this three gear system, the invention is of course not to be limited to such. The preferred embodiment also constitutes a special purpose digital computer which can be incorporated into an over-all control system for the motor vehicle. Input data can be supplied to such a system in digital form. When the actual sensors do not furnish a digital output analog-digital convertors or mechanical-digital convertors can be supplied. The special purpose computer to be described below can readily be embodied in an integrated circuit and can be combined with other special purpose computers, thereby allowing the sharing of particular elements such as storages. Where a shared storage is used, a time multiplexing system can be used for addressing such storages.

The special purpose computer is denoted by reference numeral 1 in FIG. 1. It has six input terminals E1, E2, E3, E4, E5 and E6. The signals at terminal E.sub.1 are desired gear selector signals which correspond to the gear selected by the driver. Input terminal E.sub.2 receives the kickdown signal KD, that is the signal which is driver initiated for obtaining a downshift to increase acceleration. Terminal E.sub.3 receives a no load signal, that is a signal which signifies that the throttle valve is fully closed and that the motor vehicle is coasting. The signal applied to terminal E.sub.4 is a present speed signal, f.sub.G, whose frequency is proportional to engine speed. The signal applied at terminal E.sub.5 is a present load signal which has a frequency corresponding to the actual engine load, i.e. the throttle position or the gas pedal position, while the signal applied at terminal E.sub.6 is a present gear signal, i.e. a signal indicating which gear is engaged. The present speed signal f.sub.G can be derived directly from the sequence of ignition pulses and may be reduced by a factor of 2 by a frequency divider stage U1'. The frequency of signal f.sub.G varies between 110 Hz and 3.5 kHz, while the present load signal has frequencies varying between 25 kHz and 150 kHz. Present load signal f.sub.L can be generated by a suitable transducer stage wherein the position of the throttle valve or of the gas pedal serves as an input and which furnishes the signal f.sub.L (that is signal having a frequency corresponding to the mechanical position of the input element) at its output. Electronic building blocks for producing a signal having a frequency corresponding to a mechanical displacement are well known. Basically, they include an oscillator whose oscillating frequency is varied as a function of the variation of the value of one component e.g. a resistor. The variation of the resistor is a function of the position of the mechanical element relative to a reference position.

Input terminals E.sub.1, E.sub.2 and E.sub.3 are connected to an input logic circuit L1. It is the function of logic circuit L1 to prevent the driver initiated shift or to prevent a kickdown during predetermined operating conditions of the engine as will be discussed below.

Frequencies f.sub.G and f.sub.L are converted to a binary speed number Y.sub.g and a binary present load number Y.sub.L respectively in counters Z.sub.g and Z.sub.L. Further, a limiting load number Y.sub.k is computed from values read out from a main storage S. The values are read out under control of the present engine speed number Y.sub.g. Depending upon the relationship between the limiting load number Y.sub.k and the present load number Y.sub.L as indicated by the output signal of comparator C output logic A.sub.L either furnishes or does not furnish a gear shift control signal initiating an upshift or a downshift operation. It should be noted that a clock generator having an output frequency f.sub.0 =600 kHz is part of special purpose computer 1.

The mode of operation of the present system will first be explained relative to the curves of FIG. 2. In FIG. 2, frequency f.sub.L is plotted as a function of frequency f.sub.G, that is, present load is plotted as a function of present engine speed. Designation 1-2 for one of the characteristic curves means, for example, that whenever the actual operating point of the engine lies below this curve, an upshift from the first to the second gear should occur. Similarly a downshift from the third to the second gear should take place when the operating point of the engine lies above characteristic curve 3-2. Unnecessary shifting back and forth between two gears is eliminated by the relatively broad switching hysteresis. The solid lines in FIG. 2 indicate desired characteristic curves of limiting load vs. engine speed, while the dashed lines indicate the curves actually obtained in a preferred embodiment as will be discussed below.

To clarify the operation, let is be assumed that the engine is operating at operating point P1, that is at a speed f.sub.G1 and a load f.sub.L1. The limiting load for an upshift operation from second to third gear would then be characterized by frequency f.sub.K1 (i.e. corresponding to limiting load number Y.sub.k1). If the presently engaged gear is third gear, the control system will not initiate any gear shift. However, if the frequency f.sub.L increases to operating point P2, that is reaches the value f.sub.L2, then the downshift curve 3-2 has been crossed and the control circuit will initiate a downshift from third to second gear. If, on the contrary, the engine was in second gear when the operating conditions were as specified by operating point P1, then no gear shift would be initiated unless the load dropped to operating point P3, that is to a frequency f.sub.L3. Under these conditions the load is less than the limiting load for upshift and an upshift from second to third gear would be initiated. It should be noted that the absolutely vertical movement from point P1 to point P2 and P3 would not occur in practice since in general some speed change will occur together with the change in load. The perpendicular line segments above a frequency of F.sub.1 =150 kHz are the kickdown speed thresholds.

Referring again to FIG. 1, the present load number Y.sub.L is created in an eight bit counter Z.sub.L. Counter Z.sub.L has a counting input and receives pulses of frequency f.sub.L during a predetermined gating time T.sub.1. Gating time T.sub.1 can be determined by the requirement that counter Z.sub.L will have counted to capacity at the end of the gating time when the highest possible counting frequency f.sub.0 =150 kHz is applied at its input. Therefore T.sub.1 =255/150 kHz=1.7 ms. The gating signal is furnished by stage ZG.sub.0 which is triggered at the start of phase I of each cycle of operation of this system (see FIG. 6) and maintained its output for 1.7 ms. Stage ZG.sub.0 may, for example, be a monostable multivibrator. The gating signal is applied to one input of a NAND gate T.sub.1 whose other input is connected to terminal E.sub.5. The count on counter Z.sub.L at the end of the gating time is then a measure of the present engine load.

The creation of the binary speed number Y.sub.g as a function of the present speed signal having frequency f.sub.G is somewhat more difficult. Frequency f.sub.G is so low that direct counting as described above can not be carried out. Therefore the number of pulses of a frequency f.sub.z are counted which are applied to the counting input of counter Z.sub.G during a half period of the square wave having a frequency f.sub.G. In other words, the gating signal is derived from two sequential passages through zero of signal f.sub.G. During this time a NAND gate T.sub.2 allows counting pulses of frequency f.sub.Z to be applied to the counting input of counter Z.sub.G. If frequency f.sub.Z were a constant frequency, the number generated in counter Z.sub.G would be proportional to the period T.sub.G =1/f.sub.G of the present speed signal. To create the inverse of this number, counter Z.sub.G is first set to a maximum count which, in the preferred embodiment, is the binary number 255. It then counts down with the frequency f.sub.Z which is variable as a function of time or as a function of the then-present count Y.sub.G on counter Z.sub.G. Frequency f.sub.Z is varied in such a manner that the substantially hyperbolic curve of FIG. 3 results. The hyperbolic curve is approximated by four straight line segments. This approximation achieves sufficient accuracy with relatively little difficulty. This lack of difficulty results from the fact that the frequency associated with each straight line segment is an integral subdivision of clock frequency f.sub.0 =600 kHz, and that the break points of the curve occur at integral submultiples of the count on counter Z.sub.G. The curve of FIG. 3 is plotted in accordance with the following table, the values of which are also entered on the curve in FIG. 3:

The characteristic curve of FIG. 3 is a plot of the number Y.sub.G on counter Z.sub.G as a function of the period of the present speed signal f.sub.G. The characteristic curves resulting from this approximation are shown by dashed lines in FIG. 2. The deviation from the desired value is within the required accuracy.

Referring now to FIG. 1, the variable frequency f.sub.Z is generated in block H. Block H contains a plurality of frequency dividers connected in cascade, the first dividing the applied frequency by 2, the second dividing its applied input frequency by 4, and the third dividing by 8. Three AND gates are provided, each having a first input connected to the output of one of the frequency divider stages. A fourth AND gate has a first input directly connected to receive the clock frequency of 600 kHZ. Each of the AND gates has a second input connected to receive a gating signal. The gating signals are derived from the counting outputs of counter Z.sub.G. The fourth AND gate would receive a gating signal while the count on counter Z.sub.G varies between 255 and 128, the gating signal associated with the first voltage divider would be present while the count on counter Y.sub.G varies between 128 and 64, etc. The AND gate outputs are all connected to the inputs of an OR gate whose output is symbolized by the line connecting block H to the input of AND gate T.sub.2. The pulses f.sub.Z are applied to the counting input of counter Z.sub.G in the presence of a signal at the second input of AND gate T.sub.2, that is during a half period of signal f.sub.G.

Blocks Z.sub.i, Z.sub.a, Z.sub.k, Z.sub.p are eight bit counters. Z.sub.i is an interval decoder, Z.sub.a is an address counter, Z.sub.k generates the limiting load number Y.sub.k and counter Z.sub.p generates the reference value for the main pressure.

Main pressure regulation takes place by regulating the current through a solenoid valve MV. This is the number Y.sub.p on counter Z.sub.p. The main pressure reference value is to vary as a function of engine load. Specifically, the non-linear characteristic line of FIG. 5 is to be implemented. The process of creating number Y.sub.p in counter Z.sub.p in dependence on the load number Y.sub.L will be described in greater detail below.

The first phase of the cycle of FIG. 6 is a so-called measuring phase I in which the frequency f.sub.G and f.sub.L are converted into binary numbers Y.sub.G and Y.sub.L respectively. The next phase phase II, is a computing phase in which the limiting load number Y.sub.K is formed. One of the characteristic shift curves is shown schematically in FIG. 4 (without kickdown threshold). Y.sub.L is plotted along the ordinate, Y.sub.G along the abscissa. The characteristic shift curve is approximated by three straight line segments and any point on this line can be computed as a function Y.sub.G by use of six parameters. The parameters are .DELTA.Y.sub.i, n.sub.i where i=0,1,2. The initial value Y.sub.0 is constant. The curve thus consist of intervals (speed ranges) .DELTA.Y.sub.0, .DELTA.Y.sub.1, .DELTA.Y.sub.2 each with an associated slope n.sub.0, n.sub.1, and n.sub.2. In order to create the count of Y.sub.K, a sequence of pulses having a variable repetition rate is applied to the input of counter Z.sub.K during a time proportional to the binary speed number Y.sub.G. The total duration of counting in counter Z.sub.K is determined by counting down the number Y.sub.G in counter Z.sub.G (or in a counter receiving the number Y.sub.G) at a predetermined frequency, for example f.sub.4 =37.5 kHZ. The counting process is started simultaneously with the countdown of number Y.sub.G and terminates when the counted down number is zero. The variable frequency f.sub.K is generated in block E. The frequency in each interval .DELTA.Y.sub.i is proportional to slope n.sub.i. Counter Z.sub.I is used as an interval decoder. At the beginning of phase II a starting value of .DELTA.Y.sub.i is loaded into counter Z.sub.I. This number is counted down with the same frequency as the count down of counter Z.sub.G. When counter Z.sub.I reaches its zero count, a new interval value .DELTA. Y.sub.i+1 is read out of storage S. Simultaneously, the frequency of the output of frequency generator E is changed to the value associated with the next interval. Counter Z.sub.K thus counts upward in each interval with a corresponding frequency as shown in FIG. 6d. When Y.sub.G =0, that is at the end of the count-down of the binary speed number, the number in counter Z.sub.K will be the limiting load number Y.sub.K.

The number Y.sub.K must then be compared to the number Y.sub.L, that is to the present load number, in order to decide whether or not a shift operation may be initiated. A comparison between these two numbers is accomplished as follows. When Y.sub.G has been counted down to zero, a simultaneous count-down of counters Z.sub.L and Z.sub.K is initiated. Both are counted down at the same frequency f.sub.4 during the third phase of the cycle shown in FIG. 6. As soon as counter Z.sub.L has reached the count of zero, a test is carried out as to whether counter Z.sub.K has or has not reached zero also. If counter Z.sub.K has already reached zero, the present load exceeds the limiting load and a "1" signal is created at the 0/1 input of output logic AL. If the present load is less than the limiting load, a "0" signal is created at this terminal.

It should be noted at this point that the system in addition to the components shown in FIG. 1 has further components as discussed throughout the text for achieving null detection, causing the proper loading of the counters, etc. These are omitted for the purpose of clarity. For example it is clear that one skilled in the art would know that the zero count on counter can be recognized by connecting an OR gate to all counter outputs. The OR gate will furnish a "1" output as long as any count exists on the counter but a "0" output when the zero state has been reached. This output signal can then control the reading out of the next subsequent values from main storage S. Similarly the change from a "1" to a "0" at the output of the OR gate can be utilized to test whether or not another counter has also reached a zero output count.

During phase III of FIG. 6 the reference main pressure number Y.sub.p is created in counter Z.sub.p as a function of the present load number Y.sub.L. Again, the non-linear curve of FIG. 5 is approximated by straight line segments as was done for the characteristic shift curve in FIG. 4. The generation of count Y.sub.p is thus completely similar to that of the generation of the limiting load number Y.sub.K. Counter Z.sub.I is again utilized as an interval decoder. The relevant constants, that is slopes and interval values are stored in corresponding storage locations in main storage S and are read-out under control of address logic A and interval counter Z.sub.I as described with reference to the curve approximation of FIG. 4. The number Y.sub.p created in the counter is converted into a corresponding frequency f.sub.p. Specifically the number Y.sub.p /2.sup.8 is multiplied by clock frequency f.sub.0. The multiplier is a so-called rate multiplier and the main pressure reference frequencies f.sub.p can be used directly to control the standard main pressure regulator HR for solenoid valve MV.

The operation in response to a kickdown signal KD will now be discussed. The kickdown signal passes through input logic L1 whose other functions will be described below and is applied through line LG2 to address logic A. In response to the kickdown signal the gear shift is carried out only as a function of speed, that is only under control of binary speed number Y.sub.G on counter Z.sub.G. Different speed threshold values are stored in storage S. Kickdown signal KD also controls two switches U1 and U2 to disconnect counters Z.sub.K and Z.sub.L, respectively, from the comparator logic CL after receipt of the kickdown signal, since neither the present load number Y.sub.L nor the limiting load number Y.sub.K are then to be taken into consideration in determining whether a shift will be allowed. As shown in FIG. 6c the kickdown signal causes counter Z.sub.I to be preset to a starting value Y.sub.KD. If a kickdown signal is present, switches U.sub.1 and U.sub.2 respectively connect counters Z.sub.I and Z.sub.G to comparator logic CL, so that Y.sub.KD is compared to counter Y.sub.G. The comparison is carried out as was the comparison between the counts on counters Z.sub.K and Z.sub.L by counting down both counters with a predetermined frequency, for example frequency f.sub.4. When the count on counter Z.sub.G reaches zero, a test is carried out whether counter Z.sub.I has reached a zero count or not. If the actual speed number exceeds the limiting number Y.sub.KD, a "1" signal is set at terminal 0/1 of output logic AL and, if the opposite is true, a "0" signal is set at this terminal. The action of output logic AL in response to the signal will be discussed in greater detail below. It should also be noted that in response to the kickdown signal the third phase of the cycle is omitted because the main pressure is to be set at the highest possible value and not in accordance with the non-linear characteristic curve of FIG. 5.

At the end of phase I of each cycle a counter ZL' is set to the number YL. At the end of phase I of each cycle two load numbers are thus available, one from the previous cycle and the present load number. A comparator K can thus furnish a load change signal which signifies the direction of change of load or, more specifically, furnishes a "1" signal under decreasing load conditions. If the gas pedal is let up, such a load decrease will be noted. If the present load number Y.sub.L was less than the limiting load number Y.sub.K, and the characteristic curve, was an upshift curve the furnishing of the "1" load change signal causes the initiation of a delay time in output logic AL. This delay time may for example be 500 ms. Following this time the position of the throttle valve is checked. If the throttle valve is closed, that is if a "1" signal exists at terminal E3 of input logic L.sub.1 then an upshift is blocked even though all other conditions for an upshift have been met. This is done in order that the maximum effectiveness can be derived from motor braking. In the absence of a signal at terminal E3 the computation is carried out as described above. A delay time can be created by any one of a number of known means. For example a counter can be counted down from a preset count until it reaches zero.

The gear shift control signals as well as the signals for regulating the regulator stage HR for main pressure valve MV are furnished by output logic AL. First, output logic AL furnishes address control signals B1 and B2 which, for the thenpresent gear, signify the particular shift characteristic curve whose constants are to be read out from storage S. Specifically the generation of signals B1 and B2 can be in accordance with the following truth table:

In accordance with a signal representing the present engaged gear (terminal E.sub.6), which is derived from the switching state of solenoid valves MV1 and MV2, signals B1 and B2 are generated. As in second gear upshift and downshift is possible, signal B2 is held constant in second gear and signal B1 is varied with each operating cycle of the logic. The gear control signal is furnished in accordance with signals B1 and B2 and the state of the signal at terminal 0/1. This is done in accordance with the following table:

The actual gear change is carried out by corresponding activation of solenoid valves MV1 and MV2. A two bit up/down counter is provided within output logic AL. This counter counts up for a upshift operation and down for a downshift operation. The actual switching of solenoid valves MV1 and MV2 takes place only after a predetermined delay time T1. The delay is furnished by a timer in output logic AL and may for example be 200 ms. During this time the main pressure is set. Afterwards the main pressure is regulated as a function of load in accordance with the characteristic curve of FIG. 5 during a further delay T2, which may for example be 800 ms, before it is allowed to return to the maximum permissible value for the new gear.

The operation of input logic L1 and circuits associated therewith will now be discussed briefly. Stored in main storage S are the following values which are transferred to a set of registers R.sub.k at the beginning of each operating cycle.

S.sub.0 =320 Hz

S.sub.1 =3.68 kHZ

S.sub.2 =6.08 kHZ

S.sub.R =Maximum allowable motor speed S.sub.R =6500 min.sup.-1

Y.sub.0 =Initial value of shift curves (FIG. 2), Y.sub.0 =23 kHZ

T.sub.500 =Delay time for upshift "Kick-Up"; adjustable; order of magnitude 500 ms

T.sub.1 =Delay time for setting the maximum main pressure (200 ms)

T.sub.2 =Delay time for regulating the main pressure (800 ms)

The values S.sub.0, S.sub.1 and S.sub.2 are three threshold values for the speed Y.sub.G. The value S.sub.0 is the threshold speed for reverse gear (6 km/h), while threshold values S.sub.1 and S.sub.2 represent the limiting speeds for switching back into the first and second gear respectively. The values S.sub.0, S.sub.1, and S.sub.2 are compared to the speed number Y.sub.G. If the number Y.sub.G exceeds speeds S.sub.0, S.sub.1, and S.sub.2 respectively a "1" signal on lines I.sub.0, I.sub.1, I.sub.2 applied to logic circuit L1 causes possible desired gear shift signals generated under operator control at terminal E.sub.1 to be blocked.

Additional safety features are provided. A main value S.sub.R signifying the maximum permissible engine speed is also stored in storage S. One example of determining whether this speed has been exceeded is use of a counter ZR in output logic AL. This counter is set to a starting value of SR. It is then counted down for a particular angular increment of shaft rotation, as for example the 60.degree. segment of the distributor. If the counter does not reach the value of zero during this angular segment then the motor speed is excessively high and the current supply for the solenoid valves is interrupted.

Various changes and modifications may be made within the scope of the inventive concept.