Decoder Circuit

The present invention relates to a decoder circuit. This decoder circuit is connected to one of a group of word lines which are arranged in a matrix form. Each word line is connected to a large number of binary cells. By using the decoder circuit according to the present invention, one of a large number of binary cells is selected randomly so as to write or read the data.

A dynamic random access memory MISFET integrated circuit which is conventionally used so as to write or read the data into or from a great number of address storage cells is disclosed in U.S. Pat. No. 3,969,706. As illustrated in FIG. 10 of U.S. Pat. No. 3,969,706, a decoder circuit is connected to each one of a group of word lines which are arranged in a matrix form. Each word line is connected to a plurality of storage cells and the decoder circuits determine whether or not the decoder selects (i.e., drives) the word line. This decoder circuit includes: a charge-up transistor for maintaining the content of an input address signal; a power supply switching transistor for controlling a charge-up current which is supplied to the charge-up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge-up transistor and the power supply switching transistor so as to select an output word line, and; a bootstrap transistor which is connected at an opposite side of the connection node with respect to the charge-up transistor.

In the above described conventional decoder circuit, when the selection transistors do not select the word line, occasionally only one of the selection transistors is placed in the on state. Therefore, when the electric charges stored in the connection node of the selection transistors are discharged by the selection transistors which are placed in the on state, a long time is required for the potential level to drop in the connection node, the remaining charges at the connection node keep the bootstrap transistor in the on state and a selection output is supplied to the word line, thus a malfunction is caused and the information stored in the memory cells is destroyed.

An object of the present invention is to provide a decoder circuit which can prevent a malfunction from occurring when the word line is not selected.

Another object of the present invention is to provide a decoder circuit which can rapidly discharge the charges which are stored when the word line is not selected.

For the purpose of achieving the above mentioned objects, the decoder circuit according to the present invention comprises: a charge-up transistor for maintaining the content of an input address signal; a power supply switching transistor for controlling a charge-up current which is supplied to the charge-up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge-up transistor and the power supply switching transistor and which select an output word line; a bootstrap transistor which is connected at an opposite side of the connection node with respect to the charge-up transistor; a first clock pulse generating circuit which generates first clock pulses for driving the power supply switching transistor, and; a second clock pulse generating circuit which generates second clock pulses having a level higher than the power supply voltage V.sub.DD for driving the charge-up transistor.

Further features and advantages of the present invention will be apparent from the ensuing description with reference to the accompanying drawings to which, however, the scope of the invention is in no way limited.

FIGS. 1A, 1B, 1Ba and 1C are schematic diagrams of a conventional decoder circuit;

FIG. 2 is a schematic diagram of one embodiment of the decoder circuit according to the present invention;

FIG. 3 is a schematic diagram of one example of the circuit which generates clock pulses for driving the charge-up transistor illustrated in FIG. 2;

FIG. 4 is a schematic diagram of one example of the circuit which generates clock pulses for driving the power supply switching transistor illustrated in FIG. 2;

FIG. 5 is a graphical representation of various waveforms useful in connection with the description related to FIGS. 2, 3 and 4.

FIG. 1A illustrates a conventional decoder circuit. This decoder circuit is one of the decoder circuits which are connected to word lines of row and column circuits of a matrix. One example of the connection between address lines for selecting the desired cell in the matrix and the decoder circuit is illustrated in FIG. 1C.

In the decoder circuit illustrated in FIG. 1A, the inputs of each decoder are connected to address lines A.sub.0 or A.sub.0 ; A.sub.1 or A.sub.1 ; A.sub.2 or A.sub.2 ; . . . , An or An and the output of each decoder is connected to a word line of a row or column of the matrix. Referring to FIG. 1A and FIG. 1B, EL designates a power supply line, Q.sub.1 a power supply switching transistor, Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n selection transistors and Q.sub.3 a charge-up transistor, Q.sub.4 designates a bootstrap transistor, Q.sub.5 and Q.sub.7 designate low level clamp transistors, Q.sub.6 a transistor for releasing a low level clamp transistor, and N.sub.1, N.sub.2 and N.sub.3 each is a connection node; .phi..sub.1, .phi..sub.2 and .phi..sub.3 designate clock pulse signals, A0-An designates address signal lines and GND designates a ground.

In the circuit illustrated in FIG. 1A, the nodes N.sub.1 and N.sub.2 are charged via the transistor Q.sub.1 to a potential V.sub.DD -V.sub.th, during a reset time, by using a clock pulse signal .phi..sub.1 wherein V.sub.DD is the power supply line voltage and V.sub.th is the threshold voltage of the transistor Q.sub.1. The transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n are connected between node N.sub.1 and ground, and the gates of the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n are connected to the address lines A.sub.0 or A.sub.0 ; A.sub.1 or A.sub.1 ; A.sub.2 A.sub.2 ; . . . ; An or An as illustrated in FIG. 1C. The charge-up transistor Q.sub.3 is connected between the node N.sub.1 and the node N.sub.2 (that is, the gate of transistor Q.sub.4). The bootstrap transistor Q.sub.4 determines whether the potential level of the node N.sub.3 is a logic high or low in accordance with the voltage level in the node N.sub.2 when the clock pulse .phi..sub.3 is received. The gate of transistor Q.sub.3 is connected to the potential level V.sub.DD, so that the potential level at the gate of the transistor Q.sub.4 is driven to a potential higher than the power supply line potential V.sub.DD.

In the circuit illustrated in FIG. 1A, when transistor Q.sub.1 is placed in the on state by a first clock pulse .phi..sub.1 being applied thereto, at a reset time, the nodes N.sub.1 and N.sub.2 are charged up to the potential level of V.sub.DD -V.sub.th, because the gate of the transistor Q.sub.3 is connected to the power supply line voltage V.sub.DD.

If we assume that the proper address signals are supplied to transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n, the potential levels in the nodes N.sub.1 and N.sub.2 in the selected decoder circuits are not changed because transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n are kept in the off state by the address signals Ao-n or Ao-n. However, the electric charges in the nodes N.sub.1 and N.sub.2 in the non-selected decoder circuits are discharged because at least one of the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n is placed in the on state by the address signals Ao-n or Ao-n.

In the selected decoder circuit, when a clock pulse signal .phi..sub.3 is supplied to transistor Q.sub.4, and .phi..sub.3 becomes equal to V.sub.DD, the level at the node N.sub.2 is increased to a potential higher than that of V.sub.DD +V.sub.th due to the capacitance of transistor Q.sub.4. Therefore, an output signal appears at the node N.sub.3 and the potential level at the node N.sub.3 becomes equal to V.sub.DD. In the non-selected decoder circuit, since no charge exists on the nodes N.sub.1 and N.sub.2, the above mentioned function is not carried out, and therefore, the transistor Q.sub.4 is placed in the off state and no output appears at the node N.sub.3.

When the non-selected decoder discharges the charges on the nodes N.sub.1 and N.sub.2, it is preferable that all transistors Q.sub.21, Q.sub.22, . . . , Q.sub.2n are kept in the on state. However, this is very rare, and sometimes it is necessary for the discharge to be carried out by only one transistor. In such a case, a long time is required for the potential to drop at the nodes N.sub.1 and N.sub.2 and, further, the discharge of the electric charges on the node N.sub.3 is more difficult because the potential level at the gate of transistor Q.sub.3 is fixed at the power supply line potential V.sub.DD. Therefore, when a clock signal .phi..sub.3 is applied to transistor Q.sub.4, the charge left at the node N.sub.2 sometimes places transistor Q.sub.4 in the on state and the output appears at the node N.sub.3 so that a malfunction is caused. The node N.sub.3 is usually connected to the word line and, therefore, if a malfunction is caused, the information which is stored in the memory cells attached thereto is destroyed.

In a conventional circuit, the gate of the transistor Q.sub.3 is usually connected to the power supply line potential V.sub.DD, as illustrated in FIG. 1A. However, sometimes the gate (.phi..sub.2) of the transistor Q.sub.3 is connected to the source of the transistor Q.sub.3a, the gate and the drain of which are connected to the power supply line, as illustrated in FIGS. 1B and 1Ba. With regard to FIGS. 1B and 1Ba, the plurality of the decoders illustrated in FIG. 1B are commonly connected to the transistor Q.sub.3a as illustrated in FIG. 1Ba.

In the circuit illustrated in FIGS. 1B and 1Ba, the potential level of the gate .phi..sub.2 varies in dependence upon the mean potential level in the nodes N.sub.1 and N.sub.2 of the plurality of decoder circuits via the capacitance which exists between the gate and the source of the transistor Q.sub.3 and between the gate and the drain of the transistor Q.sub.3, and the potential level of the gate .phi..sub.2 oscillates between the potential levels V.sub.DD +.alpha. and V.sub.DD -V.sub.th because of the following:

When the address signals A or A are applied to the decoder circuit, the nodes N.sub.1 and N.sub.2 of all of the decoders except the selected decoder are grounded, and the gate .phi.2 of the transistor Q.sub.3 is charged up to the potential level V.sub.DD -V.sub.th via the transistor Q.sub.3a. When the decoder is placed in the reset state, the clock pulse .phi..sub.1 is input, and the nodes N.sub.1 and N.sub.2 are charged up, the potential level of the gate .phi..sub.2 is raised to V.sub.DD +.alpha. due to the capacitance of the transistor Q.sub.3. After the nodes N.sub.1 and N.sub.2 are sufficiently charged and the decoder is placed in the reset state, the potential level of the clock pulse .phi..sub.1 is grounded GND, and the nodes N.sub.1 and N.sub.2 are placed in a floating state. Then, when the address signals A or A are input to the decoder circuits, the charges on the nodes N.sub.1 and N.sub.2 of the non-selected decoder circuits are discharged. When the charges on the nodes N.sub.1 and N.sub.2 are discharged, the potential level of the gate .phi..sub.2 drops due to the capacitance of the transistor Q.sub.3, and when the nodes N.sub.1 and N.sub.2 are grounded, the potential level of the gate .phi..sub.2 of the transistor Q.sub.3 becomes equal to V.sub.DD -V.sub.th. As mentioned above, the potential level of the gate .phi..sub.2 of transistor Q.sub.3 follows the mean value of the potential level of the non-selected decoder and the potential level of the gate .phi..sub.2 oscillates between the potential levels V.sub.DD +.alpha. and V.sub.DD -V.sub.th.

Next, the circuit illustrated in FIGS. 1B and 1Ba and the circuit illustrated in FIG. 1A will be compared. In the circuit illustrated in FIGS. 1B and 1Ba, the potential level of the gate .phi..sub.2 is placed at V.sub.DD +.alpha. at the time the nodes N.sub.1 and N.sub.2 begin to discharge. Therefore, the mutual conductance g.sub.m of the transistor Q.sub.3 is higher than in the circuit illustrated on FIG. 1A and the electric charges in the node N.sub.2 in the circuit illustrated in FIGS. 1B and 1Ba discharge at first more rapidly than the circuit illustrated in FIG. 1A. However, when the potential levels of the nodes N.sub.1 and N.sub.2 fall to near ground level, the potential level of the gate .phi..sub.2 falls to near V.sub.DD -V.sub.th, and therefore, the mutual conductance g.sub.m falls to a value lower than that of the circuit illustrated in FIG. 1A and the discharge of the charges on the node N.sub.2 is delayed.

As mentioned above, in the circuit illustrated in FIGS. 1B and 1Ba as well as in the circuit illustrated in FIG. 1A, the discharge of the electric charges on the node N.sub.2 is not carried out sufficiently, and a malfunction may be caused.

In the present invention, the potential level of the gate .phi..sub.2 , illustrated in FIG. 1B, oscillates between the two potential levels of V.sub.DD and V.sub.DD +.alpha., so that the mutual conductance g.sub.m of transistor Q.sub.3 is increased, causing the discharge of the electric charge on the node N.sub.2 to be rapidly carried out and thus preventing a malfunction of the decoder.

Further, in a conventional decoder circuit, the potential level of the clock pulse .phi..sub.1 is V.sub.DD and the potential levels at the nodes N.sub.1 and N.sub.2 are equal to V.sub.DD -V.sub.th. However, in the decoder circuit according to the present invention, the potential level of the clock pulse .phi..sub.1 is higher than V.sub.DD +V.sub.th and the charge-up potential levels in the nodes N.sub.1 and N.sub.2 are equal to V.sub.DD. By increasing the potential level in the node N.sub.2 from V.sub.DD -V.sub.th to V.sub.DD, if the transistor Q.sub.4 is of a small size, the mutual conductance g.sub.m of the transistor Q.sub.4 can be held at that value which is held by the transistor Q.sub.4 when the potential level at the node N.sub.2 is equal to V.sub.DD -V.sub.th. If the transistor Q.sub.4 is small, the capacitance of the transistor is decreased, the electric charges on the node N.sub.2 can be discharged rapidly and malfunction of the decoder can be prevented. The reason for this is as follows:

FIG. 2 illustrates the decoder circuit according to the present invention. The differences between the circuit illustrated in FIG. 2 and the conventional circuits illustrated in FIGS. 1A, 1B and 1Ba, are that the potential level at the gate of the transistor Q.sub.3 oscillates between V.sub.DD and V.sub.DD +V.sub.th and the potential level of the clock pulses .phi..sub.10 is raised to a value higher than V.sub.DD +V.sub.th. As a result of this, the electric charges on the node N.sub.2 can be rapidly discharged and a malfunction of the decoder circuit can be prevented.

The following is an explanation of the operation of the circuit for oscillating the clock pulse signal .phi..sub.20 between levels V.sub.DD and V.sub.DD +.alpha., and the circuit for raising the potential level of the clock pulse signal .phi..sub.10 to the value higher than V.sub.DD +V.sub.th. FIG. 3 illustrates a circuit for generating the clock pulse signal .phi..sub.20. FIG. 4 illustrates a circuit for generating the clock pulse signal .phi..sub.10 and FIG. 5 is a graphical representation of various waveforms useful in connection with the description related to FIGS. 2, 3 and 4. Referring to FIGS. 4 and 5, a clock pulse signal .phi..sub.4 is used for resetting the low level clamp transistor Q.sub.5 and, further, for driving the circuit illustrated in FIG. 4 to generate the clock pulses signal .phi..sub.10 with a potential level V.sub.DD +V.sub.th during a predetermined reset time. Clock pulse signal .phi..sub.5 is used for resetting the circuit illustrated in FIG. 4 and clock pulse signal .phi..sub.6 is used to make a clock pulse .phi..sub.10 low before the address signals Ao-n or Ao-n are input after the nodes N.sub.1 and N.sub.2 are charged up to the potential level V.sub.DD in the circuit illustrated in FIG. 2, thus keeping transistor Q.sub.1 in the off state. Clock pulse signal .phi..sub.6 is also used for keeping the node N.sub.8 shown in FIG. 3 at a potential level higher than V.sub.DD +V.sub.th and for keeping the clock pulse signal .phi..sub.20 at a potential level V.sub.DD during the active time of the circuit illustrated in FIG. 3. The clock pulse signals are generated by the clock pulse generator.

The clock pulse generating circuit for generating the clock pulse signal .phi..sub.20 comprises, as illustrated in FIG. 3: a transistor Q.sub.30, the drain of which is connected to the power supply line voltage V.sub.DD and the gate of which receives the clock pulse signal .phi..sub.10 ; a capacitor C.sub.P1, one terminal of which is connected to the source of the transistor Q.sub.30 and which receives the clock pulse signal .phi..sub.6, on its other terminal and; the transistor Q.sub.31, the gate of which is connected to the connection node between the transistor Q.sub.30 and the capacitor C.sub.P1, the drain of which is connected to the power supply line voltage V.sub.DD and the source of which provides the clock pulse signal .phi..sub.20. In the circuit illustrated in FIG. 3, during the reset time, the node N.sub.8 is charged to the potential level V.sub.DD by transistor Q.sub.30 using the clock pulse signal .phi..sub.10 having a potential level V.sub.DD +V.sub.th. During the active time, the potential level of the node N.sub.8 is caused to rise to V.sub.DD +V.sub.th by the clock pulse signal .phi..sub.6 and the capacitor C.sub.P1, so that the potential level of the clock signal .phi..sub.20 is charged to the potential level V.sub.DD. By applying the clock signal .phi..sub.20 to the gate of the transistor Q.sub.3 illustrated in FIG. 2, the potential level at the gate of the transistor Q.sub.3 oscillates between V.sub.DD and V.sub.DD +.alpha., in accordance with the potential levels at the nodes N.sub.1 and N.sub.2 of the decoder circuit, as illustrated in (f) of FIG. 5. In the circuit illustrated in FIG. 3, the potential level of the clock pulse signal .phi..sub.10 is not necessary higher than V.sub.DD +V.sub.th. If it is assumed that the input potential at the gate of the transistor Q.sub.30 is V.sub.DD, a capacitor having a capacitance larger than that of C.sub.P1 in FIG. 3 should be used for the purpose of raising the node N.sub.8 to a potential level higher than V.sub.DD +V.sub.th.

In the circuit illustrated in FIG. 4, the circuit for generating the clock pulse signal .phi..sub.10 comprises: a series circuit of a transistor Q.sub.11, which receives the clock pulse signal .phi..sub.4, as illustrated in (b) of FIG. 5; a transistor Q.sub.12, which receives the clock pulse signal .phi..sub.5 having an opposite phase with respect to the clock pulse signal .phi..sub.4, as illustrated in (c) of FIG. 5; a series circuit of transistor Q.sub.13, which receives the clock pulse signal .phi..sub.5 of FIG. 5; a transistor Q.sub.14, having a gate which is connected to a connection node between transistors Q.sub.11 and Q.sub.12 ; a transistor Q.sub.15, having a drain which receives the clock pulse signal .phi..sub.4 ; a transistor Q.sub.16, having a gate which is connected to the power supply line voltage V.sub.DD, and a source and a drain which are connected respectively to a connection node between transistors Q.sub.13 and Q.sub.14 and to the gate of transistor Q.sub.15 ; a transistor Q.sub.17, having a drain and a source which are connected between the source of transistor Q.sub.15 and ground GND and a gate which receives the clock pulse signal .phi..sub.6 ; a series circuit of transistor 18, having a gate which is connected to a connection node between the transistors Q.sub.15 and Q.sub.17 ; a transistor Q.sub.19, having an input which is connected to a connection node between the transistors Q.sub.13, Q.sub.14 and Q.sub.16, and; a MOS capacitor C.sub.P2, which is connected between the connection node of transistors Q.sub.15 and Q.sub.17 and the connection node of transistors Q.sub.18 and Q.sub.19.

In the circuit illustrated in FIG. 4, if the clock pulse signal .phi..sub.4, as illustrated in (b) of FIG. 5, is received during the reset time, the potential level in the node N.sub.4 rises and, as a result, transistor Q.sub.14 is placed in the on state and the potential level at the node N.sub.5 falls; furthermore, the clock pulse signal .phi..sub.4 is also applied to transistor Q.sub.15 and, as a result, the potential level at the node N.sub.6 rises and the transistor Q.sub.15 is placed in the on state, so that the potential level of the clock pulse signal .phi..sub.10 is raised by the application of clock pulse signal .phi..sub.4. At the same time, the potential level at the node N.sub.5 falls, the charge on the node N.sub.6, (the potential level of which is raised), is discharged to the node N.sub.5 and transistor Q.sub.16 is placed in the off state. Further, at the same time, the potential level at the node N.sub.7 rises and the potential level of the clock pulse signal .phi..sub.10 is raised to a potential level higher than V.sub.DD +V.sub.th by the bootstrap effect of MOS capacitor C.sub.P2, as illustrated (e) of FIG. 5, and this clock pulse signal .phi..sub.10 is applied to the gate of the transistor Q.sub.1, illustrated in FIG. 2.

As mentioned above, according to the present invention, the potential level of the clock pulse signal for driving the charge-up transistor which holds the content of an input address signal is oscillated between V.sub.DD and V.sub.DD +.alpha., so that the mutual conductance g.sub.m of the charge-up transistor can be increased. Further, the potential level of the clock pulse signal for driving the power supply switching transistor, which supplies the charge-up current to the charge-up transistor, is raised to a value higher than V.sub.DD +V.sub.th, so that the capacitance of the node from which the electric charges are discharged can be decreased and the charges in the non-selected decoder can be rapidly discharged. Therefore, the distruction of the memory cells caused by a malfunction of the decoder can be prevented. Further, the bootstrap effect in the bootstrap transistor is increased, because the potential level in the bootstrap transistor is increased.