Digital Integrated Circuit

The present invention relates to a digital logic circuit, and more particularly, to a digital logic circuit to be realized as a monolithic integrated circuit.

As is well known, accompanying progress in large scale integrated circuit (hereinafter referred to as LSI) of digital logic circuits, the number of internal nodes therein has been greatly increased, and especially where the circuit contains memory elements (flip-flops or the like), the entire testing of such LSI has become extremely difficult.

For overcoming this difficulty, a method, so-called scan-path method for simplifying the test by converting a general sequential logic circuit comprised in the circuit into a combinational logic circuit has been known, in which flip-flops are arranged at particular portions within a logic circuit to divide them into a number of groups so that each flip-flop group may be independently operated as a shift register upon a test operation mode which is different from a normal operation mode, and at any arbitrary time point the state of any arbitrary flip-flop can be read or rewritten by connecting test terminals to the clock input, data input, data output, etc. of the flip-flop group. While this method is surely very effective for simplifying the method for testing an LSI, its shortcoming exists in that test input and output terminals therefore are greatly increased in number. Though this shortcoming is not remarkable in the case where a large scale logic circuit is constructed according to the conventional system which uses as a basic unit a printed circuit card having integrated circuits of small scale integration mounted thereon and having a large number of connector terminals, it is becoming extremely disadvantageous at present because, accompanying the increase of a degree of integration of integrated circuit, there remains no margin for additional terminals.

Therefore, it is one object of the present invention to provide a digital integrated circuit which is additionally provided the function of checking or the like without increasing the number of terminals.

Another object of the present invention is to provide a digital integrated circuit in which a maximum number of input and output terminals are assigned for a normal operation mode that is an inherent purpose of use of the circuit and the number of terminals required for a function test is minimized.

A digital integrated circuit, especially a monolithic integrated circuit according to the present invention, is characterized in that an integrated circuit is provided with, in addition to a plurality of input and output terminals, at least one control terminal, and functions of at least a part of the input and output terminals are determined in response to the logical level at the control terminal.

The present invention is based on the recognization that even with physically n input (output) terminals, they can function as 2n terminals if different functions are assigned to each terminal depending upon a logical state of another control terminal, for instance, depending upon whether it is "1" or "0". Of course, provision must be made in the assignment such that among the 2n functions, the former n functions may not be used simultaneously with the latter n functions. This principle can be easily extended to the case of m control inputs. Furthermore, the present invention is based on the recognition that if the so-called third value in a voltage value region other than the normal logical voltage region (for instance, -0.5 V.about.+5.5 V in the case of TTL) is used (for instance, an inverter input terminal operating at a threshold value of +8 V is connected in parallel to a normal TTL terminal) and this third value is employed as the mode control input, that is, if a normal logic mode is realized at -0.5 V.about.+5.5 V and a third mode is realized at 8 V or higher, then the terminal efficiency can be further enhanced.

According to one feature of the present invention, there is provided a monolithic digital integrated circuit including a plurality of input terminals, a plurality of output terminals, and at least one mode control input terminal, which circuit has one or more operation modes corresponding to the control terminal, and in which at least a part of the input and output terminals are controlled by the mode control input terminal so that they may achieve different functions in the different operation modes.

According to another feature of the present invention, there is provided the above-featured digital integrated circuit, in which at least a part of the input (output) terminals also physically serve as control terminals, such that in a normal logical voltage value region they may function as input (output) terminals in one operation mode but at a predetermined voltage value region higher or lower than the normal logical voltage value region (hereinafter this predetermined voltage value region being called "a third value") they may function as control terminals in such manner that they inhibit the one operation mode and at the same time activate another operation mode.

According to still another feature of the present invention, in the above-featured monolithic digital integrated circuit, the operation modes include at least one test operation mode besides the normal operation modes, and the former is used for logic debugging or fault diagnosis.

According to yet another feature of the present invention, in the above-described monolithic digital integrated circuit, one or more groups of flip-flops are included, and each flip-flop group achieves a flip-flop operation in response to one or more clock inputs in the normal operation mode, but operates as a shift register in response to clock inputs applied to the same clock input terminals in the test operation mode.

According to a still further feature of the present invention, there is provided a monolithic digital integrated circuit including, as a part of its logic construction, one or more assemblies of programmable AND logic terms ("AND array"), one or more assemblies of programmable OR logic terms ("OR array"), or one or more OR arrays driven by one or more AND arrays, that is, the so-called programmable logic arrays (PLA), which comprises in the test operation mode, a selection circuit including a shift register that acts on the AND array or OR array so as to selectively activate one or a part of the respective AND terms or OR terms, that is, which has parallel outputs such that

(1) all the AND (OR) terms other than the selected AND (OR) terms may be inactivated and the entire logic is operated only by the selected AND (OR) terms, and

(2) the states of only the selected AND (OR) terms are transmitted to separately provided data output terminals,

and in which at least a part of the various inputs, that is, all the activation inputs, shift operation clock inputs, shift in data and data outputs in the test operation mode of the selection circuit, uses the terminals in common with the inputs (outputs) in the other operation modes .

These and other features and advantages of the invention will become apparent from the following detailed description of the preferred embodiments of the invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing an integrated circuit according to a first preferred embodiment of the present invention,

FIG. 2 is a block diagram showing an integrated circuit according to a second preferred embodiment of the present invention,

FIG. 3 is a circuit diagram showing an inverter to be used in the second preferred embodiment of the present invention,

FIG. 4 is a block diagram showing an integrated circuit according to a third preferred embodiment of the present invention, and

FIG. 5 is a block diagram showing a fourth preferred embodiment of the present invention.

Now a first preferred embodiment of the present invention will be described with reference to FIG. 1. A logic section 10 in a semiconductor integrated circuit has six inputs I.sub.1 to I.sub.6 and six outputs O.sub.1 to O.sub.6, and is controlled by mutually complementary mode control signals C and C. The inputs I.sub.1 and I.sub.2 are inputs which are always necessary irrespective of an operation mode, and are directly fed through input terminals I.sub.11 and I.sub.12, respectively. The outputs O.sub.1 and O.sub.2 are likewise necessary to be always derived, and are directly derived through output terminals O.sub.11 and O.sub.12, respectively. The combination of inputs I.sub.3 and I.sub.4 and the combination of the inputs I.sub.5 and I.sub.6 are never used simultaneously but only either one combination or the other is used. The combination of the outputs O.sub.3 and O.sub.4 and the combination of the outputs O.sub.5 and O.sub.6 are also never used simultaneously but only either one combination or the other is used, and in the illustrated embodiment it is assumed that the combination of the outputs O.sub.3 and O.sub.4 is used jointly with the combination of the inputs I.sub.3 and I.sub.4, while the combination of the outputs O.sub.5 and O.sub.6 is used jointly with the combination of the inputs I.sub.5 and I.sub.6. The inputs I.sub.3 to I.sub.6 are applied via 2-input AND gates A.sub.1 to A.sub.4, respectively. To one input of each of the AND gates A.sub.1 and A.sub.2 is applied, as a gate signal, a first mode control signal C that is fed from a terminal IC without modification. Whereas, to one input of each of the AND gates A.sub.3 and A.sub.4 is applied, as a gate signal, asecond mode control signal C that is complementary to the signal C and is fed from the terminal 1C through an inverter 11. On the other hand, the outputs O.sub.3 and O.sub.4 are derived to output terminals O.sub.21 and O.sub.22, respectively, through AND gates A.sub.5 and A.sub.6 to which the first mode control signal C is inputted and through OR gates R.sub.1 and R.sub.2, respectively. Likewise, the outputs O.sub. 5 and O.sub.6 are also derived to the output terminals O.sub.21 and O.sub.22, respectively, through AND gates A.sub.7 and A.sub.8 to which the second mode control signal C is inputted and through the OR gates R.sub.1 and R.sub.2, respectively. The logical integrated circuit according to the illustrated embodiment has two operation modes, in which one operation mode may be a normal operation mode, and the other operation mode may be a test mode.

More particularly, the first operation mode is the operation involving the inputs I.sub.1, I.sub.2, I.sub.3 and I.sub.4 and the outputs O.sub.1, O.sub.2, O.sub.3 and O.sub.4 which occurs in response to a higher level (logic "1" level) of the first mode control signal C, while the second operation mode is the operation involving the inputs I.sub.1, I.sub.2, I.sub.5 and I.sub.6 and the outputs O.sub.1, O.sub.2, O.sub.5 and O.sub.6 which occurs in response to a higher level of the second mode control signal C. In these respective operation modes, the unnecessary inputs are fixed at logic "0" level by closing AND gates in the illustrated embodiment. As described above, according to this preferred embodiment, an integrated circuit provided with many functions, that is, many input-output logic functions in this case can be realized while reducing the number of terminals to a small number. It is to be noted that the numbers of the inputs, outputs and mode control inputs as well as the details of the mode switching logic are not limited to those of the above-described embodiment.

Next, a second preferred embodiment of the present invention will be described with reference to FIGS. 2 and 3.

A logic circuit 20 has the same construction as that illustrated in FIG. 1, and input terminals I.sub.11 and I.sub.12 are directly coupled to inputs I.sub.1 and I.sub.2, respectively, while output terminals O.sub.11 and O.sub.12 are directly coupled to outputs O.sub.1 and O.sub.2, respectively. An input terminal I.sub.21 is coupled to inputs I.sub.3 and I.sub.5, respectively, via AND gates A.sub.1 and A.sub.3. Likewise, an input terminal I.sub.22 is coupled to inputs I.sub.4 and I.sub.6, respectively, via AND gates A.sub.2 and A.sub.4. On the other hand, outputs O.sub.3 to O.sub.6 are derived to output terminals O.sub.21 and O.sub.22 via AND gates A.sub.5 to A.sub.8 and OR gates R.sub.1 and R.sub.2. The above-mentioned construction is entirely similar to the first preferred embodiment. In this second preferred embodiment, a second mode control signal C is generated by an inverter 21 having a high threshold value (for example, 10 V) which is higher than the normal logic voltage region and coupled to the input terminal I.sub.21, while a first mode control signal C is generated by inverting the second mode control signal C through an inverter 22, and these mode conrol signals C and C are applied to the circuit 20 and the respective AND gates. In this embodiment, when the terminal I.sub.21 is within the normal logic voltage region (for instance, 0 to 5.5 V in the case of a TTL logic), the inverter 21 senses it as a lower level logic input (logic "0") and generates a higher level ("1") output C, whereas when the terminal I.sub.21 is at the third logic level (for instance, about 10 V), the inverter 21 senses it as a higher level logic input and generates a lower level output C. It will be readily understood without further explanation that these mode control signals C and C obtained as inverter outputs drive the respective AND gates exactly in the same manner as the first preferred embodiment and thereby can realize two operation modes. However, attention should be paid to the fact that in this preferred embodiment, when an input at the third level is applied to the input terminal I.sub.21, that is, during the first operation mode, the input I.sub.3 of the logic circuit 20 is always applied with a higher level of input signal. One preferred embodiment of the inverter 21 is illustrated in FIG. 3. This circuit includes transistors Q.sub.1, Q.sub.2 and resistors R.sub.1 and R.sub.2, and if the ratio of the resistance values R.sub.1 /R.sub.2 is chosen at an appropriately small value, the transistor Q.sub.2 is held OFF at the normal TTL level ("0" or "1") of OV to 5.5 V, but it will be turned ON when a voltage that is sufficiently larger than the Zener breakdown voltage of the transistor Q.sub.1 (the third level input voltage) is applied to the input terminal I.sub.21, and thereby a desired mode control output C can be obtained.

Now a third preferred embodiment of the present invention will be described with reference to FIG. 4. In this embodiment, let us consider the case where a general sequence circuit including flip-flops is divided into a series of flip-flop groups and another combinational logic section when a test is performed. In this case, as is well known, it is extremely desirable even for the purpose of mere testing of the system to arrange a part of or the whole series of flip-flop groups comprised therein so as to be operable as a shift register and to prepare inputs and outputs therefor, and this preferred embodiment uses this system. A logic section 30 including a combinational logic circuit comprises input I.sub.1 ', I.sub.2 ' and I.sub.3 ' coupled to input terminals I.sub.31, I.sub.32 and I.sub.33, respectively, outputs O.sub.1 ' and O.sub.2 ' coupled to output terminals O.sub.31 and O.sub.32, respectively, and an output O.sub.3 ' coupled to an output terminal O.sub.33 via AND gate A.sub.25 and OR gate R.sub.3. This logic section 30 may be, for example, a PLA including at least one of an AND array and an OR array having inputs I.sub.1 ' to I.sub.3 ', N.sub.12 and N.sub.22 and outputs O.sub.1 ' to O.sub.3 ', N.sub.11 and N.sub.21. Also the logic section 30 is coupled with a flip-flop F/F.sub.1 through a write-output terminal N.sub.11 which supplies the flip-flop F/F.sub.1 with an information to be written therein and through a read-input terminal N.sub.12 which supplies the logic section 30 with an information read-out from the flip-flop F/F.sub.1. Similarly, the logic section 30 is coupled with a flip-flop F/F.sub.2 through a write-output N.sub.21 which supplies the flip-flop F/F.sub.2 which supplies the logic section 30 with an information read-out from the flip-flop F/F.sub.2. As the flip-flops F/F.sub.1 and F/F.sub.2, commonly used flip-flops such as those disclosed in FIG. 2 of U.S. Pat. No. 3,644,758 may be used. In this case, the flip-flop F/F.sub.1 of the present invention may easily be realized by taking the input terminals 1 and 2 and clock terminals C1 and C2 of the above-cited flip-flop and respectively connecting them to the output N.sub. 11, the output 14, and the clocks 1 and 2 of the present invention, FIG. 4. The output 5 or 6 of the above-cited flip-flop may be coupled to the input end 12 of the present invention, FIG. 4. Similarly, the flip-flop F/F.sub.2 of the present invention may easily be realized by taking the input terminals 1 and 2 and the clock terminals C1 and C2 of the cited flip-flop and respectively coupling them to the outputs N.sub.21, N4 and clocks 1 and 2 of the present invention, FIG. 4. Again, the output terminals 5 or 6 of the above-cited reference may simply be coupled to the input M.sub.22 of FIG. 4.

In a normal operation mode, these flip-flops F/F.sub.1 and F/F.sub.2 are coupled with the logic section 30 through these inputs and outputs N.sub.11 to N.sub.22 and operate so as to define the state of the circuit 30. Wherein, an AND gate A.sub.23 having one input coupled to a mode control signal terminal C and the other input coupled to a clock input terminal I.sub.22 is opened to supply the flip-flops F/F.sub.1 and F/F.sub.2 with a clock signal CLK1 which makes the flip-flops F/F.sub.1 and F/F.sub.2 operate independently in parallel in response to the logic "1" level of the mode control signal supplied at the terminal C. While, in another operation mode, i.e. test mode, an AND gate A.sub.24 having its inputs coupled to an output C of an inverter 11, an input of which is coupled to the mode control signal terminal C, and coupled to the clock terminal I.sub.22 is opened to supply the flip-flop F/F.sub.1 and F/F.sub.2 with a clock signal CLK2 in response to the logic "1" level of the output C. This clock signal CLK2 makes the flip-flops F/F.sub.1 and F/F.sub.2 operate as a shift-register. When this clock CLK2 is applied to the flip-flops F/F.sub.1 and F/F.sub.2 in response to a higher level ("1") of the signal C, data applied to the input terminal I.sub.33 is applied to the flip-flop F/F.sub.1 as shift-in data I.sub.4 via an AND gate A.sub.22 to which the signal C is inputted, an output M.sub.4 of this flip-flop F/F.sub.1 is inputted to the flip-flop F/F.sub.2 as an intermediate shift input, and an output of the flip-flop F/F.sub.2 is derived as shift-out data O.sub.4 at the output terminal O.sub.33 via an AND gate A.sub.26 to which the signal C is inputted and the OR gate R.sub.3. Assuming now that the mode control terminal C is at a lower level, i.e. logic "0", and at the same time if a clock CLK2 for performing a shift operation of the flip-flop F/F.sub.1 and F/F.sub.2 is applied to the terminal I.sub.22 and shift data are applied to the input terminal I.sub.33, then both the AND gates A.sub.22 and A.sub.24 are opened, the AND gate A.sub.26 in the output section is also opened, and thereby the two flip-flops F/F.sub.1 and F/F.sub.2 can perform a shift register operation. In this case, these flip-flops can be controlled so as to have their memory state forcibly and externally set, instead of operating as an internal state memory associated with the logic section 30. Accordingly, the inputs N.sub.12 and N.sub.22 for the logic section 30 can be controlled externally, and therefore, testing of the logic section 30 can be achieved. In the present embodiment, saving of terminals is achieved by utilizing the terminals I.sub.33 and O.sub.33 in common for the input I'.sub.3 and output O'.sub.3 and for the shift-in data I.sub.4 and shift-out data O.sub.4 respectively as well as the clock signal terminal I.sub.22 for the clock signal CLK1 and for the clock signal CLK2.

Finally, a fourth preferred embodiment of the present invention will be described with reference to FIG. 5. In this preferred embodiment, the invention is described as applied to a programmable logic array, so-called PLA including an AND-OR array which is most popular as a combinational logic, and further, as the most appropriate example in the case of converting it to a sequential logic, we will consider the case where a part of an OR-array output is fed back to an AND-array input via flip-flops. Such a PLA is known, as disclosed in U.S. Pat. No. 3,958,110, for example.

An input buffer section 1 is inputted from input terminals I.sub.101 to I.sub.116 and from outputs Q.sub.1 to Q.sub.8 of a flip-flop section 5, and its outputs are inputted to an AND-array section 2. This AND-array section has AND term outputs A'.sub.1 to A'.sub.128, and these AND term outputs A'.sub.1 to A'.sub.128 are inputted to an OR-array section 3. A part of the outputs of the OR-array section 3 is inputted to the flip-flop section 5, and the other outputs are outputted to output terminals 0.sub.101 to 0.sub.108 via an output buffer section 4. The respective output terminals A'.sub.1 to A'.sub.128 of the aforementioned AND-array section 2 are forciby selected, that is, set at a higher level by the outputs of the shift register section 6 independently of the input condition. In the AND-array and OR-array, any arbitrary cross-points can be programmed as indicated by black dots. The black dot at the cross-point is practically realized by means of a transistor, diode, etc.

To the shift register section 6 is applied a data input DIA through a terminal DI, and an output DOA of the shift register section 6 is derived to an output terminal DO via an AND gate A.sub.13 and an OR gate R.sub.20. In this embodiment, the terminals DI and DO are commonly used as data input and output terminals, respectively, of the flip-flop section 5. To the shift register section 6 are also applied an enable signal ADE and a clock signal CLK13. An enable input terminal EN is coupled to inputs of an inverter 51 and an AND gate A.sub.11, the other input of the AND gate A.sub.11 is applied with an output ADE of the inverter 51, and the output of the AND gate A.sub.11 is applied to the output buffer section 4 as its enable signal CE. The signal ADE is applied to an input of an AND gate A.sub.10 the other input of which is coupled to a clock terminal CLK, and the output of the AND gate A.sub.10 is applied to the output buffer section 4 as a latch clock CLK.sub.10. While, an output of an inverter 52 is applied to the shift register section 6 as an enable signal ADE, and also applied to an AND gate A.sub.12 the output of which is applied to the shift register section 6 as a clock signal CLK13. The inverter 51 has a treshold value at the third level (for example, 10V) apart from normal operation levels (for example, 0-5 V) and performs a logic operation with respect to this threshold value in the similar manner to the inverter illustrated in FIG. 3. Consequently, depending upon whether the enable input terminal EN is at the normal operation levels or at the third level, switching is performed between the normal operation mode and the mode in which the AND term selection operation in the shift register section 6 is activated. In the former mode, since the signal ADE is at a lower level ("0") and thus the clock signal CLK13 is blocked, the shift register section 6 is inactivated and the output buffer section 4 is enabled. While in the latter mode, the shift register section 6 is enabled. In this way, by means of the enable signal ADE, switching is effected between the output latch clock signal CLK10 and the shift clock signal CLK13 for the shift register section 6. As described above, in the logic integrated circuit constructed as shown in FIG. 5, what is as important as the controllability and observability of the condition of the flip-flop section 5 upon test debugging, is the controllability and observability of the respective terms in the AND-array 2 and OR-array 3, especially of the respective AND terms A'.sub.1 to A'.sub.128. While the former can be realized by the well-known shift register connection as described above, with regard to the latter the mode of activating the AND term selection circuit by the shift register section 6 is necessary, and it is possible to make the shift register section 6, which consists of 128 bits in the case described, forcibly select any arbitrary one of the AND terms by introducing data from the data input terminal DI under control of the terminals CLK and EN. Then the observation of the output generated by the forcibly selected AND term can be achieved by means of the output terminals O.sub.101 to 0.sub.108 by once returning the signal at the terminal EN to a signal having the normal logic amplitude and thereby operating the output buffer 4.

As described above, according to the present invention, the number of terminals of an extremely wide variety to monolithic logic integrated circuits can be reduced by appropriately utilizing an independent or third-level-responsive mode control input terminal EN and commonly using a plurality of input and output signal terminals depending upon use or non-use of input and output signals in the respective operation modes, and thereby effective utilization of the terminals can be achieved. Therefore, the effects of the present invention are extremely large.

It is to be noted that the present invention should not be limited to the above-described preferred embodiments but a wide scope of application thereof could be made.