Electrical Communications System

This invention relates generally to communications apparatus and more particularly to a system whereby both digital and analog signals in any desired combination are transmitted on demand from one or more signal sources to a selected one or more utilization devices.

Communications at radio frequencies over wired and wireless transmission channels are well known. More recently the emergence of fiber optic conductors of light has found utility as a medium for transmitting a signal carrier in the light region of the electromagnetic spectrum. In the case of digital data, memories have also been included at either end for purposes of multiplexing and demultiplexing data from plural sources so that a common channel can be utilized. While these various and sundry systems are adapted to accomplish a wide range of tasks, it is the purpose of the present invention to provide an improvement in such communications systems, particularly for transmitting digital data, originating at diverse signal sources, from one location to another and storing the data for a momentary or predetermined time for subsequent selected utilization by one or more diverse utilization devices.

The present invention is directed to a system wherein a plurality of data streams originating at separate input signal sources, fixed or portable, are fed to a first random access memory which when loaded is outputted on demand, either automatically or manually, over a first energy type or RF communications link to a second random access memory. The second memory on demand, outputs the data coupled thereto from the first memory over a second energy type, optical or when desirable inductive, communications link to a terminal device including a third random access memory. On demand, the third memory outputs its contents to one or more utilization devices. The means included in the first energy type communications link is also adapted to include means for simultaneously transmitting analog data along with the digital data. In one form, the first and second random access memories on either side of the first type communications link are adapted to remain relatively stationary, whereas the input signal sources and the terminal device including the third random access memory may be selectively a portable or fixed piece of apparatus, depending upon the use intended.

FIG. 1 is a block diagram broadly illustrative of the subject invention;

FIG. 2 is a detailed block diagram illustrative of the preferred embodiment of the RF transmission portion of the system shown in FIG. 1;

FIG. 3 is a detailed block diagram illustrative of the RF receiver and optical transmitter portion of the system shown in FIG. 1;

FIG. 4 is a detailed block diagram illustrative of the optical receiver portion of the system shown in FIG. 1; and

FIG. 5 is a detailed block diagram illustrative of a typical memory control circuit for operating the random access memories shown in FIGS. 2, 3 and 4 .

Referring now to the drawings and more particularly to FIG. 1, a plurality of signal sources 10.sub.1, 10.sub.2 and 10.sub.3 are shown coupled to a digital memory 12, preferably a random access memory (RAM) operated by means of a memory controller 14. The memory controller 14, a typical example of which is further disclosed in FIG. 5, is adapted to load data into the RAM 12 and upon demand, either automatically or manually, output its contents in sequence to an RF (first energy type) transmitter 16 where it is modulated onto an RF carrier. The carrier is then coupled to an RF communications link 18 in the form of a signal which is adapted for transmission via a radio/microwave antenna or a coaxial cable. Additionally, an analog signal source 20 which is adapted, for example, to generate an audio and/or video signal, is also applied to the RF transmitter 16 for simultaneous single or multiplexed transmission over the RF communications link 18 with the digital data outputted from the memory 12.

At the far or receiving end of the RF communications link 18 is located an RF receiver 22 which is adapted to demodulate the communications signals on the carrier and accordingly couple the analog signal transmitted to an analog signal utilization device 24 while the digital data outputted from the RAM 12 is fed into a second random access memory 26 under the control of a respective memory controller 28. The memory controller 28 on demand subsequently outputs the contents of the RAM 26 to an optical (second energy type) transmitter 30 where the data is modulated onto a carrier of light energy. The light energy is transmitted over an optical communications link 32 to an optical receiver located in a terminal device, not shown. The light signal is demodulated and the digital data is fed into a third random access memory 36 under the control of its own memory controller 38. Upon demand, the digital memory 36 outputs the digital data fed thereto selectively to one or more utility devices 40.sub.1, 40.sub.2 and 40.sub.3.

What the broad system disclosure of FIG. 1 is intended to show is the concept of first sending digital and/or analog signals originating at a plurality of input signal sources, some or all of which may be portable, over RF communication means utilizing various types of modulation techniques e.g. frequency modulation, phase modulation, amplitude modulation, pulse code modulation, stored either on a real time or long term basis for later optical transmission to a device, either portable or fixed, which is adapted to store the selected signals as necessary and thereafter apply it to predetermined utilization device(s). Particularly, however, digital data in the form of a data stream is adapted to be intermediately or momentarily stored, for selective transfer upon command to the next location. Thus the data from any of the digital signal sources 10.sub.1, 10.sub.2 and 10.sub.3 is first relayed to the digital RAM 26 over the RF link 18 at some appointed time. Thereafter when it is desirable to do so, the data stream is then coupled over the optical communications link 32 to the digital memory 36.

This concept has particular utility, for example, where the optical receiver 34, the digital memory 36 and the memory controller 38 are all included in a portable terminal, not shown, which is adapted to be brought, from time to time, into proximity with the optical transmitter 30, which is located in a fixed installation, also not shown. More particularly, the fixed installation at the RF end and optical transmitter location may consist of a piece of hardware secured to a wall of a building or inside a room with the optical transmitter 30 including at least one light emitting diode or other such device which is adapted to output an IR or pulse/intensity modulated signal. This signal is coupled to a photo pick up device contained in a relatively small portable device which is brought into proximity with and pointed at the light emitting source wherein the light is then directed to the photo pick up device, thus completing the optical link 32. The digital memory 26 in the fixed installation can then be ordered when desirable to transfer its data to the digital memory 36 in the portable device where it is then adapted to be displayed, coupled to a printer, or activate some type of control device.

Referring now to FIG. 2, there is shown in greater detail the input side of the system. Whereas the RAM 12 and the memory controller 14 are as shown in FIG. 1, FIG. 2 is intended to additionally illustrate that a plurality of diverse input signal sources are adapted to feed respective digital data streams to the RAM 12 by means of a data bus 42, which includes, for example, a plurality of parallel data lines. The data bus 42 couples the RAM 12 to the outputs of four input devices; a keyboard 44, a graphics generator 46, a television camera 48 and an auxiliary storage 50 which may be, for example, a read only memory (ROM). The storage 50 may be comprised of disk, tape, bubble, core, semiconductor type of memory of known type. When desirable these input devices may be duplicated and some or all may be made selectively portable and coupling to the RAM 12 effected by way of respective optical input/output ports.

The memory controller 14 is adapted to strobe load the memory addresses of the RAM 12 upon receiving clock signals from the respective signal sources until the desired number of data bytes have been inputted thereto. Upon command, as will be shown when FIG. 5 is considered, the memory controller 14 resets the memory address of the RAM 12 and the data bytes stored therein are coupled in sequence to a multi-line parallel output data bus 60. The data bus 60 feeds into an input gated parallel-to-serial converter 62, which is strobe loaded upon receipt of three control signals i.e. gate, strobe load, and clock signals from the memory controller 14. The parallel-to-serial converter 62 is a well known device, a typical example being a Fairchild F3843 USART (Universal Synchronous or Asynchronous Receiver and Transmitter.) The output from the parallel-to-serial converter 62 is coupled to a frequency shift keying XR-2206 type voltage to frequency converter 64. Coupled to the variable frequency output of the converter 64 is a multiplexer type circuit 66 which is adapted for single or multiplexed operation so that an analog signal from the source 68 can be applied simultaneously along with the FSK output from the converter 64. The signal source 68 may be, for example, an audio signal source. When desirable, it may be comprised of a video signal source.

The output from the multiplexer 66 is coupled to an RF modulator 70 of any selected design. The RF modulator generates an RF carrier signal modulated in accordance with the signals supplied from the circuits 64 and 68. The modulated carrier is then fed to a radiating antenna 72 or when desirable, to a coaxial cable 74. The RF transmission elements shown are not meant to be interpreted in a limiting sense since when desirable other means may also be employed such as, for example, microwave apparatus could also be utilized. Also as noted above, other types of modulation may be resorted to when desirable.

Referring now to FIG. 3, the RF communications link 18 is terminated, as shown, either in a receiving antenna 76 or the far end of the co-axial cable 74. The RF signals appearing thereat are coupled to the input of an RF demodulator and demultiplexer 78 which is operable to remove the analog signal from the carrier and couple it to a transducer element 80, which may be, for example, a loud-speaker in the case of an audio signal emanating from the analog signal source 68. The digital data format outputted from the RAM 12 as shown in FIG. 2, is also removed from the carrier and is fed to at least one digital memory module 80.sub.1 which includes the RAM 26 and its associated memory controller 28 originally shown in FIG. 1. The memory module 80.sub.1 may be duplicated when desirable to other identical modules 80.sub.2 and 80.sub.3 . In each instance the respective module includes an active filter 82 which is adapted to be frequency selective so that a routing action can be obtained, when desirable, between the multiple memory units. The active filter 82 is coupled to a frequency to voltage XR-2211 type frequency to voltage converter 84 where the frequency shift keying operation is reversed. The variable voltage signal outputted from the converter 84 is next fed to a serial-to-parallel converter 86 which may also be comprised of a Fairchild F3843 USART inasmuch as it is a duplex device whereby both parallel-to-serial and serial-to-parallel conversions can be implemented thereby. A parallel multi-line data bus 88 couples to the RAM 26 and the multi-bit data stream in the form of bytes are fed into the RAM under the control of the memory controller 28 which is also adapted to receive a clock signal from the serial-to-parallel converter 86. When desirable the serial-to-parallel converter 86 may embody an addressable gate controlling data flow to RAM 26. Once the RAM 26 has been loaded with data from the RAM 12 shown in FIG. 2, the memory controller 28 will cause the memory to become inactive until such time that a cycle out command is provided, either manually or by some desired means, at which time the RAM will output its contents which is then strobe loaded into an input gated parallel-to-serial converter 92 over the data bus 94. The serial data stream outputted from the converter 92 is fed to an amplifier 96 which is adapted to intensity modulate the light output from a respective light emitting source 98, a typical example being a light emitting diode. Each of the other memory modules 80.sub.2 and 80.sub.3 also couple to individual light emitting sources 100 and 102 which are respectively modulated in accordance with signals outputted from the respective memories contained therein. The intensity modulated light outputted from the light emitting source 98 and the light emitting sources 100 and 102 when utilized, are launched into the optical communications link 32 which may comprise simply a gaseous medium such as air, or when desirable space or a vacuum, but may also consist of one or more optical fibers 104, which are adapted to couple any one light emitting source to a remote photo pickup device which maybe, for example, a matching photo-diode.

Turning attention now to FIG. 4, a photo pickup device 106 is coupled to the light emitting source 98 of FIG. 3. Additionally, photo pickups 108 and 110 are adpated to be coupled to light emitting sources 100 and 102 also shown in FIG. 3. While the use of light emitting diodes and the respective photo-diodes is preferred, inductive coupling means can be utilized when desirable for the second energy type communications link. Each of the photo pickup devices 106, 108 and 110 are adapted to form part of and be coupled to respective terminal units 112.sub.1, 112.sub.2 and 112.sub.3, each of which is adapted to include a RAM 36 and memory controller 38 such as shown in FIG. 1.

Each terminal unit 112 includes an amplifier 114 coupled to the respective photo pickup device. The amplifier output is coupled to a serial-to-parallel converter 116 which converts the serial data stream into a parallel data stream which is fed into the RAM 36 via the data bus 118. The memory controller 38 also receives a clock signal from the converter 116 in order to initially reset the memory addresses, strobe the data into the memory and sequentially index the addresses following completion of the storage of each data byte. When desirable, a display device 120 is included. Following receipt of the data into the RAM 36, the memory controller 38 is then adapted on command such as by means of a cycle out switch, not shown, to output the data contained therein onto an output bus 120 where it is strobe loaded into an input gated parallel-to-serial converter 122, whereupon a serial data stream in the form required by one or more utilization devices, is provided. Utilization devices 40.sub.1, 40.sub.2, 40.sub.3 shown in FIG. 1 are shown in FIG. 4 comprising cathode ray tube display 124, an output printer 126, a graphics display 128 or a switch mechanism 130 for controlling an external device, not shown.

Thus the individual random access memories 12, 26 and 36 act in combination with its respective peripheral hardware to store and transfer digital data which is coupled to and from the respective memories in the form of multiple bit data streams or bytes. In order that intelligent management of the data stream flow be provided an illustrative embodiment of the memory controllers 14, 28 and 30 is shown in FIG. 5.

There a clock signal, generated in any one of the data sources 44, 46 . . . 50 shown in FIG. 2 or by the serial-to-parallel converters 86 and 116 shown in FIGS. 3 and 4, is coupled to an input lead 132 which is applied to a one-shot circuit 134. This circuit is an electrical circuit for generating a trigger pulse in response to a signal being applied and thereafter automatically resetting itself until the next signal is applied. The one shot circuit 134 accordingly responds to the clock signal applied to generate a memory strobe load signal which is coupled to its associated memory for strobe loading the parallel data presentation or byte into a particular memory address. Additionally, an initial reset switch 136 is included which is adapted to be responsive, for example, to the leading edge of the first clock signal to provide a reset signal for recycling the respective memory to the initial or first address position. Additionally, the initial reset swtich 136 is coupled to an address counter 138 and a memory counter 140 which are reset to the zero count position by the action of the initial reset switch. It should also be pointed out that when desirable the reset switch 136 may be comprised of a manually actuated switch device rather than one being shown as operated in accordance with a leading edge of the clock signal.

A second one-shot circuit 142 is coupled to the one-shot circuit 134 and is adapted to be triggered when circuit 134 resets. The output of the one-shot circuit 142 provides an output pulse which is applied directly to counter 140 and through buffer 141 to counter 138 to advance the count each time a byte of data is entered into the respective memory. This process is repeated until all the desired data bytes are entered into the appropriate addresses.

When the contents of the respective memory is desired to be outputted i.e. translated to its respective output data bus, a cycle out switch 144, included in each memory controller, is actuated on demand either manually or by remote control and operates to trigger a third one-shot circuit 146 which generates a pulse to reset the address counter 138 to a zero count and triggers on a latch 148 which in turn enables the converter's gated input as well as gate circuit 150 coupled to a local source of clock signals 152. The output of gate 150 provides a clock signal for the parallel-to-serial converters. Pulses gated from the local clock source 152 and also divided by a.div.N counter 155 and are fed to a one-shot circuit 154 which is adapted to strobe load the respective parallel-to-serial converters 62, 92 and 122, respectively. The N count is equal to the number of data lines being inputted from serial-to-parallel converters 86 and 116 to their respective memories 26 and 36. Each time the one-shot circuit 154 restores it triggers one-shot circuit 156 which produces a trigger pulse which is coupled to the address counter 138 through the buffer amplifier 158, thereby causing the address counter 138 to advance the memory to the next address position. On the next clock pulse outputted from the clock 152 the readout process is repeated. This action continues until the count in the address counter 138 matches the previously stored count in the memory counter 140. A comparator circuit 160, coupled to both counters 138 and 140, monitors the counters looking for a match, meaning that on readout the address counter 138 has cycled the memory to the same number of counts read into the memory counter 140 during the read-in phase. When both counts are equal, the comparator circuit 160 triggers another one-shot circuit 162 which produces a trigger signal to trigger off the latch 148, which acts to disable the gate 150, thereby interrupting the output of clock pulses from the clock 152 to the one-shot circuit 154. This causes the readout cycle to stop, meaning that the readout process of the data from the respective memory has been completed.

Thus what has been shown and described is a means for relaying electrical signals such as digital data first over an RF communications link, and then over an optical communications link, so that data can be conveyed from a local source of diverse signals to a remote data terminal having a memory which upon demand can thereafter output the data to one or more selected diverse types of utilization devices.

Having thus shown and described what is at present considered to be the preferred embodiment of the subject invention, modifications and alterations thereto will readily occur to those skilled in the art. It is not desired, therefore, that the invention be limited to the specific arrangements shown and described, but it is intended to cover all such modifications and alterations which fall within the true spirit and scope of the invention as defined by the appended claims.