US 4,255,209 AGrant
Process of Fabricating an Improved I.sup.2 L Integrated Circuit Utilizing Diffusion and Epitaxial Deposition
Issue Date:1981-03-10
•12 Claims
•2 Drawing Sheets
Abstract
In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector. This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation. The process of fabrication includes forming the vertical transistor's base by diffusion into a first surface of a substrate of opposite conductivity type, forming the vertical transistor's emitter epitaxially on the first surface and forming the vertical transistor's collector and the lateral transistor's emitter and collector by diffusion into the opposite surface of the substrate. The lateral transistor's collector diffusion is from the opposite surface down to the vertical transistor's base and separates the vertical transistor's collector from the portion of the substrate which is the lateral transistor's base. For integrated circuits, the process includes dividing the substrate into a plurality of dielectrically insulated regions after forming the epitaxial emitter and depositing a polycrystalline support.
Metadata
Assignee
- Harris Corporation
Inventors
- William R. Morcom
- Hugh C. Nicolay
- Eugene R. Cox
Application Information
Application Number:US 1063413
Filing Date:1979-12-21
Priority Date:1978-02-07
Art Unit:111
Classifications
IPC:
H01L 2120H01L 2122H01L 2710
Field of Search:
14829357156175;187;191577 C;578;58035;44;48;49;50;89;90;92647;649;662
Patent Drawings (2 sheets)
Description
Background of the Invention
The present invention relates generally to bipolar integrated circuits and more particularly to integrated injection logic (I.sup.2 L).
The use of merged transistor logic or integrated injection logic (I.sup.2 L) has made possible high packing density of low power integrated circuits. The standard I.sup.2 L structure is an NPN device with an active PNP load fabricated such that the collector of the PNP and the base of the NPN share the same semiconductor region and the base of the PNP and the emitter of the NPN are common. The structures of the prior art have generally not provided both transistors having a high gain or Beta. Similarly, the particular structure and method of fabrication of I.sup.2 L structure of the prior art have not permitted their effective use with transistor to transistor logic (T.sup.2 L). Thus three exists a need for an I.sup.2 L structure which is simple to manufacture and provides complementary transistors sboth with high current gains and in an integrated circuit which allows compatibility with T.sup.2 L devices.
Summary of the Invention
The present invention is an I.sup.2 L structure of bipolar transistors including a vertical and a lateral transistor. The vertical transistor includes a heavily doped emitter region formed on a lightly doped substrate of the same conductivity type, a lightly doped graded base region in the substrate in direct contact with the epitaxial emitter region and a heavily doped collector region formed in the opposite surface of the substrate and having the same conductivity type. The lateral transistor includes heavily doped emitter and collector regions formed in the opposite surface of the substrate where the collector acts to separate the portion of the substrate which forms the base of the lateral transistor from the heavily doped collector region of the vertical transistor.
The I.sup.2 L transistors of the present invention may be included in an integrated circuit wherein the lightly doped substrate is divided into a plurality of dielectrically isolated areas which may include other I.sup.2 L and T.sup.2 L bipolar transistors. The support structure of the plurality of dielectrically isolated substrate regions is a heavily doped polycrystalline material of the same conductivity type as the substrate. The heavily doped epitaxial layer or the emitter region of the vertical transistor is connected to the heavily doped substrate through an opening in the dielectric insulated layer so as to interconnect the emitters of the vertical transistors. The opening may be vertically aligned with the base of the vertical transistor.
The process of fabrication of the I.sup.2 L structure of the present invention begins with diffusing impurities of first conductivity type into a single crystal substrate of a second conductivity type to form the graded base of the vertical transistor. The diffused region and the substrate are both lightly doped. A heavily doped epitaxial layer is grown on the surface of the substrate into which the base is diffused to form an emitter region of the vertical transistor. Impurities are then diffused in the opposite or second surface of the substrate to form the emittter and collector regions of the lateral transistor with the collector diffusing down to the diffused base region of the vertical transistor. Impurites are then diffused into the second surface of the substrate to form a heavily doped collector region of the same conductivity type as the substrate. The collector region of the lateral transistor separates the base portion of the substrate of the lateral transistor from the collector region of the vertical transistor.
The pesent process may be used to form integrated circuits having I.sup.2 L structures and T.sup.2 L devices. The above process is modified wherein the substrate is divided into a plurality of regions dielectrically isolated. The dielectric isolation is performed after the formation of the heavily doped epitaxial layer. Openings are provided in the dielectric isolation before formation of the heavily doped polycrystalline support layer so as to interconnect all of the emitter regions of the vertical transistors through the support layer of the same conductivity type. The process steps used to form the emitter of the lateral transistor can also be used to form a base of a T.sup.2 L transistor in other diectrically isolated regions and the step used to form the collector of the vertical transistor can be used to form the collector and emitter of a T.sup.2 L bipolar transistor.
Objects of the Invention
An object of the present invention is to provide an improved I.sup.2 L semiconductor structure.
Another object is to provide an I.sup.2 L structure wherein both transistors have a high current gain or Beta.
A further object of the invention is to provide an I.sup.2 L structure wherein the buried emitter of the vertical transistor is in direct contact with a graded buried base region.
Still another object of the invention is to provide an integrated circuit having dielectric isolation and including improved I.sup.2 L structure in combination with T.sup.2 L devices.
Other objects, advantages, and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a cross-sectional view of a structure of an I.sup.2 L structure incorporating the princples of the present invention.
FIG. 2 is a schematic diagram of the I.sup.2 L structure of FIG. 1.
FIGS. 3-8 are cross-sectional views illustrating the different stages of the process of fabrication of an integrated circuit having isolated I.sup.2 L structures and T.sup.2 L devices incorporating in the princples of the present invention.
Description of the Preferred Embodiments
FIG. 1, which illustrates a preferred embodiment of the I.sup.2 L structure shows a vertical NPN device formed in a lightly doped N.sup.- substrate 10 and including a heavily doped N.sup.+ collector 12 formed in surface 14 of the substrate, a lightly doped graded P.sup.- base 16 and a heavily doped N.sup.+ epitaxial emitter 18. A lateral PNP transistor is also formed in the substrate 10 having a heavily doped P.sup.+ collector 20 and a heavily doped P.sup.+ emitter 22 formed in the top surface 14 of substrate 10 and a base region formed from the lightly doped N.sup.- substrate region 10. The P.sup.- base region 16 of the vertical NPN transistor is graded having a heavier doped region adjacent to the N.sup.+ epitaxial emitter region 18 and decreasing toward surface 14. P.sup.+ region 20 which is the collector of the lateral PNP transistor separates the N.sup.+ collector region 12 from the portion of the N.sup.- substrate 10 which forms the base of the lateral transistor. Also heavily doped P.sup.+ region 20 provides surface contact areas for the buried lightly doped P.sup.- base region 16 of the vertical transistor.
The schematic view of FIG. 2 illustrates that the collector 12 of the NPN transistor and the emitter region 22 of the PNP transistor provide terminals for the I.sup.2 L structure with the emitter region 18 and the base region 10 of the NPN and PNP transistors respectivley being commonly connected and grounded. Base region 16 of the NPN transistor and the collector region of the PNP transistor are commonly connected in the semiconductor material.
The high current gain or Beta of the NPN transistor results from the high concentration of emitter region 18 and that it is in intimate contact with a graded base region 16 in such a matter to aid the flow of carriers across the base region 16. The PNP transistor achieves increased current gain or Beta because of the good lifetimes produced by the single crystal base region 10.
The I.sup.2 L structure, illustrated in FIG. 1, may be part of an intergrated circuit including a T.sup.2 L structure formed in a dielectrically isolated substrate region. The process for forming the dielectric isolation and the I.sup.2 L structure and T.sup.2 L device of the present invention is illustrated in FIGS. 3-8. The process begins with a substrate 10 having a masking material, for example, an oxide 24 formed on a first surface 26 and an opening 28 formed therein by standard photolithographic operations for the buried base region 16 of the NPN transistor. Impurities, for example, boron are diffused into surface 26 through opening 28 by ion implantation or deposition. The P.sup.- region 16 will have a impurity concentration, for example, 5.times.10.sup.17 atoms/cc in a substrate having impurity concentration of 1.times.10.sup.16 atoms/cc. The oxide layer 24 is then removed and an N.sup.+ epitaxial region 18 is grown on surface 26. Substrate 10 being a single crystal structural produce an epitaxial layer 18 of single crystal structure and layer 18 will have impurity concentration of, for example, 1.times.10.sup.21 atoms/cc.
A masking layer, for example, oxide 29 is grown on the epitaxial layer 18 and delineated by standard photolithographic processes to form openings 30 in the mask layer 29. The epitaxial layer 18 and the substrate 10 are then etched to form the V-shape moats 32 illustrated in FIG. 4. Oxide layer 29 is then removed and a new layer of oxide 34 is grown over the epitaxial layer 18 and in the moats 32. Opening 36 is formed in the oxide layer 34 which may be vertically aligned and have horizontal dimensions substantially equal to the horizontal dimensions of the P.sup.- base region 16. It should be noted that even though a single base region 16 is shown, opening 36 in oxide layer 34 is formed for each substrate region having a base region 16. A highly doped N.sup.+ polycrystalline material is deposited over the oxide layer 34 into opening 36 to provide a support 38 for the substrate. The opposite surface 26 of the substrate is then polished down to the bottom of the moats 32 to define a surface 14 and to divide the substrate 10 into a plurality of dielectrically isolated regions on a support 38. This is illustrated in FIG. 6.
It should be noted that forming region 16 by diffusing impurities into layer 26 and later placing a high impurity N.sup.+ region thereon, the base region 16 is in intimate contact with the emitter of the NPN transistor and has a graded impurity concentration which is heaviest at the emitter and which decreases towards the collector region.
A masking layer, for example, oxide 40 is grown on surface 14 of the substrate 10 and openings 42, 44 and 46 are formed therein. Boron, for example, is deposited and diffused through the openings 42, 44 and 46 to form collector region 20 and emitter region 22 of the I.sup.2 L structure and a base region 48 of a T.sup.2 L device, respectively. The resulting regions have an impurity concentration, for example, 5.times.10.sup.18 atoms/cc. The collector region 20 is formed to a depth sufficient to contact the buried P.sup.- region 16 and to separate the subsequent to be formed collector region of the NPN transistor from the base region of the lateral PNP transistor. The device at this stage is illustrated in FIG. 7.
The oxide mask 40 and oxide formed during diffusion is removed and a new oxide layer 50 is formed thereon with openings 52, 54 and 56 delineated therein. An N.sup.+ dopant, for example, phosphorous, is deposited and diffused through openings 52, 54 and 56 to form a collector region 12 for the I.sup.2 L structure and collector and emitter regions 58 and 60 for the T.sup.2 L device, respectively having an impurity concentration, for example, of 1.times.10.sup.21 atoms/cc. The structure at this point in the process is illustrated in FIG. 8. Oxide is then formed over the substrate and openings provided thereon for the required surface interconnects.
The integrated circuit illustrated in FIG. 8 includes an I.sup.2 L structure and a T.sup.2 L device in dielectrically isolated regions. The I.sup.2 L structures are interconnected on the surface as well as through the openings in the dielectric isolation 34 and the heavily doped N.sup.+ polycrystalline support 38. Although a single I.sup.2 L structure is shown formed in a dielectrically isolated region, a plurality of such structures may be formed in a single dielectrically isolated region.
From the preceding description of the preferred embodiments, it is evident that the objects of the invention are obtained and although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation. The impurities may be reversed such that the complementary pair of transistors for the I.sup.2 L structure may be formed in a P-type substrate. The spirit and scope of this invention are to be limited only by the terms of the appended claims.
Claims
What is claimed:
1. A process for fabricating a high gain complementary pair of bipolar transistors comprising: diffusing impurities of a first conductivity type in a first surface of a substrate of a second conductivity type opposite said first conductivity type to form a first region; epitaxially forming a layer on said first surface of said second conductivity type; diffusing impurities of said first conductivity type into a second surface of said substrate opposite said first surface to form a second region extending from said second surface to said first region and to form a third region; diffusing impurities of said second conductivity type into said second surface to form a fourth region separated from said third region by said second region; said epitaxial layer, said first region and said fourth region forming the emitter, base and collector respectively of a first transistor and said third region, said substrate and said second region forming the emitter, base and collector respectively of a second transistor complementary to said first transistor.
2. The process according to claim 1 wherein said first diffusion is performed to form a graded lightly doped first region and said epitaxial growth is performed to form a heavily doped layer.
3. The process according to claim 1 wherein said substrate is a lightly doped single crystal material and said second diffusion is performed to form heavily doped second and third regions.
4. The process according to claim 1 including dividing said substrate and said epitaxial layer into a plurality of spaced regions and dielectrically isolating said spaced substrate regions by an insulative layer.
5. The process according to claim 4 including forming an opening in said insulative layer adjacent said first region and forming a polycrystalline layer of said second conductivity type on said insulative layer and in said opening.
6. The process according to claim 5 including forming transistors in other dielectrically isolated substrate regions, and forming openings in said insulative layer for each substrate region having a first region.
7. The process according to claim 5 wherein said opening is formed to have the horizontal dimension of said first region and to be vertically aligned therewith.
8. A process for fabricating an integrated circuit having I.sup.2 L and T.sup.2 L transistors comprising: diffusing impurities of a first conductivity type in a first surface of a substrate of a second conductivity type opposite said first conductivity type to form a plurality of spaced first regions; epitaxially forming a layer on said first surface of said second conductivity type; dividing said substrate and said epitaxial layer into a plurality of laterally spaced regions; forming an insulative layer on said epitaxial layer and the lateral substrate edges of said laterally spaced substrate regions; forming an opening in said insulative layer adjacent said epitaxial layer for each substrate region having a first region; forming a layer of said second conductivity type on said insulative layer and in said openings; diffusing impurities of said first conductivity type into a second surface of said substrate opposite said first surface (a) to form a plurality of second regions extending from said second surface to a corresponding first region, (b) to form a plurality of third regions one in each of the laterally spaced substrate regions having a first region, and (c) to form at least one fourth region in a laterally spaced substrate region not including a first region; diffusing impurities of said second conductivity type into said second surface (a) to form a plurality of fifth regions separated from a corresponding third region by a corresponding second region, (b) to form at least one sixth region in the surface of said fourth region, and (c) to form at least one seventh region in the laterally spaced substrate region including said fourth region; said epitaxial layer, said first regions and said fifth regions forming the emitter, base and collector respectively of a first plurality of first transistor of an I.sup.2 L structure, said third regions, said substrate and said second regions forming the emitter, base and collector respectively of a plurality of second transistors of said I.sup.2 L structure complementary to said first transistors, and said sixth region, said fourth region and said seventh region forming the emitter, base and collector respectively of a T.sup.2 L transistor.
9. The process according to claim 8 wherein said first diffusion is performed to form graded lightly doped first regions and said epitaxial growth is performed to form a heavily doped layer.
10. The process according to claim 8 wherein said substrate is a lightly doped single crystal material and said second diffusion is performed to form heavily doped second, third and fourth regions.
11. The process according to claim 8 wherein said third diffusion is performed to form heavily doped fifth, sixth and seventh regions.
12. The process according to claim 8 wherein said openings are formed to be vertically aligned with a corresponding first region.
Patent Citations (9)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3440498 | 1969-04-01 | Mitchell | |
| US3508980 | 1970-04-01 | Jackson et al. | |
| US3858237 | 1974-12-01 | Sawazaki et al. | |
| US3990102 | 1976-11-01 | Okuhara et al. | |
| US4032957 | 1977-06-01 | Yagi et al. | |
| US4076556 | 1978-02-01 | Agraz-Guerena | |
| US4081697 | 1978-03-01 | Nakano | |
| US4087900 | 1978-05-01 | Yiannoulos | |
| US4101349 | 1978-07-01 | Roesner et al. |
Non-Patent Literature (4)
- Berger et al., "Base Ring Transistor and Method of Production" I.B.M. Tech. Discl. Bull., vol. 14, No. 1, Jun. 1971, p. 302.
- Cook, Bob, "Anodizing Silicon . . . Isolate IC Elements" Electronics, Nov. 13, 1975, pp. 109-113.
- Kindl, T. E., "L.S.I. System" I.B.M. Tech. Discl. Bull., vol. 21, No. 2, Jul. 1978, pp. 494-497.
- McGreivy et al., "Up-Diffused I.sup.2 L . . . Bipolar LSI Process" Proc. IEDM, Wash. D.C., Dec. 1976, pp. 308-311.