Accuracy Correction in an Electronic Timepiece

The present invention relates to an accuracy correction system in an electronic timepiece.

In general a quartz oscillator is employed in an electronic timepiece for developing a reference signal of a predetermined frequency, for example, one hertz via an appropriate frequency dividing means. Therefore, the accuracy of the electronic timepiece mainly depends on the precision of the quartz oscillator. However, the natural frequency of the quartz oscillator is unavoidably different from each other due to different manufacturers of the individual quartz oscillators. Moreover, the natural frequency of the quartz oscillator will undergo modification with the lapse of time in an irreversible manner due to on account of the "ageing" and matching between the quartz oscillator and a C-MOS inverter included within the oscillation circuit.

Heretofore, the oscillation frequency of the quartz oscillator has been adjusted through the use of a variable capacitor called a trimmer. The conventional adjustment was achieved in an anologue fashion and was unavoidably complicated.

Accordingly, an object of the present invention is to provide an accuracy correction system for correcting a reference signal frequency in an electronic timepiece in a digital fashion.

Another object of the present invention is to provide an accuracy correction signal input system for introducing a frequency correction signal into a frequency divider included within an electronic timepiece.

Still another object of the present invention is to provide a quartz tester arrangement for indicating a correction value in a form suitable for correcting a reference signal frequency in an electronic timepiece in a digital fashion.

Yet another object of the present invention is to provide a combination for correcting a reference signal frequency in an electronic timepiece, including a quartz tester arrangement for measuring the accuracy of the reference signal frequency and indicating the displacement of the reference signal frequency, and an electronic timepiece comprising a reference signal frequency correction means having an input system corresponding to an indication unit provided at the quartz tester arrangement.

Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

To achieve the above objectives, pursuant to an embodiment of the present invention, a quartz tester arrangement measures the accuracy of the reference signal frequency and indicates the displacement of the reference signal frequency from the standard signal frequency with the use of five lamps, each of which is selected to be enabled in accordance with the detected value of the displacement. A reference signal frequency correction means in an electronic timepiece includes five manually operative switches corresponding to said five lamps and functions to increase or decrease the reference signal frequency in a digital fashion with the use of a low frequency signal, the low frequency signal being generated in response to the closing of the manually operative switches.

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:

FIG. 1 is a circuit diagram of an embodiment of an accuracy correction system comprising a quartz tester including a value detector, and an electronic timepiece including a gain pulse generator, a lose pulse generator and control switches;

FIG. 2 is a circuit diagram of an embodiment of the gain pulse generator shown in FIG. 1;

FIG. 3 is a time chart showing various signals occurring within the gain pulse generator of FIG. 2;

FIG. 4 is a circuit diagram of an embodiment of the lose pulse generator shown in FIG. 1;

FIG. 5 is a time chart showing various signals occurring within the lose pulse generator of FIG. 4; and

FIG. 6 is a cross-sectional view of an embodiment of a control switch shown in FIG. 1.

In general a quartz oscillator employed in an electronic timepiece shows deviations of around .+-.15 PPM due to different makes of individual quartz oscillators, of around .+-.6 PPM due to the phenomenon of "ageing", and of around .+-.3 PPM due to the matching between the quartz oscillator and a C-MOS inverter included within the oscillation circuit. Therefore, the maximum value of the deviation caused by the above-mentioned three factors is .+-.24 PPM. The maximum deviation in a day can be calculated as follows:

Accordingly, the displacement in a day caused by the deviation of the oscillation frequency usually lies within a range between +2 seconds/day and -2 seconds/day. When the displacement in a range between zero (0) and 2 seconds/day is divided into twelve (12) blocks and correction values are determined for the respective blocks, the deviation after the correction can be reduced to around 0.09 seconds/day as shown in the following TABLE I.

It will be clear from TABLE I that, when, for example, the deviation lies within a range between 0.79 seconds/day and 0.96 seconds/day, the correction of 0.879 seconds/day is performed and, therefore, the deviation is reduced to a range between -0.089 seconds/day and +0.081 seconds/day after the correction. When the deviation lies in the first block, namely, between 0.00 seconds/day and 0.10 seconds/day, the correction is not performed because the deviation is so little that the reference frequency is almost accurate.

Referring now to FIG. 1, there is illustrated a circuit diagram of an embodiment of an accuracy correction system of the present invention, which comprises an electronic timepiece A and a quartz tester arrangement B.

The electronic timpiece A includes an oscillation circuit 1, a frequency divider 2, a second information counter 3, a minute information counter 4, an hour information counter 5, a suitable display means (not shown), a decoder circuit 6, five (5) manually operable control switches 7, a gain pulse generator 8, a lose pulse generator 9, and several gate means. The quartz tester arrangement B mainly comprises a conventional quartz tester 10. A typical circuit construction of the quartz tester is shown in U.S. Pat. No. 3,238,764 "METHOD FOR MEASURING THE ACCURACY OF TIMEPIECES" invented by Rudolf Greiner and patented on Mar. 8, 1966. In this embodiment the quartz tester 10 is "SHARP QUARTZ METER LX-811" manufactured by SHARP KABUSHIKI KAISHA. The quartz tester arrangement B further includes a deviation value detector 11, five(5) indication lamps 13, and a decoder/driver circuit 12 for enabling the lamps 13.

The oscillation circuit 1 includes a quartz osillator and generates a base signal f.sub.0 of 32,768 hertz. The frequency divider 2 comprises a chain of T-type flip-flops FF.sub.21, FF.sub.22, FF.sub.23, - - - , and FF.sub.2n and develops a reference signal f.sub.s of one hertz. An OR gate OR.sub.1 is disposed between the second T-type flip-flop FF.sub.22 and the third T-type flip-flop FF.sub.23 is connected to receive not only an output signal f.sub.o /4 of the second T-type flip-flop FF.sub.22 but also a gain pulse p.sub.f and a lose pulse P.sub.d, which will be described later. The reference signal f.sub.s of one hertz is sequentially introduced into the second information counter 3, the minute information counter 4 and the hour information counter 5. The time information stored in the respective counters is displayed on a display unit via suitable decoder/driver circuits. The display unit and the decoder/driver circuits can be of any construction known in the art and since the specific details thereof do not constitute a part of the present invention they have been omitted from the drawing for the purposes of simplicity.

The quartz tester 10 included within the quartz tester arrangement B can measure the accuracy of the electronic timepiece A in the order of 1/100 seconds/day. When the electronic timepiece A is set on an appropriate place of the quartz tester arrangement B, the quartz tester 10 picks up a signal P of around 32 hertz from the frequency divider 2 included within the electronic timepiece A in order to develop signals A, B, C, - - - , and J in a binary-coded decimal notation in accordance with the measurement of the accuracy of the electronic timepiece A. The signals A (1), B (2), C (4) and D (8), in combination, represent the deviation in the order of 0.1 seconds/day, the signals E (1), F (2), G (4) and H (8), in combination, represent the deviation in the order of 0.01 seconds/day, and the signals I (1) and J (2), in combination, represent the deviation in the order of 10.sup.0 seconds/day. An additional output signal K bears the logical value "1" when the deviation takes a nagative value, whereas the output signal K bears the logical value "0" when the deviation takes a positive value.

The deviation value detector 11 receives the output signals of the quartz tester 10 in the binary-coded decimal notation to develop signals 1 , 2 , - - - , and 11 in accordance with the following TABLE II.

When, for example, the measured deviation lies in a range between 0.11 seconds/day and 0.26 seconds/day, only the signal 1 bears the logical value "1". When the measured deviation lies in a range between 0.27 seconds/day and 0.44 seconds/day, only the signal 2 bears the logical value "1". In the same manner, only the signal 11 takes the logical value "1" when the measured deviation is in a range between 1.85 seconds/day and 2.00 seconds/day. When the measured deviation is in a range between 0.00 seconds/day and 0.10 seconds/day, no signals take the logical value "1".

The decoder/driver circuit 12 receives the signals 1 through 11 to convert them into binary signals in accordance with the signal number bearing the logical value "1", whereby activating lamps L.sub.1, L.sub.2, L.sub.3 and L.sub.4 in the binary notation. That is, the lamps L.sub.1, L.sub.2, L.sub.3 and L.sub.4 correspond to the decimal number one (1), two (2), four (4) and eight (8), respectively. When, for example, the signal 3 from the deviation value detector 11 takes the logical value "1", the lamps L.sub.1 and L.sub.2 are enabled. The decoder/driver circuit 12 also receives the output signal K of the quartz tester 10, thereby to enable a lamp L.sub.5 when the output signal K bears the logical value "1" to indicate that the deviation takes a negative value.

When one (1) pulse is added to or subtracted from the output signal f.sub.o /4 of the second T-type flip-flop FF.sub.22 every one minute by controlling the input signal of the third T-type flip-flop FF.sub.23 every one minute, the accuracy of the electronic timepiece A will be corrected by 0.176 seconds in a day because the output signal f.sub.o /4 has a frequency of 32,768/4 hertz and;

When two (2) pulses are added to or subtracted from the signal f.sub.o /4 every one minute, the correction of 0.352 seconds/day will be effected. The accuracy of the electronic timepiece will be corrected by 1.934 seconds/day by adding or subtracting eleven (11) pulses to or from the signal f.sub.o /4 every one minute.

The second information stored in the second information counter 3, namely, BCD (binary-coded decimal) output signals as to seconds and ten seconds are introduced into the decoder circuit 6, which develops signals D.sub.6, D.sub.12, D.sub.14, D.sub.18, D.sub.24, D.sub.28, D.sub.30, D.sub.36, D.sub.42, D.sub.48 and D.sub.59 which take the logical value "1" when the contents of the second information counter 3 are six (6), twelve (12), fourteen (14), twenty-four (24), twenty-eight (28), thirty (30), thirty-six (36), fourty-two (42), fourty-eight (48), and fifty-nine (59), respectively. The signal D.sub.59 is applied to one terminal of a switch S.sub.1 within the control switches 7. The signals D.sub.14 and D.sub.28 are applied to one terminal of a switch S.sub.2 of the control switches 7 via an OR gate OR.sub.2. The signals D.sub.30, D.sub.36, D.sub.42 and D.sub.48 are conducted to one terminal of a switch S.sub.3 included within the control switches 7 through an OR gate OR.sub.3. The signals D.sub.30, D.sub.36, D.sub.42 and D.sub.48 are also conducted to one terminal of a switch S.sub.4 in unison with the signals D.sub.6, D.sub.12, D.sub.18 and D.sub.24 via an OR gate OR.sub.4. When the control switches S.sub.1, S.sub.2, S.sub.3 and/or S.sub.4 are closed, the signals conducted to the respective switches are applied to an AND gate AND.sub.1 and another AND gate AND.sub.2 via an OR gate OR.sub.5. One (1) signal is applied to the OR gate OR.sub.5 when the switch S.sub.1 is closed. Two (2) signals are applied to the OR gate OR.sub.5 when the switch S.sub.2 is switched on. Four (4) signals are supplied to the OR gate OR.sub.5 when the switch S.sub.3 is turned on. Eight (8) signals are applied to the OR gate OR.sub.5 when the switch S.sub.4 is closed. Accordingly, the number of signals to be applied to the AND gates AND.sub.1 and AND.sub.2 via the OR gate OR.sub.5 can be desirably selected up to eleven (11) in a binary fashion because the switches S.sub.1, S.sub.2, S.sub.3 and S.sub.4 correspond to the decimal numbers one (1), two (2), four (4) and eight (8), respectively. One terminal of a switch S.sub.5 included within the control switches 7 is always supplied with a signal taking the logical value "1". The other terminal of the switch S.sub.5 is connected to the AND gate AND.sub.1 and to the AND gate AND.sub.2 via an inverter In.sub.1, whereby the AND gate AND.sub.1 is set ON when the switch S.sub.5 is closed and the AND gate AND.sub.2 is set ON when the switch S.sub.5 is switched off.

An output signal of the AND gate AND.sub.1 is applied to the gain pulse generator 8 for developing the gain pulse P.sub.f, whereas an output signal of the AND gate AND.sub.2 is applied to the lose pulse generator 9 for developing the lose pulse P.sub.d. The gain pulse generator 8 is connected to receive the base signal f.sub.o and the output signals f.sub.o /2 and f.sub.o /4 from the first and second T-type flip-flops FF.sub.21 and FF.sub.22 included within the frequency divider 2 as clock pulses. The lose pulse generator 9 is connected to receive the inverted base signal f.sub.o via an inverter In.sub.2 and the output signals f.sub.o /2 and f.sub.o /4 as clock pulses.

A typical circuit construction of the gain pulse generator 8 is shown in FIG. 2. The operation mode of the gain pulse generator 8 will be described with reference to the FIG. 3 time chart.

When a signal bearing the logic value "1" is applied to the D terminal of a D-type flip-flop FF.sub.81 from the AND gate AND.sub.1, the Q output of the D-type flip-flop FF.sub.81 takes the logic value "1" upon occurrence of the first leading edge of the output signal f.sub.o /4 as shown in FIG. 3 Q.sub.81. The Q output signal of a D-type flip-flop FF.sub.82 bears the logic value "1" upon occurrence of the following leading edge of the output signal f.sub.o /4 as shown in FIG. 3 Q.sub.82. An AND gate AND.sub.81 receives the Q output signal Q.sub.81 of the D-type flip-flop FF.sub.81 and the Q output signal Q.sub.82 of the D-type flip-flop FF.sub.82, and applies the output signal Q.sub.81 .multidot.Q.sub.82 thereof to an AND gate AND.sub.82. The AND gate AND.sub.82 is connected to receive the output signal Q.sub.81 .multidot.Q.sub.82, the base signal f.sub.o, an inverted signal f.sub.o /2 of the output signal f.sub.o /2 via an inverter In.sub.81, and an inverted signal f.sub.o /4 of the output signal f.sub.o /4 via an inverter In.sub.82, thereby to develop an output signal Q.sub.81 .multidot.Q.sub.82 .multidot.f.sub.o /4.multidot.f.sub.o /2.multidot.f.sub.o, which acts as the gain pulse P.sub.f. Therefore, the gain pulse P.sub.f has a pulse width identical with a half period of the base signal f.sub.o and assumes the logic value "1" when the output signal f.sub.o /4 bears the logic value "0".

When the gain pulse P.sub.f is added to the output signal f.sub.o /4 of the second T-type flip-flop FF.sub.22 by the OR gate OR.sub.1, the pulse number of the signal f.sub.o /4 increases by one. The adding operation is performed at every time when the D terminal of the D-type flip-flop FF.sub.81 receives the signal of the logic value "1". The electronic timepiece A becomes fast by 0.176 seconds in a day when one (1) pulse is added to the output signal f.sub.o /4 every one minute. The electronic timepiece A becomes fast by 0.352 seconds in a day when two (2) pulses are added to the output signal f.sub.o /4 every one minute. In the same way, the electronic timepiece A becomes fast by 1.934 seconds in a day by adding eleven (11) pulses to the output signal f.sub.o /4 in one minute.

A typical circuit construction of the lose pulse generator 9 is shown in FIG. 4, of which the operation mode will be described with reference to the FIG. 5 time chart.

A NAND gate NAND.sub.91 is connected to receive an inverted signal f.sub.o of the base signal f.sub.o generated from the oscillation circuit 1, the output signal f.sub.o /2 of the first flip-flop FF.sub.21 included within the frequency divider 2 and the output signal f.sub.o /4 of the second flip-flop FF.sub.22 included within the frequency divider 2, thereby to develop an output signal f.sub.o .multidot.(f.sub.o /2).multidot.(f.sub.o /4). When the D terminal of a D-type flip-flop FF.sub.91 receives a signal bearing the logic value "1" from the AND gate AND.sub.2, the Q output Q.sub.91 of the D-type flip-flop FF.sub.91 takes the logic value "1" upon first occurrence of the leading edge of the output signal of the NAND gate NAND.sub.91 as shown in FIG. 5 Q.sub.91.

A Q output signal Q.sub.92 of a following D-type flip-flop FF.sub.92 bears the logic value "1" upon occurrence of the following leading edge of the output signal of the NAND gate NAND.sub.91 (see FIG. 5 Q.sub.92). An AND gate AND.sub.92 is connected to receive the Q output signal of the flip-flop FF.sub.91 and the Q output signal of the flip-flop FF.sub.92 in order to develop an output signal Q.sub.91 .multidot.Q.sub.92 as the lose pulse P.sub.d. Therefore, the lose pulse P.sub.d has a pulse width identical with one period of the output signal f.sub.o /4 and is positioned in such a manner to have the logic value "1" when the output signal f.sub.o /4 assumes the logic value "0" between the two adjacent portions of the logic value "1".

When the lose pulse P.sub.d is added to the output signal f.sub.o /4 of the second T-type flip-flop FF.sub.22 by the OR gate OR.sub.1, the pulse number of the output signal f.sub.o /4 is decreased by one as will be clear from the FIG. 5 time chart. The decrement operation is performed at every time when the D terminal of the D-type flip-flop FF.sub.91 receives the signal taking the logic value "1". When one (1) pulse is reduced from the output signal f.sub.o /4 every one minute, the electronic timepiece A becomes slow by 0.176 seconds in a day. The electronic timepiece A becomes slow by 0.352 seconds in a day when the pulse number of the output signal f.sub.o /4 is decreased by two (2) in one minute. In the same manner, when eleven (11) pulses are removed from the output signal f.sub.o /4 in one minute, the electronic timepiece A loses 1.943 seconds in a day.

The pulse number to be added to or substracted from the output signal f.sub.o /4 in every one minute is selectively determined through the use of the switches S.sub.1, S.sub.2, S.sub.3 and S.sub.4 included within the control switches 7. The pulse number is represented in a binary fashion. The switch S.sub.5 functions to determine whether the pulses should be added or subtracted. It will be clear that the indication lamps 13 included within the quartz tester arrangement B correspond to the control switches 7 included within the electronic timepiece A. More particularly, the switches S.sub.1, S.sub.2, S.sub.3, S.sub.4 and S.sub.5 correspond to the lamps L.sub.1, L.sub.2, L.sub.3, L.sub.4 and L.sub.5, respectively. Therefore, a suitable correction value can be selected through the use of the control switches 7 by closing the switches S.sub.1 through S.sub.5 corresponding to the enabled lamps L.sub.1 through L.sub.5.

When, for example, the electronic timepiece A set on the quartz tester arrangement B has the deviation -1.85 seconds/day, the quartz tester 10 detects the deviation -1.85 seconds/day and the output signal 11 of the deviation value detector 11 takes the logical value "1" as will be clear from the TABLE II. The lamps L.sub.1, L.sub.2 and L.sub.4 in the indication lamps 13 are enabled because [1+2+8=11]. The lamp L.sub.5 is also enabled since the deviation takes the negative value and the signal K bears the logic value "1". When the switches S.sub.1, S.sub.2, S.sub.4 and S.sub.5 corresponding to the lamps L.sub.1, L.sub.2, L.sub.4 and L.sub.5 are closed, the detector output signals D.sub.59, D.sub.14, D.sub.28, D.sub.6, D.sub.12, D.sub.18, D.sub.24, D.sub.30, D.sub.36, D.sub.42 and D.sub.48 are applied to the OR gate OR.sub.5 through the switches S.sub.1, S.sub.2 and S.sub.4. These decoder output signals are applied to the gain pulse generator 8 via the AND gate AND.sub.1 since the switch S.sub.5 is closed. The gain pulse generator 8 receives eleven (11) pulses in every one minute, whereby eleven (11) pulses are added to the output signal f.sub.o /4 of the second T-type flip-flop FF.sub.22 in the frequency divider 2 in every one minute. In this manner the electronic timepiece A is made faster by 1.943 seconds in a day. The correction value actually made corresponds to the correction value shown in the TABLE I in the region of the deviation between 1.85 seconds/day and 2.00 seconds/day.

When the electronic timepiece A has the deviation +0.40 seconds/day, the output signal 2 of the deviation value detector 11 takes the logic value "1", and hence only the lamp L.sub.2 is enabled. When the switch S.sub.2 corresponding to the lamp L.sub.2 is closed, the decoder output signals D.sub.14 and D.sub.28 are applied to the lose pulse generator 9 via the OR gate OR.sub.5 and the AND gate AND.sub.2. The lose pulse generator 9 receives two (2) pulses in every one minute, whereby two (2) pulses are subtracted from the output signal f.sub.o /4 in very one minute. In this manner the electronic timepiece A becomes slow by 0.352 seconds in a day.

FIG. 6 shows a typical construction of the control switches 7. In FIG. 6, only one switch is illustrated for the purpose of simplicity.

Wiring patterns 18 and 19 are formed on a circuit board 14 included within the electronic timepiece A such as an electronic wristwatch.

A block 16 having a tapped hole is installed through a hole 15, the tapped hole having a screw 17 therein. When the screw 17 is installed through the tapped hole, the screw head functions to connect the wiring patterns 18 and 19 with each other. When the wiring patterns 18 and 19 are connected with each other, the switch corresponding to the screw 17 is in its closed condition. The installation of the screw 17 is performed at the desired points corresponding to the enabled lamps 13 by opening the rear cover of the electronic wristwatch. Needless to say, five (5) screw portions are formed in such a manner to practice the circuit shown in FIG. 1.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.