US 4,254,462 AGrant
Hardware/Firmware Communication Line Adapter
Issue Date:1981-03-03
•4 Claims
•10 Drawing Sheets
Abstract
A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.
Metadata
Assignee
- Honeywell Information Systems Inc.
Inventors
- James C. Raymond
- Richard A. Lemay
- Richard P. Kelly
Application Information
Application Number:US 9116354
Filing Date:1978-06-01
Priority Date:1978-06-01
Art Unit:237
Classifications
IPC:
G06F 300
Field of Search:
364200 MS File;900 MS File200;900
Patent Drawings (10 sheets)
Description
FIELD OF THE INVENTION
The invention relates to information channel controllers in a computer system, but more directly to communication line adapters for electrically interfacing with a data processing system.
PRIOR ART
Hardware adapters have been used in the communications field to accommodate the transfer of information between a communication transmission line and a data processing system. Changes in communication protocol have placed great demands on the adapters. Such demands have been met by increasing the amount of hardware, thereby increasing manufacturing costs and physical size.
The essence of communication is a concurrent bidirectional transfer of information. Hardware adapters have required two separate systems, one for receive operations and one for transmit operations. It also is recognized that messages may be varying lengths and be comprised of data bytes of varying bit sizes. Hardware has provided a highly limited flexibility at high costs and space sacrifice. The potential for cost effective expansion of hardware functionality is low.
The problems associated with hardware communication adapters have been overcome partially by the advent of communication controllers comprised of hardware and some form of firmware control system. While the duplication of entire systems to accommodate both transmit and receive operations has been obviated, the amount of hardware used is still significant because of an inefficient marriage of firmware and hardware functionalities.
The ineffective marriage of hardware and firmware functionalities also has resulted in a less than achievable capacity for expansion and modification. In addition, information transfer rates have been compromised to an unacceptable degree because of the firmware overhead demands in handling the control and status transfers accompanying a data message. Such overhead demands have been increased by a bit or byte sensitive rather than a message sensitive control architecture.
Unwanted or invalid data messages thus contribute to the overhead requirement to the same degree as valid messages. A further problem encountered with prior systems is the loss of data at the end of a message frame. If a partial data byte is resident in the system at the end of a message frame the system operation terminates when the communication line clock is terminated. The data thereby is lost.
The present invention provides a communication line adapter having a hardware/firmware architecture which exhibits a substantially improved potential for functionality expansion and flexibility. Neither the manufacturing costs nor size obstacles of prior systems are incurred. In addition, the concurrent bidirectional transfer of data messages having varying lengths and byte sizes is accommodated with a reduced firmware overhead. Transfer rates are not substantially affected.
SUMMARY OF THE INVENTION
The invention is directed to a hardware/firmware communication line control system for accommodating the concurrent bi-directional transfer of data messages of varying lengths. The system architecture readily accommodates an expansion of capacity and exhibits a dynamic flexibility.
More particuarly, in response to commands from a communications processor, the control system enters into either a receive mode or a transmit mode for transferring data messages between the communications processor and a communication channel. Data transfers occur under the control of a firmware control system acting in concert with a microprocessor to assemble and disassemble whole or partial data bytes of varying bit sizes. Those systems which use general purpose microprocessors also limit a system's capacity to that of the microprocessor. Only data bytes having the microprocessor byte size or less may be accommodated.
The firmware control system and microprocessor further interact to modify the firmware microinstruction set in response to changing conditions, thereby enhancing system flexibility.
Bit sequences in the data flow are sensed to detect the occurrence of data message frames and end-of-frame conditions. Valid data is distinguished from invalid data, and the data flow is resynchronized to the beginning of a frame in the event a data message is invalid or otherwise unwanted.
In the event that partial data bytes are present in the communication line control system when an end of message frame is detected, the data transfer continues without benefit of communication line transmit or receive clock signals.
The architecture of the system readily accommodates the modular expansion of system capacity by the mere combination of microprocessor chips.
DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and for further objects and advantages thereof, reference may now be had to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a functional block diagram of a system within which the invention may operate; and
FIGS. 2a-2e are detailed electrical schematics of the invention.
FIG. 1
FIG. 1 illustrates in functional block diagram form a computer system having a multiline communications processor (MLCP) 10 in electrical communication with a central processor unit 11 and a main memory unit 12 by way of a common communication bus hereinafter referred to as megabus 13.
The megabus 13 provides an information path between any two units in the system. The paths are asynchronous in design, thereby enabling units of various speeds to operate efficiently. The bus accommodates information transfers including communication requests, control commands, status signals and data transfers between main memory unit 12 and MLCP 10.
Any system unit requiring communication with any other system unit issues a bus cycle request. When the bus cycle is granted, the requesting unit becomes the master and the addressed system unit becomes the slave. Some bus interchanges require a response cycle as well as a request cycle. By way of example, the master unit may identify itself to a slave unit and indicate that a response is required. When the required information becomes available, the slave assumes the role of master and initiates a transfer to the requesting unit. A more detailed background description of the megabus system of FIG. 1 is given in U.S. Pat. No. 3,993,981 which is assigned to the assignee of the present invention, and which is incorporated by reference herein.
In the servicing of bus cycle requests, the central processor has the lowest priority, the MLCP 10 has the next to the lowest priority, and the memory unit 12 has the highest priority.
The MLCP 10 further communicates with a high level data link control communications line adapter (HCLA) 14 and other communication adapters 15. The HCLA in turn may be directly connected to data processing equipment such as a CPU, or to any type of data terminal equipment (DTE). In a remote connect mode, the HCLA may be connected by way of a local data communications equipment unit (DCE) 16 and a communications cable 17 to a remote DCE 18. The remote DCE 18 in turn may be connected to a remote DTE 19. The DCEs have a capacity to both modulate and demodulate binary information streams, and thus may either receive or transmit information.
The HCLA 14 in which the present invention is embodied may be used to interface with communications lines such as a line 20 operating at synchronous rates up to 20,000 bits per second. The HCLA may be made compatible with any DCE interface type conforming to the well known EIARS-232C, MIL 188-C or RSXYZ standards merely by changing DCE line driver/receiver circuitry. The preferred embodiment of the invention as described herein is compatible with the EIARS-232C interface standard.
FIGS. 2a-2e
FIGS. 2a-2e illustrate in electrical schematic form the HCLA 14 of FIG. 1.
In referring to the electrical schematics illustrated in the Figures, it is to be understood that the occurrence of a small circle at the input of a logic device indicates that the input is enabled by a logic zero. Further, a circle appearing at an output of a logic device indicates that when the logic conditions for that particular device are satisfied, the output will be a logic zero.
The MLCP 10 supplies a first address signal to a control line 20 leading to the B3 input of an MLCP command decoder 21, a second address signal to a control line 22 leading to the A1 input of the decoder 21, and a third address signal 23 leading to the A3 input of the decoder. The MLCP 10 also supplies a control signal on a control line 24 leading to the B1 input of the decoder, and a second control signal on a control line 25 leading to the B2 input of the decoder. The A2 input to the decoder is connected to ground.
The decoder 21 decodes the logical AND of inputs A1-A3, and the B1-B3 inputs to provide control signals for the operation of the logic system of FIGS. 2a-2d to control the interface between the MLCP 10 and HCLA 14. The decoder 21 is of a 74LS138 type manufactured and sold by Texas Instruments Incorporated of Dallas, Texas.
The D0 output of the decoder is connected to the L2 input of a 4.times.4 bit tri-state RAM (random access memory) 26. The D1 output of the decoder is connected to one input of an AND gate 27. The D2 output of the decoder is connected to one input of an AND gate 28 and to one input of a NAND gate 29. The D3 output of the decoder 21 is connected to the L1 load input of RAM 26 and to the L1 input of a 4.times.4 bit tri-state RAM 30. The D3 output also is applied through an inverter 31 to the K input of a J-K flip-flop 32.
The D4 output of decoder 21 is applied to the L2 input of RAM 30, and the D5 output of the decoder is applied to a second input of gate 27. The D6 output of decoder 21 is applied to a second input of gate 28 and to one input of a NAND gate 33. The D7 output of decoder 21 is applied to the SEL 1 select input of a 4.times.4 bit tri-state RAM 34, and to the output enable input (F) of the RAM 34. The D7 output of decoder 21 further is connected to the SEL 1 input of a 4.times.4 bit tri-state RAM 35, to one input of an AND gate 36, and through an inverter 37 to the J input of J-K flip-flop 38. The RAMs 26, 30, 34 and 35 are of the TI74LS670 type RAMs manufactured and sold by the Texas Instruments Corporation of Dallas, Texas.
The MLCP 10 further supplies an eight bit byte of data to the RAMs 26 and 30. More particularly, bits 0-3 of the data byte are applied to the A1-A4 inputs of RAM 26, respectively, and bits 4-7 of the data byte are applied to the A1-A4 inputs of RAM 30. The D1 output of RAM 26 is applied to a data line 39, the D2 output to a data line 40, the D3 output to a data line 41 and the D4 output to a data line 42. The D1 output of RAM 30 is applied to a data line 43, the D2 output to a data line 44, the D3 output to a data line 45 and the D4 output to a data line 46.
The control store memory of the HCLA 14, which is to be further described, supplies a binary encoded two-bit word to control lines 47 and 48 respectively leading to the SEL 1 and SEL 2 inputs of RAMs 26 and 30. The control line 48 also is connected to the L2 inputs of RAMs 34 and 35. The control store memory further supplies output enable signals to a control line 49 leading to the F input of RAM 26, and to a control line 50 leading to the F input of RAM 30. The clock inputs to RAMs 26 and 30 are supplied by way of a control line 51 leading to the output of an inverter 52. The control store memory also supplies a load signal to a control line 53 leading to the L1 input of RAM 34, and a load signal to a control line 55 leading to the L1 input of RAM 35.
The clock input to RAM 34 is connected to the clock input of RAM 35 and to the output of an OR gate 56. The SEL 2 input to RAM 34 is connected to the SEL 2 input to RAM 35 and to the output of gate 28. The A1-A4 inputs to RAMs 34 and 35 are connected to data lines 57-60, respectively. The D1-D4 outputs of RAM 34 are applied to data lines 61-64, respectively. The D1-D4 outputs of RAM 35 are applied to the date lines 65-68, respectively. The F input to RAM 35 is connected to the outut of gate 36.
The MLCP 10 supplies a master clear signal to a control line 69, and through an inverter 60 to the reset input of flip-flop 32. A strobe signal supplied by the MLCP 10 is applied by way of a control line 71 through an inverter 72 to the clock input of flip-flop 32. The output of inverter 72 further is applied through inverter 52 to one input of a NAND gate 73, a second input of which is connected to the output of gate 27. The output of gate 73 is applied to a control line 74.
The MLCP 10 also supplies a system clock having a clock rate of the order of 4.0 MHz on control line 75, and through an inverter 76 to one input of gate 56. A second input to gate 56 is connected to a control line 77. The output of inverter 76 also is applied through an inverter 78 and an inverter 79 to a control line 80.
The K input to flip-flop 32 is connected to the output of inverter 31, and the J input to the flip-flop is connected to ground. The set input to the flip-flop is connected to a control line 100. The Q output of the flip-flop 32 is connected to a control line 82, and the Q output of the flip-flop is connected to a control line 81. The set input to flip-flop 38 is connected to a control line 83, and the J input to the flip-flop is connected to the output of inverter 37. The clock and K inputs to the flip-flop 38 are connected to ground, and the reset input is connected to a control line 84. The Q output of flip-flop 38 is applied to a control line 85 leading to one input of an OR gate 86, and the Q output of the flip-flop is connected to the reset input of a J-K flip-flop 87.
The set and clock inputs to flip-flop 87 are connected to the set and clock inputs of a J-K flip-flop 88, and to a control line 89. The J input to flip-flop 87 is connected to the output of an inverter 90, the input of which is connected to a control line 91. The K input to flip-flop 87 is connected to the output of gate 33, a second input of which is connected to a second input of gate 29 and to a control line 92. The Q output of flip-flop 87 is applied to a control line 93, and the Q output of the flip-flop is applied to a second input of gate 86. The output of gate 86 is connected to a control line 94.
The J input to flip-flop 88 is connected to the output of an inverter 95, the input of which is connected to a control line 96. The K input to the flip-flop is connected to the output of gate 29, and the reset input to the flip-flop is connected by way of a control line 102 to one input of a NAND gate 97, the output of which is applied to a control line 98. The Q output of flip-flop 88 is applied to the second input of gate 97, and the Q output of the flip-flop is applied to a control line 99. The reset input to flip-flop 88 also is connected to a control line 100.
Referring to FIG. 2b, a microprocessor 110 having a four-bit data input, two four-bit RAM addres inputs and a nine-bit instruction input is illustrated, The carry-in (CN) input to the microprocessor is connected to control line 101. The data inputs DA1-DA4 are connected respectively to data lines 111-114. The RAM A address input RA1 is connected to line 55, and the RA2 input is connected to line 53. The RA3 input is connected to line 47, and the RA4 input is connected to line 48.
The RAM B address input RB1 is connected to an address line 115, and the RB2 input is connected to an address line 116. The RB3 input to microprocessor 110 is connected to an address line 117, and the RB4 input is connected to an address line 118. The instruction input IN0 to microprocessor 110 in connected to a control line 119, and the IN1 input is connected to a control line 120. The IN2 input to microprocessor 110 is connected to a control line 121, the IN3 input to control line 122, the IN4 input to control line 123 and the IN5 input to a control line 124. The IN6 input is connected to ground and the IN7 input is connected to a control line 125. The IN8 input is connected to a control line 126.
The S1, S2 and S4 bidirectional input/outputs to the microprocess 110 provide a data bit input with shift register capability. More particularly, when a data bit is supplied to the S2 input by way of example, a specific instruction code at the In0-IN8 inputs shifts the data bit one position to the right. The S2 input to the microprocessor 110 is connected to the output of a driver 127, one input of which is connected to a data line 128. The output enable input F of the driver 127 is connected to a control line 129.
The D1-D4 outputs of microprocessor 110 are applied respectively to lines 130-133 leading to data inputs of a 16.times.4 bit RAM 134, and to lines 60, 59, 58 and 57 of FIG. 2a. More particularly, line 130 leads to the A4 input to RAM 134, the line 131 is connected to the A3 input to the RAM, the line 132 to the A2 input, and the line 133 to the A1 input.
The microprocessor 110 is of a type manufactured and sold by Advanced Micro Devices Incorporated in Sunnyvale, Calif. as the AM 2901 microprocessor. In normal operation, the microprocessor 110 receives an instruction at the IN0-IN8 inputs which may require manipulation of operands addressed by the RA1-RA4 and RB1-RB4 inputs, or a manipulation of data received at the DA1-DA4 inputs. The results of the manipulation is provided at the D1-D4 outputs. In addition, if the result is a logic zero, a logic one level appears at the D0 output of the microprocessor which is applied to a data line 135 leading to the inputs of a NOR gate 136 and also to a 1.0 K ohm resistor to +5V. The D0 koutput also is applied through a 1.0 K ohm resistor 103 to a +5.0 volt source 104. The output of gate 136 is applied to the A6 input of an eight-to-one multiplexer 137.
the SEL 1, SEL 2 and SEL 3 inputs to the multiplexer 137 are connected to control lines 138-140, respectively. The enable output (EN) input to the multiplexer 137 is connected to the D3 output of an instruction decoder 141. The A0 input to the multiplexer is connected to the control line 81, and the A1 input is connected by way of a control line 142 to the Q output of flip-flop 38 of FIG. 2a. The A2 input to multiplexer 137 is connected by way of a control line 143 to the Q output of flip-flop 88 of FIG. 2a, and the A3 input to the multiplexer is connected to the line 93. The A4-A5 inputs to the multiplexer 137 are connected to lines 144 and 145, respectively. The A7 input to the multiplexer is connected to the output of a NOR gate 146, one input of which is connected to a control line 147. A second input to gate 146 is connected to a control line 148.
The D0 output of multiplexer 137 is applied to the D input of a D-type flip-flop 149. The set and reset inputs to the flip-flop are each connected to control line 89 and to the A1 input of decoder 141. The clock input to the flip-flop is connected to control line 80, and the Q output of the flip-flop is connected to A2 and A3 inputs of decoder 141.
The B1-B3 inputs to the decoder 141 are connected to control lines 150-152, respectively. The D0 output of decoder 141 is connected to one input of an AND gate 153, the output of which is connected to the A2 input of a decoder 154. The D1 output of decoder 141 is connected to one input of an OR gate 155, a second input of which is connected by way of a control line 156 to the output of inverter 76 of FIG. 2a. The output of gate 155 is connected to the write enable (WE) input of RAM 134. The D2 output of decoder 141 is connected to control line 77, and the D4 output is connected to a control line 157. The D5 output of the decoder is connected to a control line 158, and the D6 output is connected to a control line 159. The D7 output of decoder 141 is connected to a second input of gate 153.
The decoders 141 and 154 are of a 74S138 type manufactured and sold by Texas Instruments Incorporated of Dallas, Texas.
The A1 input to decoder 154 is connected by way of a control line 160 to the output of inverter 78 of FIG. 2a, and the A3 input of the decoder is conected to a control line 161. The B1-B3 inputs of decoder 154 are connected to control lines 138-140, respectively. The D0 output of decoder 154 is connected to control line 71, the D1 input to control line 84, the D2 input to control 96 and the D3 input to control line 91. The D4-D6 outputs of decoder 154 are connected to control lines 162-164, respectively.
the SEL 1-SEL 4 inputs to RAM 134 are connected respectively to control lines 55, 53, 47 and 48. The output enable (F) input to RAM 134 is connected to a control line 165, and the D1-D4 outputs of the RAM are connected respectively to control lines 166-169.
Referring to FIG. 2c, four-bit counters 175-177 are configured to provide a ten bit address counter. The clock inputs to each of the counters is connected to control line 80 leading to the output of inverter 79 of FIG. 2a. The CI1 and CI2 carry-in inputs of counter 175 are connected to the increment (INC) inputs to counters 175-177, and connected by way of a control line 178 to the D7 output of decoder 141 of FIG. 2b. The reset input to counter 175 is connected to the reset inputs of counters 176 and 177, and by way of a control line 179 to the output of inverter 70 of FIG. 2a. The A1 input to counter 175 is connected by way of the control line 121 to the D1 output of a programmable read only memory (PROM) 180. The A2 input to counter 175 is connected by way of control line 122 to the D2 output of PROM 180, and the A3 input of the counter is connected by way of control line 123 of the D3 output of the PROM. The A4 input to counter 175 is connected by way of control line 124 to the D4 output of PROM 180.
The D1 output of counter 175 is applied to the A1 address inputs of PROMs 180-186. The D2 output of counter 175 is applied to the A2 inputs of PROMs 180-186, and the D3 output of the counter is applied to the A3 inputs of the PROMs. The D4 output of counter 175 is applied to the A4 input of the PROMs, and the carry out (CO) output of the counter is connected to the CI1 and CI2 carry-in inputs of counter 176.
The A1-A4 inputs to counter 176 are connected to control lines 115-118, and the D1 output of the counter is connected to the A5 inputs of PROMs 180-186. The D2 output of counter 176 is connected to the A6 inputs to the PROMs, and the D3 output of the counter is connected to the A7 inputs of the PROMs. The D4 output of counter 176 is connected to the A8 inputs of the PROMs, and the CO output of the counter 176 is connected to the CI1 and CI2 inputs of counter 177.
The A1 input to counter 177 is connected by way of control line 55 to the D1 output of PROM 185. The A2 input to counter 177 is connected by way of control line 53 to the D2 output of PROM 185. The D1 output of counter 177 is connected to the A9 inputs of PROMs 180-186, and the D2 output of the counter is connected to the A10 inputs of the PROMs.
The EN1 and EN2 enable inputs to PROMs 180-183, 185 and 186 are connected to ground. The EN1 input to PROM 184 also is connected to ground, but the EN2 input to the PROM is connected to the output of a NOR gate 187 having one input connected to control line 158 leading to the D5 output of decoder 141 of FIG. 2b. The second input to gate 187 is connected to control line 165 leading to the D3 output of PROM 182.
The D1 output of PROM 183 is connected to line 101.
The D2-D4 outputs of PROM 183 are applied by way of control lines 150-152 to the B1-B3 inputs respectively of decoder 141 of FIG. 2b. The D1-D4 outputs of PROM 184 are connected respectively to control lines 188-191, and the D3 and D4 outputs of PROM 185 are connected respectively to control lines 47 and 48. The D1 output of PROM 181 is connected to control line 125, and the D2 output is connected to control line 126. The control lines 125 and 126 lead to the IN7 and IN8 inputs of microprocessor 110 of FIG. 2b. The D3 and D4 outputs of PROM 181 are applied respectively to control lines 119 and 120 leading to the IN0 and IN1 inputs of the microprocessor 110.
Each of the PROMs 180-186 are 1024.times.4 bit tri-state PROMs having the firmware program of Appendix A stored therein. In response to the address signals supplied by the counters 175-177, internal RAM address signals and microinstructions are supplied by the firmware program of PROMs 180-186 to the microprocessor 110.
Referring to FIG. 2d, a local DCE such as DCE 16 of FIG. 1 supplies a transmit clock signal by way of a control line 200 and a receiver 201 to the A2 input of a four-stage two-to-one multiplexer 202. The DCE further supplies a receive clock signal by way of a control line 203 and a receiver 204 to the B2 input of the multiplexer 202. The DCE also supplies a serial data bit stream by way of a control line 205 and a receiver 206 to the C2 input of multiplexer 202.
The SEL select input of the multiplexer 202 is supplied by the Q output of a D-type flip-flop 207, and the output enable input (F) of the multiplexer is connected to ground. TJhe A1 and B1 inputs of the multiplexer are connected to a control line 208 leading to the MLCP 10. The C1 input to multiplexer 202 is connected to the Q output of a D-type flip-flop 209, and the D1 input to the multiplexer is connected to ground. The D2 input to the multiplexer 202 is connected to the Q output of flip-flop 209.
The A0 output of multiplexer 202 is applied to the clock input of flip-flop 209 and to the clock input of a D-type flip-flop 210. The B0 output of multiplexer 202 is applied through an inverter 211 to the clock inputs of a D-type flip-flop 212 and a D-type flip-flop 213. The CO output of multiplexer 202 is connected to the D input of flip-flop 212, and the CO output of the multiplexer is connected to two logically ANDed inputs of a driver 214. The output of driver 214 is applied to a data line 215 leading to the DCE 16 of FIG. 1.
The local DCE 16 supplies status signals by way of control lines 216-219, which are applied through receivers 220-223 to the inputs of tri-state drivers 224-227. More particularly, a data set ready status signal is supplied by the DCE to control line 216, and a clear to send signal is supplied to control line 217 in response to a request from the HCLA 14 to transfer data to the DCE. The local DCE 16 also supplies a carrier detected signal on line 218 to indicate that a communication from the remote DCE 18 has been detected. The DCE 16 also supplies a ring indicator signal on line 219 to indicate that the remote DCE 18 has alerted the local DCE 16 that a communication is forthcoming.
The output enable input (F) of the drivers 224-227 are each connected to control line 28a leading to the output of gate 28 of FIG. 2a, and the output of the drivers 224-227 respectively are applied to control lines 229-232 leading to the MLCP 10.
The reset and set inputs to flip-flop 212 are connected through a 1.0 K ohm resistor 233 to control line 135 leading to the +5.0 volt source 104. The Q output of flip-flop 212 is applied to a data line 234, and the Q output of the flip-flop is connected to data line 128 leading to driver 127 of FIG. 2b.
The reset input to flip-flop 213 is connected to control line 163 leding to the D5 output of decoder 154 of FIG. 2b. The D input to the flip-flop is connected to ground, and the set input is connected to a control line 235 leading to the output of inverter 70 of FIG. 2a. The set input of the flip-flop further is connected to the set input of flip-flop 210, to the set input of flip-flop 209, to the set input of a D-type flip-flop 236, to the reset input of a D-type flip-flop 237, and to the reset input of a D-type flip-flop 238. The set input to flip-flop 213 also is connected to the set input of flip-flop 207, to the reset input of a D-type flip-flop 239, to the reset input of a D-type flip-flop 240, the reset input of a D-type flip-flop 241, to the reset input of a D-type flip-flop 242 and to the reset input of a D-type flip-flop 243.
The reset input to flip-flop 210 is connected to control line 162 leading to the D4 output of decoder 154 of FIG. 2b, and the D input to the flip-flop is connected to ground. The Q output of flip-flop 210 is supplied to control line 144 leading to the A4 input of multiplexer 137 of FIG. 2b.
The D input to flip-flop 209 is connected to the Q output of flip-flop 236. The reset input to flip-flop 209 is connected to the reset input of flip-flop 236, and to a control line 244 leading through a 1.0 K ohm resistor 195 to +5.0 volt source 104. The Q output of flip-flop 209 is applied to the D2 input of multiplexer 202, and the Q output of the flip-flop is applied to the C1 input of multiplexer 202.
The D input to flip-flop 236 is connected to control line 130 leading to the D1 output of microprocessor 110 of FIG. 2b, and the clock input to the flip-flop is connected to control line 164 leading to the D6 output of decoder 154.
The clock inputs to flip-flops 237-243 and 207 are connected to control line 74 leading to the output of NAND gate 73 of FIG. 2a. The MLCP 10 supplies an eight-bit data byte by way of data lines 245-252 with the least bit applied to line 245 and the most significant bit applied to line 252. Line 245 is connected to the D input of flip-flop 243, line 246 to the D input of flip-flop 242, line 247 to the D input of flip-flop 241 and line 248 to the D input of flip-flop 240. Line 249 is connected to the D input of flip-flop 239, and line 250 is connected by way of an inverter to the D input of flip-flop 207. Line 251 is connected to the D input of flip-flop 238 and line 252 is connected to the D input of flip-flop 237.
The Q output of flip-flop 237 is applied to line 102 leading to the reset input of flip-flop 88 of FIG. 2a, and the Q output of flip-flop 238 is applied by way of control line 83 to the set input of flip-flop 38 of FIG. 2a. The Q output of flip-flop 239 is applied to one input of a NAND gate 253, a second input of which is supplied by the MLCP 10 on a control line 254. The output of gate 253 is supplied to one input of a driver 255 and to one input of a driver 256.
A second input to driver 255 is connected to the Q output of flip-flop 240, and the output of driver 255 is applied to a control line 257 leading to the local DCE 16. A second input to driver 256 is connected to the Q output of flip-flop 241, and the output of the driver is applied to a control line 258 leading to the local DCE 16.
The Q output of flip-flop 242 is applied to each of two logically OR'd inputs of a driver 259, the output of which is applied to a control line 260 leading to the local DCE 16. The Q output of flip-flop 243 is applied to the input of a driver 261, the output of which is connected to a control line 262 leading to the DCE 16.
The flip-flop 239 is a direct connect mode flip-flop for providing a clock signal to the DCE 16 in an environment where no transmit or receive clock is otherwise provided. Flip-flop 207 specifies an internal loop test mode, but for normal operation is reset. The test mode signal controls the selection of the multiplexer 202. More particularly, the test mode signal at the Q output of flip-flop 207 selects multiplexer 202 to the A1-D1 inputs when low, and to the A2-D2 inputs when high. In either a transmit or receive mode, the multiplexer is selected to the A2-D2 inputs. When the Q of flip-flop 207 is at a logic one level. The transmit and receive clocks thereby are selected from the DCE 16, and the receive data is taken from the DCE. In addition, the transmit data to the DCE during a transmit operation is taken from the Q output of flip-flop 209.
In a test mode, the A1-D1 inputs to the multiplexer 202 are selected, and both the transmit and receive clocks are taken from a clock source supplied by the MLCP 10 on line 208. The receive data bit is taken from the Q output of flip-flop 209 and the transmit data bit to the DCE 16 is held at a low state at the output of driver 214.
It is to be understood that the transmit and receive clock signals supplied by the MLCP 10 and DCE 16 in the preferred embodiment of HCLA 14, as illustrated in FIGS. 2a-2e, may have clock rates up to 20 KHz.
When the MLCP 10 is reading status information from the HCLA 14, logic bit signals received on lines 216-219 from the DCE 16 are supplied respectively by way of receivers 220-223 through tri-state drivers 224-227. When the drivers 224-227 are enabled by the read status signal supplied by the MLCP 10 on line 228, the driver outputs surplant the D1-D4 outputs of RAM 34 to provide DCE status information to the MLCP 10. The D1-D4 outputs of RAM 35 provide HCLA status information to the MLCP.
Referring to FIG. 2e, the D1 output of RAM 26 on line 29 and the D1 output of RAM 30 on line 43 are applied to one input of a tri-state node 270, the output of which is applied by way of a data line 271 to lines 114 and 140 of FIG. 2b. The D1 output of RAM 134 on line 166 and the D4 output of PROM 184 on line 191 are connected to a second input of node 270.
The D2 output of RAM 26 on line 40 and the D2 output of RAM 30 on line 44 are connected to one input of a tri-state node 272, the output of which is applied to a data line 273 leading to lines 113 and 139 of FIG. 2b. The D2 output of RAM 184 on line 190 are connected to a second input of node 273.
The D3 output of RAM 26 on line 41 and the D3 output of RAM 30 on line 45 are connected to one input of a tri-state node 274, the output of which is applied to a data line 275 leading to lines 112 and 138 of FIG. 2b. The D3 output of RAM 134 on line 168 and the D2 output of PROM 184 on line 189 also are connected to a second input of node 274.
The D4 output of RAM 26 on line 42 and the D4 output of RAM 30 on line 46 are applied to an input of a tri-state node 276, the output of which is applied to a data line 277 leading to lines 111 and 161 of FIG. 2b. The D4 output of RAM 134 on line 169 and the D1 output of PROM 184 on line 188 are applied to a second input of node 276.
The D1 output of RAM 34 on line 61 and the output of driver 224 on line 229 are connected respectively to the inputs of a tri-state node 278. The output of node 278 is applied to a data line 279 leading to the MLCP 10.
The D2 output of RAM 34 on line 62 and the output of driver 225 on line 230 are connected respectively to the inputs of a tri-state node 280. The output of node 280 is applied to a data line 281 leading to the MLCP 10.
The D3 output of RAM 34 on line 63 and the output of driver 226 on line 231 are connected respectively to the inputs of a tri-state node 282. The output of node 282 is applied to a data line 283 leading to the MLCP 10.
The D4 output of RAM 34 on line 64 and the output of driver 227 on line 232 are connected respectively to the inputs of a tri-state node 284. The output of node 284 is applied to a data line 285 leading to the MLCP 10.
OPERATION
Transmit and receive operations can occur simultaneously within the HCLA 14. A transmit operation is the process wherein the MLCP 10 transfers data in parallel to the HCLA 14. The data is then shifted serially out of the HCLA 14 to the DCE 16 under control of a DCE transmit clock. In support of this transmit operation, the MLCP 10 supplies control information to the HCLA, and receives status information from the HCLA.
A receive operation is the process wherein data from the DCE 16 is shifted serially into the HCLA 14 under the control of a DCE receive clock. The serial data stream is assembled into data bytes, and then transferred in parallel to the MLCP 10 under MLCP control. In support of this receive operation, the MLCP 10 supplies control information to the HCLA, and receives status information from the HCLA.
When the HCLA has a requirement for transmit data, status or control information, and simultaneously receive data, status or control information, the HCLA alternates the generation of transmit and receive service interrupts to the MLCP.
In operation, the HCLA 14 may enter into either or both a transmit mode and a receive mode, or a test mode. If data is to be transitted from the HCLA 14 to the DCE 16, the MLCP 10 issues a logic one signal to line 69 to reset flip-flop 32 of FIG. 2a, and reset flip-flops 237-243 of FIG. 2d. The logic one signal on line 69 further is applied through inverter 70 of FIG. 2a to set flip-flops 207, 209, 210, 213 and 236 of FIG. 2d. The Q output of flip-flop 207 thereby transitions to a logic zero to select the multiplexer 202 to the A1-D1 inputs.
The MLCP 10 also supplies binary data to the A1-A4 inputs of RAMs 26 and 30, and logic signals to the A1, A3, and B1-B3 inputs to the command decoder 21. The A1-A3 inputs of the decoder are logically ANDed to enable the decoder, and the B1-B3 inputs are decoded to provide commands at the D0-D7 outputs. If the D3 output of decoder 21 is at a logic zero level, four bits of data are loaded into RAM 26 and four bits of data are loaded into RAM 30 when the MLCP 10 issues a logic zero signal to line 71. In addition, a logic one is applied by way of inverter 31 to the CK input of flip-flop 32 to reset the flip-flop. The Q output of the flip-flop thereupon transitions to a logic zero level to indicate to the firmware that a data byte has been stored in RAMs 26 and 30. More particularly, the logic AND nodes 270, 272, 274 and 276 are controlled by the PROM 184 to select the multiplexer 137 to its A0 input which is applied to the D input of flip-flop 149. This occurs when counters 175-177 address a TAMN instruction in PROMs 180-186 as indicated at location 58000 in the firmware program of Appendix A. Upon the occurrence of a next positive edge of the system clock supplied by the MLCP 10 on line 80, flip-flop 149 is controlled to reflect the set or reset condition of the A0 input to multiplexer 137. Upon the execution of a next instruction, decoder 141 is enabled or inhibited by the Q output of flip-flop 149 to determine whether the instruction is to be executed normally, or modified. If the Q output is at a logic zero level, the instruction shall be executed normally. If the Q output is at a logic one level, however, the instruction shall be modified or skipped. For example, if the instruction succeeding the TAMN instruction is a branch instruction (e.g., location 58100) and the Q output of flip-flop 149 is at a logic zero level, the counters 175-177 shall be loaded in response to a logic zero at the D7 output of decoder 141 with the address provided by the succeeding instruction as indicated at the D2 and D1 outputs of PROM 185, the D1-D4 outputs of PROM 186 and the D1-D4 outputs of PROM 180. If the Q output of flip-flop 149 is at a logic one level, however, the D7 output of decoder 141 transitions to a logic one level. The counters 175-177 thereupon shall increment to a next location 58600 in the firmware program without executing the branch instruction. In this manner, the microprogram continues at a location determined by the tested condition. A total of eight functions may be tested in this manner through the facility of multiplexer 137.
The MLCP 10 prepares to send data by applying a command word to decoder 21 to provide a logic zero at the D1 output, thereby supplying a logic zero at one input of NAND gate 73. The MLCP 10 further supplies a logic zero strobe signal to line 71 to cause control line 74 to transition to a logic one level and clock flip-flops 207 and 237-243. By controlling the data lines 245-252, the MLCP controls the state of flip-flops 207 and 237-243.
For the purpose of sending data, the MLCP 10 sets the Q outputs of flip-flops 237, 242, 243 and resets the Q output of flip-flop 207 by setting data ines 252, 246, 245 and 250 while supplying a clock to control line 74 in the manner previously described.
When the flip-flop 242 is set, a request to send control line 260 transitions to a logic one level to signal the DCE 16. The firmware control system waits for a logic one level on line 267 before requesting data from the MLCP 10. The flip-flop 207 is reset to select the multiplexer 202 of FIG. 2d to its A2-D2 inputs.
Flip-flop 237 raises control line 98 of FIG. 2a to a logic one state. When the flip-flop 88 is set by a firmware signal on line 96, the control line 98 transitions to a logic zero level to signal the MLCP 10 for a next data byte. When data is requested from the MLCP 10, the firmware control system sets the flip-flop 32.
Before a message transmission or reception can begin, the MLCP 10 must supply a DCE control word to flip-flops 207 and 237-243. The MLCP 10 applies a code word to the decoder 21, thereby causing either the D1 or D5 outputs of the decoder to transition to a logic zero level. The MLCP further supplies a logic zero strobe to line 71 to provide a load signal on line 74 leading to the clock inputs of flip-flops 207 and 237-243 of FIG. 2d. The MLCP data on lines 245-252 thereupon is loaded into the flip-flops.
Bits .phi.-3 on lines 245-248, respectively, provide control information to the DCE by way of drivers 255, 256, 259 and 261. Bit 4 stored in flip-flop 239 indicates whether a direct connect mode is in effect wherein a data transfer clock signal is supplied by the MLCP 10 rather than the DCE 16. Bit 5 stored in flip-flop 207 indicates whether a test mode is in effect. In a transmit or receive operation, the flip-flop must be reset to select the multiplexer 202 to the A2-D2 inputs. MLCP data bits 6 and 7 stored in flip-flops 238 and 237, respectively, determine whether a transmit or a receive operation shall be enabled. It is to be understood that both operations may be enabled simultaneously during a full duplex operation.
During a transfer of transmit control information from the MLCP 10 to the HCLA 14, the MLCP applies a command word to the decoder 21 to cause the DO output of the decoder to transition to a logic zero level. A four bit transmit control byte from the MLCP thereupon is loaded into the RAM 26. Of the four bits, bits 0, 1 and 2 indicate the byte size of the information and bit 3 indicates the occurrence of a last byte of a message to be transmitted.
The firmware control system senses the transmit control byte by applying select control signals and an output enable signal to the RAM 26. The transmit control word thereby is applied to lines 39-42 leading through tri-state nodes 270, 272, 274 and 276 to the DA1-DA4 inputs to the microprocessor 110. The ALU operations within the microprocessor 110 and the multiplexer 137 then are used as before described to accommodate the application of the transmit control word by the firmware control system.
In transferring information through the HCLA 14, the firmware control system of PROMs 180-186 must determine whether a new transmit bit is available for transfer to the DCE 16. This determination is accomplished by sensing the Q output of flip-flop 210 of FIG. 2d. More particularly, the firmware control system selects the multiplexer 137 to its A4 input, which is applied by way of flip-flop 141. Whenever a next bit is ready for transfer as indicated by the A4 input to multiplexer 137 being at a logic zero level, the D1 output of decoder 141 is enabled and applied through OR gate 155 to disable the WE (write enable) input of RAM 134. The firmware control system further supplies select control signals to the SEL 1-SEL 4 inputs to RAM 134 to select one of sixteen four bit words stored in RAM 134, and enables the four bit output of RAM 134 by issuing a logic zero signal to line 165. In response thereto, the output of RAM 134 is applied to lines 166-169 leading to nodes 270, 272, 274 and 276, respectively. The four-bit output of the nodes is applied to the DA1- DA4 inputs of microprocessor 110, and operated upon in accordance with a TAMN instruction supplied by the firmware control system to the IN0-IN8 inputs of the micro processor. The result of the operation is indicated at the D0 output of the microprocessor, and applied through NOR gate 136 to the A6 input of multiplexer 134. The multiplexer is selected to its A6 input as before described to cause new commands to issue from decoders 141 and 154. In response thereto, a reset transmit ready signal is generated at the D4 output of decoder 154 to reset the flip-flop 210 of FIG. 2d.
When the multiplexer 202 of FIG. 2d is selected to its A2-D2 inputs during a transmit mode as before described, a transmit clock signal having a clock rate up to 20.0 KHz is supplied by the local DCE 16 to the A2 input of the multiplexer by way of receiver 201. The clock signal is applied to the clock inputs of flip-flops 209 and 210. Upon each positive going slope of the transmit clock signal, the flip-flop 210 is set and the microprocessor 110 under firmware control senses the output of the flip-flop by selecting the multiplexer 137 as before described. If the flop is set, the firmware branches to a transmit update routine and the decoder 154 issues a reset signal to reset the flop 210. This operation occurs periodically in accordance with the positive going slopes of the DCE transmit clock signal.
During a transmit operation, the data in the RAMs 26 and 30 is fed four bits at a time under firmware control through the AND nodes 270, 272, 274 and 276 of FIG. 2e to the DA1-DA4 inputs of microprocessor 110. More particularly, the firmware control system issues control signals to the SEL 1 and SEL 2 input of RAMs 126 and 30 to alternatively address RAM 26 and RAM 30 data locations to be read. The firmware control system further issues logic zero signals to the F inputs of the RAMs to enable the RAM outputs. When the RAMs 26 and 30 become empty of data during a transmit operation, a logic zero strobe is generated at the D0 output of decoder 154 in response to control signals from the firmware control system. The flip-flop 32 of FIG. 2a thereby is set to indicate that the data locations within the RAMs 26 and 30 are empty.
The firmware control system also generates a second logic zero strobe at the D2 output of decoder 154 which is applied to theCj-input of the flip-flop 88 to set the flip-flop, and thereby signal the MLCP that additional data may be transmitted. The set condition is applied through the AND gate 97 to the MLCP 10 only if the MLCP 10 has loaded the DCE control register comprised of flip-flops 207 and 237-243. Before this occurs, a status condition is loaded from the microprocessor 110 into RAM 35 under firmware control. More particularly, the firmware control system issues control signals to lines 48 and 55 leading to the L2 and L1 inputs of RAM 35, respectively, to select an address for a write operation. When a logic zero clock pulse issues from gate 56, microprocessor 110 status information is applied respectively by way of lines 130-133 and lines 60-57 to the A1-A4 inputs of RAM 35. A non-zero status is loaded into RAMs 34 and 35 if an underrun condition has occured. At the time of receiving the interrupt of flip-flop 88, the MLCP examines the RAM 35 to determine the underrun condition. More particularly, the MLCP 10 issues a control word by way of the decoder 21 to the SEL 1 and SEL 2 inputs of RAM 35 to select a RAM address to be read. The decoder 21 further causes a logic zero level to be applied to the F input of the RAM, thereby enabling the RAM ouputs. If there is no underrun, the MLCP provides a next data byte as above described.
It is to be understood that whenever the MLCP 10 reads status information from the RAM 35 as above described, the output of gate 28 transitions to a logic zero level to enable drivers 224-227 of FIG. 2d. DCE 16 status information from receivers 220-223 thereupon are applied by way of lines 229-232 to tristate modes 278, 280, 282, and 284 of FIG. 2e. The lines 279, 281, 283 and 285 are read by the MLCP 10.
An underrun occurs when the MLCP 10 has not provided a new transmit data byte by the time a previous data byte has been shifted out of RAM 134 by way of microprocessor 110. If the flip-flop 32 remains in a set condition after a data byte has been shifted out of RAM 134 and microprocessor 110, an underrun condition is indicated.
The firmware control system thereupon sends an abort bit sequence to the DCE 16. Further, when a previous interrupt issued by flip-flop 88 has been serviced, the current underrun status is loaded into the RAM 35, and another interrupt is generated by flip-flop 88 to inform the MLCP that an underrun has occurred. The MLCP may then start a next message frame by loading data into the RAMs 26 and 30 as before described.
As soon as the data is transferred from the RAMs 26 and 30 to the mircroprocessor 110, and the MLCP is notified that additional data may be transferred to the HCLA, the MLCP has a time period of n bits where "n" is the byte size of the data in which to respond. When additional data is provided by the MLCP, the flip-flop 32 is reset by the MLCP by generating a logic one strobe at the D3 output of decoder 21 of FIG. 2a when data is to be loaded into the RAMs 26 and 30. The MLCP then resets the flip-flop 88 by generating a logic one strobe at the output of NAND gate 29 which is applied to the K input of the flip-flop.
While the RAMs 26 and 30 are being read, the before described transmit control byte is examined by the microprocessor 110 to determine the current byte size and to sense the occurence of the last byte in a message frame.
After a data byte, which may be of any byte size, is loaded into an input RAM of the microprocessor 110, a right shift operation occurs wherein the data byte is loaded into the RAM 134. The data byte then is reloaded into an internal RAM of the microprocessor 110 shifted right one bit and reloaded into the RAM 134. The rightmost bit of the data byte under firmware control is shifted out of the D1 output of microprocessor 110 to the Cd input of flip-flop 236 of FIG. 2d. Upon the next occurrence of a positive going slope of the DCE transmit clock signal on line 200, the contents of the internal RAM OF microprocessor 110 again is shifted to the right to load another bit into the flip-flop 236. In addition, the contents of the flip-flop 236 are loaded into the flip-flop 209. Upon a next occurrence of a positive going slope in the transmit clock signal, a next transmit data bit is transferred from flip-flop 236 to flip-flop 209. The data bits flow through the flip-flop 209 at the transmit clock rate, and through the D2 input of multiplexer 202 and driver 214 to line 215 leading to DCE 16. This process continues for n bit times wherein the letter "n" refers to the byte size.
After a data byte has been shifted out of the microprocessor 110, the firmware control system executes a TAMN instruction to test the flip-flop 32 of FIG. 2a. If the flip-flop 32 is set, an error condition is indicated wherein the MLCP has failed to transmit data at the HCLA processing rate. Thus an underrun condition has occurred.
Upon the occurrence of an end-of-frame as indicated by bit 3 of the transmit control byte, a status word is as before described loaded into the RAM 35 upon the occurrence of a next flip-flop 88 interrupt to indicate to the MLCP that the previous data message was transmitted correctly to the DCE 16.
Between message frames, either flag sequences or abort sequences are generated by the HCLA and transmitted to the DCE 16. More particularly, the bit 3 of the transmit control byte which specifies an end of a message is sensed between frames to indicate whether a flag or an abort sequence is to be issued to the DCE 16.
The HCLA 14 has a further provision for identifying to a receiver whether data or control bytes are being transferred. More particularly, the flag or abort control bytes are comprised of six or more contiguous logic ones. If five or more contiguous logic ones occur in an information transfer, the HCLA inserts a zero after the occurrence of five contiguous logic ones to flag to the receiver that data is being transferred. The receiver thereupon removes the zero to reconfigure the data message as all ones.
This feature occurs between locations 51300 and 54400 of the firmware program for a transmit operation. When a receive operation occurs, a logic zero is removed as provided between locations 98400 and 101900, and locations 105000 and 105100.
If a data receive operation is requested wherein data is transferred from the DCE 16 to the MLCP 10, the MLCP 10 issues a master clear signal to line 69 of FIG. 2a to reset the flip-flop 238. Whenever flip-flop 238 is reset, the Q output of the flip-flop is at a logic zero level which is applied to the set input of flip-flop 38 of FIG. 2a. The Q output of flip-flop 38 thereupon transitions to a logic zero level. This condition can be tested at multiplexer 137 by the TAMN instruction as described previously. During the period that the Q output of flip-flop 38 is at a logic zero level, no additional data from the DCE 16 is accepted and no new messages are assembled by the microprocessor 110.
When the MLCP 10 is ready to initiate a receive operation, the MLCP loads flip-flops 207 and 237-243 of FIG. 2d as previously described. In particular, flip-flop 207 is reset to select the multiplexer 202 to its A2-D2 inputs. In addition, the flip-flop 238 is set to allow the flip-flop 38 to be reset. When the firmware control system generates a logic zero at the D1 output of decoder 154 on line 84 to reset the flip-flop 38, a receive operation may be initiated.
The MLCP 10 loads RAM 30 with a four-bit receive control word when data is to be transferred from the DCE 16 to the MLCP 10. More particularly, the MLCP controls the D3 and D4 outputs of decoder 21 and the line 71 to load MLCP data bits 4-7 into the addressed locations of RAM 30. Bits 0, 1 and 2 of the control word indicate the expected byte size of the data byte to be received from the DCE 16.
Under firmware control, the receive control word is applied through to AND nodes 270, 272, 274 and 276 to the data inputs of microprocessor 110. More particularly, the D 3 and D4 outputs of PROM 185 applied respectively to lines 47 and 48 and the D1 output of PROM 182 applied to line 50 enable lines 43-46 leading to nodes 270, 272, 274 and 276 as described above.
The microprocessor operates upon the control word in accordance with a microinstruction supplied by the firmware control system to the IN0-IN8 inputs of the microprocessor. The result of the operation is indicated at the D0 output of the microprocessor, and applied by way of NOR gate 136 to the A6 input of multiplexer 137. If the multiplexer 137 is selected to the A6 input in response to the outputs of AND nodes 274, 272, and 270 on lines 138-140, respectively, the A6 input of the multiplexer is applied through flip-flop 149 to enable decoder 141. In response to firmware control system signals on lines 150-152, the D0 and D7 outputs of decoder 141 are applied through AND gate 153 to enable decoder 154.
when the HCLA 14 is ready to receive data from the DCE 16 as evidenced by a logic one level at the Q output of flip-flop 238 and the Q output of flip-flop 38, data bits from the DCE 16 are accepted. More particularly, a DCE receive clock signal having a clock rate up to 20.0 KHz is received from the DCE 16 on line 203 of FIG. 2d. The clock signal is applied through the B2 input of multiplexer 202 and inverter 211 to the clock inputs of flip-flops 212 and 213. Data bits from the DCE 16 are received on line 205, and applied through receiver 206 and the C2 input of multiplexer 202 to the CD input of flip-flop 212. Upon the occurrence of each rising edge in the DCE receive clock signal at the output of inverter 211, a data bit from DCE 16 is shifted into flip-flop 212 and the flip-flop 213 is set.
The firmware control system monitors the Q output of flip-flop 213 on line 145 by selecting the multiplexer 137 to its A5 input in the manner before described. When the Q output is at a logic one level, the firmware control system resets the flip-flop 213 by issuing a logic zero signal at the D5 output of decoder 154. The firmware control system then executes a routine for receiving data from the DCE 16 as indicated at location 98400 of Appendix A.
The Q output of flip-flop 212 is applied to the tristate driver 127 of FIG. 2b. When the firmware control system issues a logic zero to line 129 to enable the output of driver 127 and a microinstruction to the microprocessor 110 for performing a right shift, the DCE data bit is applied through the driver and right shifted into an input RAM of the microprocessor 110. The above-described process is repeated for each rising slope of the DCE receive clock signal at the output of inverter 211.
In this manner, data bit sequences from the DCE 16 are shifted into the input RAM of the microprocessor 110 for further examination. More particularly, the occurrence of an eight-bit signal including a logic zero followed by six consecutive logic ones and a logic zero indicates a flag sequence. The flag sequence may indicate the start of a message frame, or more accurately that a message frame shall follow. When a flag sequence is followed by a non-flag sequence, the non-flag sequence indicates that the first part of the message has begun. If the non-flag sequence is comprised of seven or more but less than 15 consecutive logic one bits, however, an abort sequence is indicated. The abort sequence occurs when something has gone wrong with a data transfer. The data receiver thereupon should disregard the information transmitted during the current message frame.
If fifteen or more logic one bit signals occur in a sequence, an idle link state is present. The idle link state indicates that no more data shall be forthcoming.
A flag sequence of bits is used to indicate that an end-of-frame has occurred, and a following idle link state sequence would indicate that the receive operation has been completed.
In examining the bit stream shifted into the internal RAM of microprocessor 110, the microprocessor executes a TAMN instruction provided by the firmware control system to test for the occurrence of a particular sequence of bits. If the particular sequence of bits is found, the D0 output of the microprocessor on line 135 transitions to a logic one level to indicate a true condition. If the condition is false, however, the line 135 transitions to a logic zero level. This condition is signalled to the firmware by way of multiplexer 137 as before described. When the D0 output of the microprocessor is at a logic one level, a next instruction in the firmware program of Appendix A is executed. When it is at a logic zero level, however, the next instruction is skipped in the firmware program.
The binary information stream from the DCE 16 initially is sensed to detect a flag sequence indicating the beginning of a frame. Upon detecting a flag sequence, the data bit stream is sensed eight bits at a time to detect a non-flag sequence. The occurrence of a non-flag sequence indicates a first data byte in a frame. If another flag sequence or an abort bit sequence occurs before 24 bits of a non-flag sequence occurs, the indicated message frame is too short and the message frame is unacceptable. If a second flag sequence is detected after the unacceptable message frame is indicated, the start of a second message frame may have occurred. If an abort sequence is detected in an unacceptable message frame, however, the firmware control system continues to look for a second flag sequence or an idle link state condition. It is to be understood that the flag, abort and idle link state bit sequences are never transferred to the MLCP 10. The acceptance of such bit sequences, however, are reported.
If the firmware control system detects an idle link state, the MLCP 10 is informed by a status word transfer. The firmware senses the Q output of flip-flop 88 in FIG. 2b to determine whether the RAM 35 is being used in a transmit operation. If the flip-flop 88 is reset, a transmit operation is not occurring and a status code is transferred to the RAM 35 as previously described. In addition, the firmware control system issues a logic zero signal by way of the D3 output of decoder 154 to the line 91. The signal is applied through inverter 90 of FIG. 2a to the CJ input of flip-flop 87. A logic zero receive service request signal thereby is provided at the Q output of flip-flop 87. Since the Q outputof flip-flop 38 is at a logic one level, the output of AND gate 86 transitions to a logic zero level to signal the MLCP 10 to read the status information in RAM 35. In response thereto, the MLCP 10 reads the RAM 35, and resets the flip-flop 87. More particularly, the MLCP decoder 21 issues a logic zero signal at its D6 output and the MLCP issues a logic signal to line 92. The output of gate 33 thereupon transitions to a logic one level which is applied to the CK input of flip-flop 87 to reset the flip-flop. The MLCP 10 thereby is notified that an idle link state is present and in turn notifies the HCLA 14 that the status word has been read.
After 24 bits in a message frame have been detected, a first eight bit data byte is transferred to the MLCP 10. If a transmit operation is not occurring, the data byte is loaded from lines 57-60 into the RAMS 34 and 35 in response to gate 56. More particularly, four data bits are loaded into RAM 34 and four data bits are loaded into RAM 35. In addition to the four data bits, a message frame status byte is loaded into RAM 35 as previously described. An all zero status byte indicates that a data byte exists in the RAMS 34 and 35, and that such byte is not the last byte of a frame. A non-zero status byte indicates that a last data byte has occurred in a frame.
The firmware control system thereafter generates a strobe at the D3 output of decoder 154 which is applied to the Cj-input of flip-flop 87 to generate an interrupt. The MLCP 10 thereby is notified that receive data and status information has been loaded into the RAMs 34 and 35. In response thereto, the MLCP reads the RAMs 34 and 35. More particularly, the SEL 1, SEL 2 and F inputs to RAMs 34 and 35 are controlled by the decoder 21 to supply the received data to lines 61-68. The data on lines 61-64 is applied through tristate nodes 278, 280, 282 and 284 of FIG. 2e to the MLCP 10. The data on lines 65-68 are supplied directly to the MLCP. The MLCP then resets the flip-flop 87 as before described.
In transferring information from the HCLA 14 to the MLCP 10, the first two data bytes are always eight bit bytes. Thereafter, the byte size is indicated by the receive control byte in RAM 30. If a byte size is less than eight bits, the byte is right justified within an eight-bit field by the microprocessor 110 before being loaded into the RAMS 34 and 35. Before each byte is loaded into the RAMS 34 and 35, however, the flip-flop 88 is sensed under firmware control as before described to detect a transmit mode condition. Further, the firmware control system senses the output of flip-flop 87 to detect a receive mode condition. If flip-flop 87 is set, the MLCP 10 is reading the last data bytes stored in the RAMs 34 and 35, and an overrun error is indicated. If an overrun condition occurs, further data byte transmission to the MLCP is inhibited. More particularly, no further data byte transfers are made to the RAMs 34 and 35, and no interrupt is generated to the MLCP to indicate that RAMs 34 and 35 are to be read. The above described operation continues until a flag bit sequence or an abort bit sequence is detected. The occurrence of a flag bit sequence indicates the end of a valid message frame, while the occurrence of an abort sequence indicates the end of an invalid message frame.
It is to be understood that the occurrence of a flag bit sequence at the end of a message frame does not necessarily mean that all information within that message frame has been transferred to the MLCP. Rather, the information may still reside both in the RAMs 34 and 35, and in the internal RAMs of the microprocessor 110. The last two bytes occurring in a message frame are FCS (frame check sequence) bytes. Each of the two bytes occur in an eight bit field to provide a CRC (cyclic redundancy check).
After the occurrence of a flag bit sequence at the end of a message frame, no further activity occursuntil the MLCP 10 has read the data in RAMs 34 and 35, and has reset the flip-flop 87. The data in RAMs 34 and 35 at the time the flip-flop is reset is the next to the last data byte preceding the FCS bytes. Thereafter, the firmware control system right justifies the last data byte, and again checks to insure that a transmit mode condition is not present. The last data byte then is loaded into the RAMs 34 and 35.
The firmware control system supplies a last data byte size indicator to the A1-A3 inputs of RAM 35. A logic one also is supplied to the A4 input of the RAM to indicate that the data byte currently residing in RAMs 34 and 35 is the last data of the message. A receive interrupt then is generated at the output of flip-flop 87 to flag to the MLCP 10 that status information is to be read from RAMs 34 and 35. The MLCP first reads the status in RAMs 34 and 35, and then reads the data in RAMs 34 and 35. The MLCP thereafter resets the flip-flop 87.
Upon detecting the reset condition of flip-flop 87, and sensing flip-flop 88 and 87 to detect the non-occurrence of a transmit mode and the occurrence of the receive mode, the firmware control system loads the RAMs 34 and 35 with the right half of the FCS bit sequence. The firmware control system then loads the RAM 35 with status information which is an all zero indication that a normal message frame has occurred. If a short message frame, an abort frame, or an overrun condition is detected, however, the FCS bit sequence is not transferred to the MLCP. More particularly, bit 4 of the status information signals the occurrence of a short frame, bit 5 signals the occurrence of an abort condition, and bit 6 signals the occurrence of an overrun condition. It is to be understood that a frame having less than twenty-five bits is automatically discarded. A frame having between twenty-five and thirty-one bits is designated a short frame.
When the firmware control system sets the flip-flop 87 to interrupt the MLCP 10 as before described, the above-described operation is repeated for the left half of the FCS bit sequence which is an all zero status word under normal operating conditions. The FCS bit sequence is transferred to the MLCP 10 by the firmware control system independent of the DCE 16 receive clock signals on line 203 of FIG. 2d.
If the MLCP 10 should command a termination of message frame at any time during the transfer of a message from the HCLA 14, the MLCP 10 resets the flip-flop 238 which in turn sets flip-flop 38. In response thereto, the firmware control system inhibits the HCLA 14 from receiving further messages until the flip-flop 238 is once again set by the MLCP.
APPENDIX A DESCRIPTION
The following is an explanation of those parts of the firmware program of Appendix A necessary for an understanding of the invention. The locations 2700 through 3400 of the listing refer to constant fields which are named and followed by a numeral/numeral configuration referring to the first bit and the number of bits in a field. At location 2900, for example, the ISCFLD field begins at bit 7 and is of a one bit size. If bit 7 is at a logic one, the subcomand is inhibited. If bit 7 is at logic zero, however, the subcommand is not inhibited.
It is to be understood that specified bits may be referenced in more than one field. For example, bit 7 is contained within both the K field at location 2800 and the ISCFLD at location 2900. This is permissible as long as the bit is not simultaneously specified to contain conflicting information.
Referring to the instruction dictionary at locations 25800 through 27700, the instructions appearing at the D0-D7 outputs of the instruction decoder 141 of FIG. 2b are defined. The operands for each of the instruction are defined at locations 2300 through 25600. Each operand is comprised of a field type, a field name and a field definition. More particularly, at location 2300, the field type is BRCHFLD which is a branch field. The field name is BRADDR which is a branch address. That part of the operand which follows the branch address is the field definition. The different types of operands include the branch field, the constant field, and the argument definition field.
Looking further at the location 2300, it is seen that the BRADDR field begins with bit 10 and is comprised of 10 bits. These 10 bits correspond to the firmware control store logic signals of RAMs 180, 185 and 186, which are applied to the data inputs of counters 175-177 of FIG. 2c to execute a branch instruction.
Referring again to the instruction d efinitions at locations 26000 through 27300, it is seen that two fields are set out within parenthesis. The first field includes variables which have to be defined by the firmware decoder 154 of FIG.2b. Referring more particularly to location 27200, it is seen that the firmware decoder would have to fill the branch address. An allowable sub field thereafter follows as determined by the sub fields defined between locations 24700 and 25600, inclusively.
The constant fields are defined within the second field. These constant fields shall remain constant throughout the program, and are not again considered by the firmware program.
Referring by way of example to the location 87100, a $ is shown followed by an address tag. An address tag in each instruction is required only if that instruction is addressed during a branch operation. If a step-by-step instruction incrementation occurs, however, then only the $ need occur in the tag field. The next field is a microinstruction field WER, which is followed by an operand field. The field next occurring to the right is a comment field which begins with a back slash mark and ends with a semicolon. Thus, each instruction begins with a $ and ends with a ;.
The hexidecimal equivalent of the tag field, microinstruction and operand fields occurs to the far right.
Relating the firmware listing more particularly with the electrical schematic diagrams of FIGS. 2a-2e, the bits 0 through 2 of the constant field at location 2700 correspond to the microprocessor control memory bits 0-2 applied to the B3-B1 inputs of the instruction decoder 141 of FIG. 2b. The constant field at location 2800 provides a means by which data maybe loaded into the microprocessor 110. The field of four bits correspond to the microprocessor control memory bits supplied by the firmware control system to lines 188-191 of FIG. 2e. The microprocessor input data bits at the output of AND nodes 270, 272, 274, 274 and 276 are applied to the data input of the microprocessor 110.
Referring to location 2900, bit 7 of the inhibit sub field corresponds to the microprocessor control memory bit on line 188 of FIG. 2e. Referring to location 3000, the ALU data control field which begins with bit 19 is used as a check code to insure that other instructions are not written incorrectly. Referring to location 3100, the inhibit microprocessor file write field refers to five bits beginning with bit 20. These bits correspond to the microprocessor control memory bits 20 through 24 applied respectively to lines 120, 119, 126, 125 and 129 of FIG. 2b. This constant field serves to fill in bits within an indicated field to preserve information that is already in the microprocessor 110, and is used only in the execution of branch instructions.
Referring to location 3200, the inhibit external RAM and input buffer file read fields include three bits beginning with bit 25. These bits correspond to microprocessor control memory bits 25-27 which are provided at the D3, D2 and D1 outputs of PROM 182 of FIG. 2c. At location 3300, the inhibit external RAM constant field is comprised of bit 25 only, which is the microprocessor control memory bit 25 provided at the D3 output of PROM 182.
The three bits of the IFRFLD constant field at location 3200 of the firmware program enable the output of RAMs 26, 30 and 134. The bit 25 of the IERFLD constant field at location 3300 enables the output of RAM 134 only. The all bits field at location 3400 comprises all 28 bits of the control memory provided by PROMs 180-186. This constant field is used to set unused memory locations to zero.
The argument definition FA field at location 4700 of the firmware program selects the A file address of the RAM A memory within the microprocessor 110. The FB field at location 5400 selects the B file of the RAM B memory within the microprocessor 110. The FA field bits are applied to the RA1-RA4 inputs of the microprocessor, and the FB field bits are applied to the RB1-RB4 inputs of the microprocessor.
The OPFLD argument definition field at location 8300 has a divided 7-bit field: bit 3 and bits 16 thru 21. Each of these bits correspond to microprocessor control memory bits leading to the inputs of the microprocessor 110, and controls the ALU logic within the microprocessor.
Referring to locaton 17200, the FDFLD argument definition field includes three bits beginning with bit 22. These bits correspond to the microprocessor control memory bits 22, 23 and 24. Bits 22 and 23 are provided at the D2 and D1 outputs of PROM 181 of FIG. 2c, and bit 24 is provided at the D4 output of PROM 182. A right shift operation is indicated when bit 22 is at a logic one level, and bits 23 and 24 are at a logic zero level. A data bit received from DCE 16 thereby is shifted into the microprocessor 110. When bits 22, 23, and 24 each are at the logic one level, a left shift is indicated, and a receive bit is not shifted into the microprocessor 110. Any other combination of bits 22 and 23 merely inhibit the driver 127 as long as bit 24 is a logic one.
Referring to location 18500 of the firmware program of Appendix A, the RAFLD argument definition field includes four microprocessor control memory bits beginning with bit 8. The RA stands for the external RAM address, and refers to RAM 134. The microprocessor control memory bits 8-11 are provided respectively at the D4, D3, D2 and D1 outputs of PROM 185. The bits select a write address when information is being written into the RAM 134, and a read address when the information is being read from the RAM 134.
Referring to location 19900, the OBFFLD argument definition field refers to four microprocessor control memory bits 8-11 which are applied to the inputs of RAMs 26, 30, 34 and 35. More particularly, bit 8 is applied to the L2 input of RAM 34, bit 9 to the SEL 1 inputs of RAMs 26 and 30, bit 10 to the L1 input of RAM 34 and bit 11 to the L1 input of RAM 35.
At location 21200, an input buffer file field is shown which has a divided 4-bit field comprising microprocessor control memory bits 8, 9 and 26, 27 which are applied to the RAMs 26 and 30. More particularly, bits 8 and 9 are applied to the SEL 2 and SEL 1 inputs respectively of RAM 26 and RAM 30 of FIG. 2a. Bit 26 is applied to the F enable input of RAM 26, and bit 27 is applied to the F enable input of RAM 30.
Referring to location 22800 of the firmware program, a TSTFLD argument defination field is comprised of three bits beginning with bit 4. These bits correspond to the microprocessor control bits 4-6, which are applied respectively to lines 191, 190 and 189 of FIG. 2e to provide select control signals for the multiplexer 137. Referring to location 24700, the SUBFLD argument definition field also is comprised of the microprocessor control memory bits 4-6. The bits of the sub field argument definition field are applied to lines 191, 190 and 189 of FIG. 2e to provide inputs to decoder 154 of FIG. 2b.
The above-described fields are used in the definition of each of the microinstructions of locations 26000 through 27400. In the fields of each instruction, those numerals followed by the letter C are octal numbers, and those followed by the symbol # are hexidecimal numbers. Each of the instructions have a variable field known as the argument definition field, and a constant field. All of the instructions except for the TAMN instruction are single-cycle instructions. The TAMN instruction, however, is a two-cycle instruction in that execution of the next instruction is effected by the outcome of the TAMN instruction.
In loading an instruction set into the PROMs 180-186, each of the instructions are dispersed throughout the PROMs. More particularly, referring to location 75300 and the hexidecimal image field indicated therein, the letter C comprising bits 0-3 is located in PROM 183. The letter F comprising bits 4-7 is located in PROM 184, the hex numeral 2 in PROM 185, the hex numeral 0 in PROM 106, the F in PROM 180, the C in PROM 181 and the B is located in PROM 182. D4 output of each PROM is the leftmost bit, and the D1 output is the rightmost bit. By way of example, if the third hexadecimal digit is a D as shown in location 31100, the D4 through D1 outputs of PROM 185 have a logic level order of 1101, respectively.
Having described the invention in connection with certain specific embodiments thereof, it is to be understood that further modifications may now suggest themselves to those skilled in the art and it is intended to cover such modifications as fall within the scope of the appended claims. ##SPC1## ##SPC2## ##SPC3## ##SPC4##
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A hardware/firmware communication control logic system for accommodting the concurrent bidirectional transfer of data messages between a communications processor and different terminal devices via a communication channel which comprises: (a) memory means in electrical communication with said communications processor for storing said data messages and status and control information exchanged between said communications processor and said control logic system; (b) firmware control means in electrical communication with said memory means and responsive to stored control information received from said communicatons processor for supplying microinstruction sequences to control the operation of said control logic system; (c) microprocessor logic control means in electrical communication with said firmware control means and said memory means for modifying said microinstruction sequences and serializing and deserializing said data messages; (d) interface logic means in electrical communication with said microprocessor logic control means and said firmware control means for supplying interrupt service requests and control information to said communications processor, said communications channel, and said control logic system; and (e) said firmware control means operating in response to said control information from said processor to adapt the functions of said control logic system to the requirements of said different terminal devices.
2. A hardware/firmware communication control logic system for accommodating the concurrent bidirectional transfer of data messages between a communications processor and a communication line, which comprises: (a) first memory means in electrical communication with said communications processor for storing control and data information; (b) second memory means in electrical communication with said communications processor for storing status and data information; (c) processor decoder means responsive to said communications processor for issuing commands to control the writing of control and data information into said first memory means, and the reading of data and status information from said second memory means; (d) interrupt control logic means in electrical communication with said comunications processor and said processor decoder means for issuing interrupts to request data, control and status information from said communications processor; (e) logic resynchronization means in electrical communication with said processor decoder means for initializing said control logic system to receive data information from said communication line; (f) microprocessor means in electrical communication with said first and said second memory for serializing data from said communications processor and deserializing data from said communication line; (g) firmware control store memory means in electrical communication with said microprocessor means, and said first and said second memory means for controlling the operation of said control logic system; (h) address counter means responsive to said communications processor for addressing said firmware control store memory means to provide a sequence of microinstructions; (i) firmware instruction decoder means in electrical communication with said microprocessor means and said firmware control store memory means for controlling the writing of data into said second memory means, the loading of data into said mircoprocessor means, and the updating of said address counter means; (j) microprogram subcommand generator means responsive to said firmware control store memory means and said firmware instruction decoder means for controlling the operation of said interrupt control logic means and said logic resynchronization means; (k) multiplexer means responsive to said firmware control store memory means and in electrical communication with said microprocessor means, said interrupt control logic means and said logic resynchronization means for controlling the modification of microinstructions in said firmware instruction decoder means; (1) communication line interface logic means in electrical communication with said microprocessor means, said microprogram subcommand generator means and said communication line for signalling the occurrence of a transmit data bit or a receive data bit to said multiplexer means; (m) line control logic means responsive to said processor decoder means and said communications processor for supplying control signals to said communication line, said resynchronization means, and said interrupt control logic means.
3. A hardware/firmware comunication control logic system for accommodating the concurrent bidirectional transfer of message data between a communications processor and a communication channel which comprises: (a) memory means in electrical communication with said communications processor for storing message data to be transmitted to said channel and status and control information exchanged between said communications processor and said control logic system; (b) firmware control means responsive to said communications processor and in electrical communication with said memory means for supplying microinstruction sequences to control the operation of said control logic system; (c) microprocessor logic control means in electrical communication with said firmware control means and said memory means for modifying said microinstruction sequences and serializing and deserializing said data messages; (d) underrun means for providing a no data indication; (e) means responsive to said firmware control means for actuating said underrun means when said memory means is emptied of message data during a transmit operation; and (f) means responsive to said underrun means for signalling said communications processor of an underrun condition prior to the transfer of additional message data from said processor.
4. A hardware/firmware communication control logic system for accommodating the concurrent bidirectional transfer of message data between a communications processor and a communication channel which comprises: (a) memory means in electrical communication with said communications processor for storing said message data and status and control information exchanged between said communications processor and said control logic system; (b) firmware control means responsive to said communications processor and in electrical communication with said memory means for supplying microinstruction sequences to control the operation of said control logic system; (c) microprocessor logic control means in electrical communication with said firmware control means and said memory means for modifying said microinstruction sequences and serializing and deserializing said data messages; (d) receive means controlled by said firmware control means for receiving message data from said communication channel and transferring said data to said memory means and then to said communications processor; (e) overrun means for providing a data present indication; (f) means responsive to said firmware control means for actuating said overrun means when said memory contains message data which has not been transferred to said communications processor; and (g) further means responsive to said firmware control means for signalling said communications processor of an overrun condition if said overrun means is actuated when said receive means is operated to transfer data to said memory means.
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