Bridge Amplifier

1. Field of the Invention

This invention relates to audio amplifier circuits and more particularly to bridge amplifier circuits.

2. Description of the Prior Art

Audio bridge amplifiers are well known in the art. Most, if not all, of the contemporary bridge amplifiers are comprised of at least two operational amplifiers using coupling capacitors and some direct current adjustment circuitry for adjusting and matching components to reduce the output offset voltage of the amplifier. It is desirous to reduce the output voltage offset in order to reduce the power consumption of the bridge amplifier. It is also desired to produce the bridge amplifier in monolithic integrated circuit form to maximize circuit efficiency and to reduce production costs.

Because many prior art bridge amplifiers require large capacitors and other external circuits for adjustments, the cost of these external components offset any practical savings which may result by fabricating the amplifier in monolithic form. Thus, a need exists to reduce or eliminate as many required external components as possible while maintaining the output offset voltage to a minimal level.

Accordingly, it is an object of the present invention to provide an improved bridge amplifier.

It is another object of the present invention to provide a monolithic bridge amplifier circuit having a minimal output offset voltage.

It is an additional object of the present invention to provide monolithic bridge amplifier circuit requiring few, if any, external components for operation while simultaneously producing a minimal offset voltage at the output thereof.

In accordance with the foregoing and other objects there is provided a bridge amplifier comprising a pair of operational amplifiers. The noninverting inputs of the two amplifiers being coupled to a reference voltage and their outputs being the outputs of the bridge amplifier. The inverting input of the first amplifier being the input of the bridge amplifier and being coupled via a resistor to its output. The inverting input of the second amplifier being coupled through a first and second resistor respectively to its output and to the output of the first amplifier such that the direct current (dc) level of the output voltage developed between the outputs of these two amplifiers is minimal.

The single FIGURE is a partial block and schematic diagram of the preferred embodiment of the invention.

The preferred embodiment of the invention is shown in the single FIGURE. Bridge amplifier 10 is illustrated as inlcuding two operational amplifiers 12 and 14 having outputs coupled respectively to output terminals 16 and 18. A load 20 is shown coupled between the output terminals 16 and 18 of the bridge amplifier circuit. The inverting inputs of operational amplifiers 12 and 14 are coupled to a reference source voltage VR through resistors 22 and 24 respectively. The inverting input of operational amplifier 12 is coupled through resistor 26 and direct current (d.c.) blocking capacitor 28 to input terminal 30 at which is provided an input signal to the circuit. It is understood that bridge amplifier 10 is suited for fabrication in monolithic integrated circuit form. Hence, capacitor 28 may or may not be included in the integrated chip. A gain setting resistor 32 is coupled between the output and the inverting input of operational amplifier 12. The inverting input of operational amplifier 14 is connected at a common junction to one terminal of each of the resistors 34 and 36. The other terminal of resistor 34 is returned to output terminal 18 and the other terminal of resistor 36 is returned to output terminal 16.

In operation, bridge amplifier 10 converts an asymmetrical input signal applied at input terminal 30 into a symmetrical output voltage applied to load 20. In a quiescent operating state only a very small output offset voltage is generated across the load (generally less than or equal to 20 mV across a 4 ohm load). In a preferred embodiment load 20 may be a speaker.

As illustrated, the noninverting inputs of amplifiers 12 and 14 are each connected to reference voltage VR. Ideally, since almost no current flows into these inputs of the amplifiers, VR can be derived from a single power supply through a simple resistor bridge.

Neglecting input current to amplifier 12, it can be shown that the output voltage appearing at the output of this amplifier, at terminal 16, is equal to VR (neglecting the voltage offset of the amplifier). Similarly, it can be shown that the output voltage of amplifier 14 which appears at terminal 18 is nearly equal to VR. Thus, the voltages appearing at respective output terminals 16 and 18 are substantially equal in the d.c. quiescent state.

In practice, however, a small offset voltage appears across the load 20. This offset voltage is caused by the input offset currents and voltages of amplifiers 12 and 14. This output offset voltage can be determined and is equal to:

provided:

Where:

I'12 is the offset current of amplifier 12

V'12 is the offset voltage of amplifier 12

I'14 is the offset current of amplifier 14

V'14 is the offset voltage of amplifier 14

By matching the characteristics of amplifiers 12 and 14 and maintaining close tolerance on the resistor values through the use of integrated circuit technology the d.c. offset voltage can be maintained at a few millivolts which in many cases is an acceptable level. In the preferred embodiment, the magnitude of VR is chosen to lie in the middle of the output range of the two amplifiers so that there is minimum distortion in the system.

As understood, in response to an applied voltage Vin, the output voltage of amplifier 12 is equal to:

Since no alternating current (a.c.) component is applied to the noninverting input of amplifier 14, and considering the gain of this amplifier to be infinite, the output voltage appearing at terminal 18 can be shown to be nearly equal to:

Thus, the output voltage appearing across the load is:

If the outputs of both amplifiers 12 and 14 have the same excursion range, and R36 made equal to R34;

A bridge amplifier circuit has been described above having minimal direct voltage offset. The circuit provides maximum gain utilizing a single power supply and is suitable to be fabricated in monolithic integrated form.