Common Base Connected Transistor and Bias Network

The present invention pertains to common base amplifiers and particularly to the biasing of common base amplifiers for linear operation. In prior art devices the most common method used to bias common base amplifiers is to float the base and bias the circuits similar to that of common emitter circuits. The capacitance added in series with the base circuit by utilizing this method causes additional instabilities and tends to limit the bandwidth in the high power, high frequency devices. If the base is not floated and a negative voltage is applied to the emitter, the bias network must be capable of handling the same current as the collector since the emitter circuit is the device return.

The present invention pertains to a common base connected transistor wherein the base is connected directly to ground and bias network including a first impedance connected from the emitter to the ground and a second impedance connected from the emitter to a common negative terminal, with a floating bias source connected between the negative terminal and an impedance connected to ground for biasing the transistor into the proper operation and a floating collector potential source connected between the negative terminal and an impedance to the collector for providing the required collector current. The grounded base increases the stability and bandwidth of the circuit while the floating power supplies are separated so that the collector current does not flow through the bias circuit and, therefore, may be relatively high without affecting the bias circuit.

It is an object of the present invention to provide a new and improved common base connected transistor and bias network.

It is a further object of the present invention to provide a new and improved common base connected transistor and bias network wherein the base is connected directly to ground to increase stability and bandwidth and the biasing potential and collector electrode potential are floating and separated so that collector current does not flow through or affect the biasing circuits.

These and other objects of this invention will become apparent to those skilled in the art on consideration of the accompanying specification, claims and drawings.

Referring to the drawings, wherein like characters indicate like parts throughout the figures:

FIG. 1 is a simplified representative schematic diagram of a common base connected transistor and bias network embodying the present invention; and

FIG. 2 is a somewhat more complex schematic diagram similar to FIG. 1.

In FIG. 1, the numeral 10 generally designates an N-P-N type transistor having an emitter 11, a collector 12 and a base 13. The emitter 11 is connected through impedance means 20 to a ground 21. The emitter 11 is also connected through a second impedance means 23 to a common negative potential terminal 25. In addition, the emitter 11 serves as the input for the circuit and, accordingly, is connected directly to an input terminal 27. A second input terminal 29 is connected directly to the ground 21 to provide a two terminal input. The collector 12 is connected directly to an output terminal 31, having a companion output terminal 33 connected to the ground 21. The collector 12 is also connected through a third impedance means 35 to a positive potential terminal 37. A collector potential source 39 (illustrated as a simple battery for convenience) is connected between the positive potential terminal 37 and the negative common terminal 25. A fourth impedance means 41 is connected between a positive bias potential terminal 43 and the ground 21. A bias potential source 45 (represented by a simple battery for convenience) is connected between the positive bias terminal 43 and the negative common terminal 25.

In the operation of the circuit, the power supplies 39 and 45 are floating because the DC return is connected to the negative terminal 25 and not to the DC ground 21. The base 13 of the transistor 10 as well as the first impedance means 20 in the bias circuit is returned to DC ground. This connection with a positive bias voltage input at the terminal 43 makes the emitter 11 negative with respect to the base 13. With the circuit connected as illustrated, the collector current, which can be very large for high powered devices, is returned through the second impedance means 23 and has no effect on the bias circuitry. A major advantage of the bias network is that a relatively simple circuit can be connected to bias a common base linear amplifier without the need to float the base. This circuit results in good stability and bandwidth. A further advantage of the circuit is that a low voltage, low current, positive power supply can be used as in common emitter circuits. Generally, the circuit is useful in applications for broadband linear amplifiers above 500 MHz where maximum gain and minimum devices are required. Particularly, common base devices are commonly used above one GHz because of their high gain.

Referring to FIG. 2, a more specific schematic diagram of a common base connected transistor and bias network is illustrated. Similar numbers are used to indicate similar parts and all of the numbers have a prime added to indicate a different embodiment. In this specific circuit, the impedance means 20', 23', 35' and 41' (illustrated in FIG. 1 as simple resistors) are illustrated as more complex impedances which may be utilized in high frequency broad band linear amplifiers. The first impedance means, generally designated 20', includes a variable resistor 50', with a variable contact connected to the ground 21', connected in series with an RF choke 52'. The second impedance means, generally designated 23', includes and RF choke 54' with a bypass capacitor 55' connected from the common negative terminal 25' to ground 21'. The third impedance means, generally designated 35', includes an RF choke 57' and a bypass capacitor 58' connected from the positive potential terminal 37' to ground 21'. The fourth impedance means, generally designated 41', includes a first resistor 60' and a second resistor 62' connected in series between the ground 21' and the positive bias potential terminal 43'. In this embodiment, a diode 65' is connected between the first and fourth impedance means. The anode of the diode is connected to the junction of the resistors 60' and 62' and the cathode is connected to the junction of the variable resistor 50' and the RF choke 52'. The purpose of the diode 65', in part, is to provide a low dynamic resistance source for the base-emitter bias of the transistor 10'. The resistors 50' and 60' act to increase the dynamic resistance and to reduce the effect of temperature variations of the voltage drop of diode 65'. Typical values for the components of the circuit of FIG. 2 are set forth below.

Thus, a new and improved common base connected transistor and bias network is illustrated and described, which circuit is much simplier than prior art circuits and allows for high power operation while maintaining good stability and bandwidth. While an N-P-N type transistor is utilized in the embodyments illustrated, it will be obvious to those skilled in the art that a P-N-P type transistor might be substituted therefor with minor modifications to the circuitry. Further, while we have shown and described specific embodiments of this invention, further modifications and improvements will occur to those skilled in the art. We desire it to be understood, therefore, that this invention is not limited to the particular forms shown and we intend in the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.