US 4,245,304 AGrant
Cache Arrangement Utilizing a Split Cycle Mode of Operation
Issue Date:1981-01-13
•39 Claims
•33 Drawing Sheets
Abstract
A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle. During the first half of the cycle, the address selected by the address switch in response to control signals from the control circuits is clocked into the address register. This permits processor operations, such as the accessing of operand data or the writing of data into cache to be performed during the second half of the same cycle.
Metadata
Assignee
- Honeywell Information Systems Inc.
Inventors
- Marion G. Porter
- Robert W. Norman, Jr.
- William A. Shelly
Application Information
Application Number:US 9683127
Filing Date:1978-12-11
Priority Date:1978-12-11
Art Unit:237
Classifications
IPC:
G06F 1300
Field of Search:
364200 MS File;900 MS File
Patent Drawings (33 sheets)
Description
REFERENCED APPLICATIONS
1. "Data Processing System Programmable Pre-Read Capability" invented by John E. Wilhite, William A. Shelly and Charles P. Ryan, Ser. No. 853,944, filed on Nov. 22, 1977 and assigned to the same assignee as named herein.
2. "A Microprogrammed Computer Control Unit Capable of Efficiently Executing a Large Repertoire of Instructions for a High Performance Data Processing Unit" invented by John E. Wilhite, Ser. No. 853,946, filed on Nov. 22, 1977 now U.S. Pat. No. 4,179,936, issued Dec. 18, 1979 and assigned to the same assignee as named herein.
3. "A Cache Memory Location Selection Mechanism" invented by Charles P. Ryan, Ser. No. 858,575, filed on Dec. 8, 1977 and assigned to the same assignee as named herein.
4. "An Instruction Buffer Associated with a Cache Memory Unit" invented by John E. Wilhite, William A. Shelly and Charles P. Ryan, Ser. No. 866,083, filed on Dec. 30, 1977 and assigned to the same assignee as named herein.
5. "A Cache Memory Command Circuit" invented by Charles P. Ryan, Ser. No. 861,228, filed on Dec. 16, 1977 and assigned to the same assignee as named herein.
6. "Buffer Store Including Control Apparatus which Facilitates the Concurrent Processing of a Plurality of Commands" invented by Charles P. Ryan, Ser. No. 853,982, filed on Nov. 22, 1977 now U.S. Pat. No. 4,156,906, issued May 29, 1979 and assigned to the same assignee as named herein.
7. "Cache Unit Information Replacement Apparatus" invented by Marion G. Porter, Robert W. Norman, Jr. and Charles P. Ryan, Ser. No. 968,048, filed on Dec. 11, 1978 and assigned to the same assignee as named herein.
8. "Instruction Buffer Apparatus of a Cache Unit" invented by Marion G. Porter and Robert W. Norman, Jr. Ser. No. 968,050, filed on Dec. 11, 1978 and assigned to the same assignee as named herein.
9. "A Cache Arrangement for Performing Simultaneous Read/Write Operations" invented by Marion G. Porter, William A. Shelly and Robert W. Norman, Jr., Ser. No. 968,521, filed on Dec. 11, 1978 and assigned to the same assignee as named herein.
10. "A Cache Unit with Transit Block Buffer Apparatus" invented by Marion G. Porter, Charles P. Ryan and William A. Shelly, Ser. No. 968,522, filed on Dec. 11, 1978 and assigned to the same assignee as named herein.
11. "Cache Apparatus for Enabling Overlap of Instruction Fetch Operations" invented by Marion G. Porter and Charles P. Ryan, Ser. No. 968,049, filed on Dec. 11, 1978 and assigned to the same assignee as named herein.
12. "Command Queue Apparatus Included Within a Cache Unit for Facilitating Command Sequencing" invented by Marion G. Porter, Ser. No. 963,311, filed on Dec. 11, 1978 and assigned to the same assignee as named herein.
BACKGROUND OF THE INVENTION
1. Field of Use
The present invention relates to data processing systems and more particularly to cache memory systems.
2. Prior Art
It is well known to provide hierarchal memory organizations in which a large slow speed main memory operates in conjunction with a small high speed buffer storage unit or cache. In such arrangements, the central processing unit (CPU) can access operand data and/or instructions at a rate which more closely approximates the machine. During normal operation, when the CPU provides the address of the information to be accessed, control circuits perform a search of a directory which stores associative addresses for specifying which blocks of information reside in cache (i.e., define hit condition). When it determines that the information resides in cache, the information is accessed and transferred to the CPU. When the requested information is not in cache, the control circuits request the information from main memory and upon its receipt write the information into cache at which time it may be accessed.
Examples of such systems are disclosed in the referenced patent applications of Charles P. Ryan and in U.S. Pat. No. 3,588,829.
It has been recognized that the limiting factor for the rate at which cache accesses take place is the time required to perform a directory search. In general, an entire cache cycle of operation is required to determine whether the requested information is in cache (i.e., make a directory access and compare associative addresses).
In the case of a hit condition indicating the information to be fetched or updated is in cache, further access is required for completing the processor operation of either accessing operand data or writing data into the cache. Since the cache memory data must be processed on a real time basis and instruction accesses must be made from cache, the writing of memory data and instruction accesses normally interfere with such operations. To overcome such interference, prior art arrangements hold up processor operations until the memory data is written into cache or instructions are accessed. This has been found to limit the overall access rate of the CPU resulting in a decrease in CPU performance.
Accordingly, it is a primary object of the present invention to provide a cache arrangement which provides a central processing unit with rapid access to information.
It is a more specific object of the present invention to provide a cache arrangement which eliminates the interference between the different types of operations required to be performed.
SUMMARY OF THE INVENTION
The above and other objects are achieved in a preferred embodiment of the cache arrangement of the present invention. The cache arrangement includes a high speed storage unit (cache) which is organized into a plurality of levels. Each level includes a number of multiword blocks and the cache unit further includes a multiposition address selection switch, an address register and control circuits.
The address switch is connected to receive address signals from a plurality of address sources. The cache arrangement further includes directory and timing circuits. The directory is organized into a plurality of levels for storing address information for accessing the blocks stored within the levels of cache. The timing circuits generate timing signals for defining first and second intervals of a cache cycle.
The control circuits which are connected to the timing circuits generate output signals for controlling the operation of the address selection switch. In operation, during the second interval of a cache cycle, the control circuits, in response to timing signals from the timing circuits, generate signals for loading the address from one address source into the address register. This enables either the accessing of instructions from one of the levels of cache or the writing of memory information data during the first interval of the following cache cycle.
Also, during the first interval, the address selection switch selects an address from another address source which is clocked into the address register. This enables processor operations such as the accessing of operand data or the writing of CPU/processor data to be performed during the second interval of the same cache cycle.
It will be appreciated that for efficient processing, the information requested to be accessed, resides in cache. This results in a high hit ratio wherein the majority of cache accesses normally will be for instructions. Therefore, it is important that the accessing of instructions not interfere with the accessing of operand data. Accordingly, when a request for an instruction is received, it can be accessed and transferred to the processor during the first interval of the same cycle that an operand requested by the processor is accessed and transferred. This eliminates any interference or conflicts arising from having to access instructions and also transfer operands. More importantly, such conflicts are eliminated without decreasing processor performance. This is particularly desirable in cache organizations wherein accesses proceed on a single word basis rather than on a block basis.
Additionally, it is desirable to be able to write memory data transferred on a real time basis. Accordingly, when memory data is received, it can be immediately written into cache during the first interval of the same cycle that an operand requested by the processor is accessed and transferred to the processor. This eliminates any interference or conflicts arising from having to write memory data and also transfer processor operands.
In the case of accessing instructions, the source of addresses is an instruction address register. When there is no need to write memory data, the control circuits select as the source of addresses the instruction register whose contents specify the address of the next instruction to be fetched from cache. When memory information/data is to be written, the source of addresses is a buffer. In such cases, the control circuits select as the source of addresses, the buffer whose contents specify the address in cache where the requested memory information is to be stored.
The source of addresses for processor operations is a register containing an address received from the processor. During a previous cache cycle, the directory is searched to determine whether the information specified by the same address resides in cache. The results of the directory search are processed during the second half of the next cache cycle as described above utilizing the stored processor address. By controlling the address switch to select different sources of addresses during the first and second intervals of a cache cycle, the cache arrangement of the present invention eliminates the kinds of interference from the number of competing sources/activities described above.
The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying drawings. It is to be expressly understood, however, that each of the drawings is given for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates in block form a system employing the principles of the present invention.
FIG. 2 shows in block diagram form the host processor 700 and the cache unit 750 of FIG. 1.
FIGS. 3a through 3e show in greater detail, certain ones of blocks of FIG. 2.
FIG. 4 shows in block diagram form the cache unit 750 of FIG. 2.
FIG. 5 shows in greater detail, the cache processor interface 604.
FIG. 6a illustrates the format of the control store control unit of FIG. 1.
FIG. 6b illustrates the format of the microinstruction words of the execution control store of FIGS. 2 and 3.
FIGS. 7a through 7e show in greater detail, different ones of the sections of cache unit 750.
FIG. 8 is a timing diagram used in explaining the operation of a preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
General Description
As seen from FIG. 1, the system which incorporates the principles of the present invention includes at least 1 input/output processor (IOPP) 200, a system interface unit (SIU) 100, a high-speed multiplexer (HSMX) 300, a low-speed multiplexer (LXMX) 400, a host processor 700, a cache memory 750, at least one memory module corresponding to a local memory module 500, and at least one memory module corresponding to a memory module 800. Different ones of these modules connect to one of a number of ports of the system interface unit 100 through a plurality of lines of different types of interfaces 600 through 604. More specifically, the input/output processor 200, the cache memory 750, and the high-speed multiplexer 300 connect to ports G, E and A, respectively, while the low-speed multiplexer 400, local memory module 500, and main memory module 800 connect to ports J, LMO and RMO, respectively. The host processor 700 connects to the cache memory 750.
SYSTEM INTERFACES
Before describing in detail the processor 700 and cache unit 750, constructed in accordance with principles of the present invention, each of the interfaces 600 through 604 discussed previously will not be described.
The data interface 600 which is one of the interfaces which provides for exchange of information between an active module and system interface unit 100. Exchange is accomplished by controlling the logical states of various signal lines in accordance with pre-established rules implemented through a sequence of signals termed a "dialog".
The interface 601 is a programmable interface which provides for transfer of command information from an active module and a designated module. The transfer is accomplished by controlling the logic of states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed a "dialog".
A further interface is the interrupt interface 602 which provides for interrupt processing by the input/output processor 200. That is, the interface enables the transfer of interrupt information by an active module to the SIU 100 to the input/output processor 200 for processing. Similar to the other interfaces, the transfer of interrupt requests is accomplished by controlling the logical states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed a "dialog".
A next set of interface lines utilized by certain ones of the modules of FIG. 1 corresponds to the local memory interface 603. This interface provides for exchanging information between local memory 500 and the modules of the system. The exchange is accomplished by controlling logical states of the various signal interface lines in accordance with pre-established rules implemented through a dialog sequence of signals.
Memory and programmable interface commands are transferred out of the same physical data lines of the interface. The interface does not include a set of lines for processing interrupt requests and therefore the modules connected to the local memory by the SIU 100 cannot directly cause a memory interrupt.
For a more detailed description of the elements of FIG. 1 and each of the interfaces 600 through 603, reference may be made to U.S. Pat. No. 4,006,466.
The last interface 604 is an internal interface between the cache unit 750 and central processor 700 which corresponds to the cache/CPU interface lines of FIG. 5. This interface provides for exchanging information and control signals between the processor 700 and the cache unit 750. The exchange is accomplished by controlling the logical states of the various signal interface lines. The cache/CPU interface includes a plurality of data to processor lines (ZDI 0-35, P0-P3), a plurality of ZAC and write data lines (ZADO 0-23, RADO 24-35, P0-P3), a processor request signal line (DREQ-CAC), a plurality of cache command lines (DMEM 0-3), a hold cache line (HOLD-C-CU), a cancel line (CANCEL-C), a flush line (CAC-FLUSH), a read word line (RD-EVEN), a read instruction buffer line (RD-IBUF), a read double (FRD-DBLE), an odd line (FODD), a plurality of instruction lines (ZIBO-35, P0-P3), a control line (DSZ), a read I-buffer data line (RD-IBUF/ZDI), a plurality of zone bit lines (DZD 0-3), a bypass cache line (BYP-CAC), a write signal line (WRT-SGN), an instruction buffer empty line (IBUF-EMPTY), an instruction buffer ready line (IBUF-RDY), an instruction buffer full line (IBUF-FULL), a CP stop line (CP-STOP), a CP control line (DATA-RECOV), a descriptor control line (FPIM-EIS), a transfer no-go line (NO-GO) and a plurality of word address lines (ZPTROUTO-1).
Instructions, cache commands and data are forwarded to the cache unit 750 via different ones of these lines. Additionally, the operation of the processor 700 is enabled or disabled by certain ones of these lines as explained herein. The description of the CPU/cache interface lines are given in greater detail herein.
GENERAL DESCRIPTION OF PROCESSOR 700-FIG. 2
Referring to FIG. 2, it is seen that the host processor 700 includes an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit (AACU) 722, a multiply-divide unit 728, which are interconnected as shown. Additionally, the control unit 704 has a number of interconnections to the cache unit 750 as shown.
The execution control unit 701 includes an execution control store address preparation and branch unit 701-1, and an execution control store 701-2. The store 701-2 and unit 701-1 are interconnected via buses 701-3 and 701-6 as shown.
The control unit 704 includes a control logic unit 704-1, a control store 704-2, an address preparation unit 704-3, data and address output circuits 704-4, an XAQ register section 704-5 which interconnect as shown.
As seen from FIG. 2, the SIU interface 600 provides a number of input lines to the cache unit 750. The lines of this interface have been described in detail previously. However, in connection with the operation of cache unit 750, certain ones of these lines are specially coded as follows.
1. MITS 0-3 for Reads are coded as follows:
bits 0-1=00;
bits 2-3=Transit block buffer address containing the ZAC command for current read operation.
For Write Operation bit 0-3=Odd word zone
2. MIFS lines are coded as follows:
bit 0=0;
bit 1=0 even word pairs (words 0,1);
bit 1=1 odd word pairs (words 2,3);
bits 2-3=Transit block buffer address containing the ZAC command for the data being received.
As concerns the interface lines DFS 00-35, P0-P3, these lines convey read data to cache unit 750. The lines DTS 00-35, P0-P3 are used to transfer data and commands from cache 750 to the SIU 100.
The control unit 704 provides the necessary control for performing address preparation operations, instruction fetching/execution operations and the sequential control for various cycles of operation and/or machine states. The control is generated by logic circuits of block 704-1 and by the execution control unit 701 for the various portions of the control unit 704.
The XAQ register section 704-5 includes a number of program visible registers such as index registers, an accumulator register, and quotient register. Other program visible registers, such as the instruction counter and address registers, are included within the address preparation unit 704-3.
As seen from FIG. 2, the section 704-5 receives signals from unit 704-3 representative of the contents of the instruction counter via lines RIC 00-17. Also, lines ZRESA 00-35 apply output signals from the execution unit 714 corresponding to the results of operations performed upon various operands. The section 704-5 also receives an output signal from the auxiliary arithmetic and control unit via lines RAAU0-8.
The section 704-5 provides signals representative of the contents of one of the registers included within the section as an input to the address preparation unit 704-3. The address preparation unit 704-3 forwards the information through a switch to the execution unit 714 via the lines XDO 0-35. Similarly, the contents of certain ones of the registers contained within section 704-5 can be transferred to the execution unit 714 via the lines ZEB 00-35. Lastly, the contents of selected ones of these registers can be transferred from section 704-5 to the multiply/divide unit 728 via the lines ZAQ 00-35.
The address preparation unit 704-3 generates addresses from the contents of various registers contained therein and applies the resultant logical, effective and/or absolute addresses for distribution to other units along the lines ASFA 00-35. The address preparation unit 704-3 receives the results of operations performed on a pair of operands by the execution unit 714 via the lines ZRESB 00-35. The unit 704-3 receives signals representative of the contents of a pair of base pointer registers from the control logic unit 701 via the lines RBASA and RBASB0-1. Outputs from the multiply/divide unit 728 are applied to the address preparation unit 704-3. Lastly, the contents of a secondary instruction register (RSIR) are applied as input to the unit 704-13 via the lines RSIR 00-35.
The data and address output circuits 704-4 generate the cache memory address signals which it applies to the cache unit 750 via the lines RAD0/ZAD0 00-35. These address signals correspond to the signals applied to one of the sets of input lines ZDI 00-35, ASFA 00-35 and ZRESB 00-35 selected by switches included within the circuits of block 704-4. These circuits will be further discussed herein in greater detail.
The control logic unit 704-1 provides data paths which have an interface with various units included within the cache unit 750. As described in greater detail herein, the lines ZIB 00-35 provide an interface with an instruction buffer included within the cache 750. The lines ZDI 00-35 are used to transfer data signals from the cache 750 to the control logic unit 704-1. The ZPTROUT lines are used to transfer address information from cache 750 to unit 704-1. Other signals are applied via the other data and control lines of the cache-CP4 interface 604. These lines include the CP-STOP line shown separately in FIG. 2.
As seen from FIG. 2, the control logic unit 704-1 provides a number of groups of output signals. These output signals include the contents of certain registers, as for example, a basic instruction register (RBIR) whose contents are applied as an input to control store 704-2 via the lines RBIR 18-27. The control logic unit 704-1 receives certain control signals read out from control store 704-2 via the lines CCSD0 13-31.
The control logic unit 704-1 also includes a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of processing an instruction. The contents of the secondary instruction register RSIR 00-35, as previously mentioned, are applied as inputs to the address preparation unit 704-3. Additionally, a portion of the contents of the secondary instruction register are applied as inputs to the auxiliary arithmetic control unit 722 via the lines RSIR 1-9 and 24-35.
The control store 704-2 as explained herein provides for an initial decoding of program instruction op-codes and therefore is arranged to include a number of storage locations (1024), one for each possible instruction op-code.
As mentioned, signals applied to lines RBIR 18-27 are applied as inputs to control store 704-2. These signals select one of the possible 1024 storage locations. The contents of the selected storage location are applied to the lines CCSD0 13-31 and to CCSD0 00-12 as shown in FIG. 2. The signals supplied to lines CCSD0 00-12 correspond to address signals which are used to address the execution control unit 701 as explained herein.
The remaining sections of processor 700 will now be briefly described. The execution unit 714 provides for instruction execution wherein unit 714 performs arithmetic and/or shift operations upon operands selected from the various inputs. The results of such operations are applied to selected outputs. The execution unit 714 receives data from a data input bus which corresponds to lines RDI 00-35 which have as their source the control logic unit 704-1. The contents of the accumulator and quotient registers included within section 704-5 are applied to the execution unit 714 via the lines ZEB 00-35 as mentioned previously. The signals applied to the input bus lines ZDO 00-35 from the address preparation unit 704-3 are applied via switches included within the execution unit 714 as output signals to the lines ZRESA 00-35 and ZRESB 00-35, as shown in FIG. 2. Additionally, execution unit 714 receives a set of scratch pad address signals from the auxiliary arithmetic and control unit 722 applied via the lines ZRSPA 00-06. Additionally, the unit 722 also provides shift information to the unit 714 via the lines ZRSC 00-35.
The character unit 720 is used to execute character type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructions are referred to as extended instruction set (EIS) instructions. Such instructions which the character unit 720 executes include the move, scan, compare type instructions. Signals representative of operands are applied via lines ZRESA 00-35. Information as to the type of character position within a word and the number of bits is applied to the character unit 720 via the input lines ZDB 00-07.
Information representative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes exponent data and data in hexadecimal form. The character unit 720 applies output operand data and control information to the unit 722 and the unit 728 via the lines RCHU 00-35.
The auxiliary arithmetic and control unit 722 performs arithmetic operations upon control information such as exponents used in floating point operations, calculates operand lengths and pointers and generates count information. The results of these operations are applied to execution unit 714 via the lines ZRSPA 00-06 and lines ZRSC 00-06 as mentioned previously. Information signals corresponding to characters such as 9-bit characters, 6-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are applied to section 704-5 via the lines RAAU 00-08.
As seen from FIG. 2, the unit 722 receives a number of inputs. Character pointer information is applied via the lines ASFA 33-36. EIS numeric scale factor information and alphanumeric field length information are applied to the unit 722 via the lines RSIR 24-35. Other signals relating to fetching of specific instructions are applied via the lines RSIR 01-09. Exponent signals for floating point data are applied to the unit 722 via the lines ZOC 00-08 while floating point exponent data signals from unit 704-1 are applied via the lines RDI 00-08. Shift count information signals for certain instructions (e.g. binary shift instructions) are applied to the unit via the lines RDI 11-17. As concerns the input signals applied to the lines RCHU 00-35, lines 24-35 apply signals corresponding to the length of EIS instruction fields while 18-23 apply address modification signals to the unit 722.
The last unit is the multiply/divide unit 728 which provides for high-speed execution of multiply and divide instructions. This unit may be considered conventional in design and may take the form of the multiply unit described in U.S. Pat. No. 4,041,292 which is assigned to the same assignee as named herein. The unit 728 as seen from FIG. 2 receives multiplier dividend and divisor input signals via the lines RCHU 00-35. The multiplicand input signals from register section 704-5 are applied via the lines ZAQ 00-35. The results of the calculations performed by the unit 728 are applied as output signals to the lines ZMD 00-35.
As mentioned previously, the cache unit 750 transfers and receives data and control signals to and from the SIU 100 via the data interface line 600. The cache unit 750 transfers and receives data and control signals to and from the processor 700 via the lines of interface 604. Lastly, the cache unit 750 receives address and data signals from the circuits 704-4 via the lines RAD0/AZD0 00-35.
DETAILED DESCRIPTION OF THE PROCESSOR 700
Certain ones of the sections which comprise the processor 700 illustrated in FIG. 2 will now be discussed in greater detail with respect to FIGS. 3a through 3e.
Referring to FIGS. 3a and 3b, it is seen that the processor includes two control stores: (1) the control unit control store (CCS) 704-200 mesh forms part of the control unit 704; and (2) the execution control store (ECS) 701-3 which is included within the execution control unit 701.
The cache oriented processor 700 of the preferred embodiment of the present invention includes a three stage pipeline. This means that the processor 700 requires at least three processor cycles to complete the processing of a given program instruction and can issue a new instruction at the beginning of each cycle. Hence, a number of program instructions may be in some stage of processing at any given instant of time.
In the preferred embodiment of the processor 700 includes the following stages: an instruction cycle (I) wherein instruction interpretation, op-code decoding and address preparation take place; a cache cycle (C) wherein access to the cache unit 750 is made ensuring high performance operation; and, an execution cycle (E) wherein instruction execution takes place under microprogram control.
As concerns control, during the I cycle, the op-code of the instruction applied via lines RBIR 18-27 is used to access a location within control store 704-2. During a C cycle, the accessed contents from control store 704-2 are applied to lines CCS D0 00-12 and in turn used to access one of the storage locations of the execution control store 701-2. During the C cycle, the microinstructions of the microprogram used to execute the instruction are read out from the execution control store 701-2 into a 144-bit output register 701-4. The signals designated MEMD0 00-143 are distributed to the various functional units of processor 700. During an E cycle, the processor executes the operation specified by the microinstruction.
Referring specifically to FIG. 2, it is seen that the control store 704-2 includes a control unit control store (CCS) 704-200 which is addressed by the op-code signals applied to the lines RBIR 18-27. The CCS 704-200, as mentioned previously, includes 1024 storage locations, the contents of which are read out into an output register 704-202 during an I cycle of operation. FIG. 6a shows schematically the format of the words stored within the control store 704-200.
Referring to FIG. 6a, it is seen that each control unit control store word includes five fields. The first field is a 13-bit field which contains an ECS starting address location for the instruction having an op-code applied to lines RBIR 18-27. The next field is a three bit field (CCS.phi.) which provides for the control of certain operations. The bit interpretations of this field depend upon its destination and whether it is decoded by specific logic circuits or decoded under microprogram control. The next field is a 4-bit field which provides for certain register control operations.
The next field is a 6-bit sequence control field which is coded to specify a sequence of operations to be performed under hardwired logic circuit control as well as the type of cache operation. In the present example, this field is coded as 75.sub.8. The last field is a 6-bit indicator field which is not pertinent to an understanding of the present invention.
As seen from FIG. 3a, signals corresponding to the CCSA field of a control unit control store word are applied via a path 704-204 as an input to the execution generation circuits 701-7. Signals corresponding to the CCSR field are applied as an input to the execution unit 714 via path 704-206. Additionally, the same signals are applied as an input to the address preparation unit 704-3 via another path 704-208.
Signals representative of the sequence control field apply as an input to the sequence control logic circuits 704-100 via path 704-210. As explained herein, these circuits decode the sequence control field and generate signals for conditioning the cache unit 750 to perform the operation designated.
As mentioned, the execution address generation circuit 701-1 receives an input address which corresponds to field CCSA from the control store 704-2. As seen from FIG. 3b, these circuits include an input address register 701-10 whose output is connected to one position of a four position switch 701-12 designated ZECSA. The output of the switch serves as an address source for the control store 701-2. The first position of the switch 701-12 is connected to receive an address from the MICA register 701-14. The contents of register 701-14 are updated at the end of each cycle to point to the location within the ECS control store following the location whose contents were read out during that cycle.
The second position selects the address produced from the ZCSBRA branch address selector switch 701-18. The third position selects the address of the first microinstruction in each microprogram provided by the CCS control store which is loaded into the REXA register 701-10. When the CCS output is not available at the termination of a microprogram, a predetermined address (octal address 14) is automatically selected.
The first position of branch switch 701-18 receives signals corresponding to a branch address read out from store 701-2 into register 701-4 which is in turn forwarded to a return control register 701-20. The second, third and fourth positions of switch 701-18 receives signals from RSCR register 701-20, an MIC register 701-15 and the contents of a number of vector branch registers 701-36. The MICk register 701-15 stores an address which points to the microinstruction word following the microinstruction word being executed. This address corresponds to address from switch 701-12 incremented by one by an increment circuit 701-12.
The vector branch registers include a 4-bit vector branch register 0 (RVB0), a 2-bit vector branch register 1 (RVB1) and a 2-bit vector branch register 2 (RVB2). These registers are loaded during a cycle of operation with address values derived from signals stored in a number of different indicator flip-flops and registers applied as inputs to the number of groups of input multiplexer selector circuits 701-32 and 701-34. The outputs of the circuits 701-32 and 701-34 are applied as inputs to two position selector circuits 701-30. These circuits in turn generate the output signals ZVBR0, ZVBR1 and ZVBR2 which are stored in the register 701-36.
The switch 701-36 provides an address based upon the testing of various hardware indicator signals, state flip-flop signals selected via an INDGRP field. The branch decision is determined by masking (ANDING) the selected indicator set with the INDMSKU and INDMSKL fields of a microinstruction word. If a vector branch is selected, INDMSKU is treated as 4 ZERO bits. The "OR" of the 8-bits is compared to the state defined by the TYPG and GO microinstruction fields. The hardware signals are applied via a number of data selector circuits 701-28 only one of which is shown whose outputs are in turn applied as inputs to a further five position multiplexer selector circuit 701-26. The output of the multiplexer circuit 701-26 feeds a comparison circuit which "ands" the indicator signals with the mask signals to produce the resulting signals MSKCBR0-7.
The signals MSKCBR0-7 are applied to another comparison circuit which "ands" the signals with the condition branch test signals TYPGGO to set or reset a branch decision flip-flop 701-22 which produces a signal RBDGO whose state indicates whether branching is to take place. The output signal RBDGO is applied as a control unit to the first two positions of switch 701-12. When the branch test condition is not met (i.e., signal RBDGO=0), then the incremented address from the MICA register 701-14 is selected.
In some instances, as seen herein, it is not possible to test the state of an indicator on the cycle following its formation. For this reason, history registers HR0-HR7, not shown, are provided for register storage of the Group 2 indicators. The states of such stored indicators are selected and tested in a manner similar to that of the other indicators (i.e., mask fields).
Additionally, the unit 701-1 includes a number of indicator circuits, certain ones of these are used to control the operation of certain portions of the processor 700 when the strings being processed by certain types of instructions have been exhausted. These indicator circuits are included in block 701-42 and are set and reset under the control of a field within the microinstruction word of FIG. 6a (i.e., IND6 field). The bits of this field read out from the ECS output register 701-4 are applied to an RMI register 701-38 for decoding by a decoder 701-40. Based upon the state of status indicator signals received from the various processor units (e.g. 714, 720, 722, etc.), the appropriate ones of the auxiliary flip-flops are switched to binary ONE states. The outputs of these flip-flops are applied via the different positions of a 4 position switch 701-44 to the GP3 position of switch 701-26 for testing. The same outputs are applied to a second position of a ZIR switch 701-43 for storage via the ZDO switch 704-340. The ZIR switch 701-43 also receives indicator signals from an indicator register (IR) 701-41. This register is loaded via the RDI lines 18-30 and 32 in response to certain instructions.
The indicator status signals for example include the outputs of different adder circuits (AL, AXP) of the unit 720. These signals will set different ones of a number of exhaust flag flip-flops designated FE11, FE12, FE13, FE1E, FE2E, FE2 and FE3. The FE1E and FE2E flip-flops are set during any FPOA cycle of any instruction. These flip-flops in turn cause the FE11, FE12 and FE13 flip-flops to be set when the outputs from the AL or AXP adder circuits of unit 720. The setting and resetting of these indicators will be described herein in further detail in connection with the description of operation. However, the exhaust flag flip-flops pertinent to the example given herein are set and reset in accordance with the following Boolean expressions.
SET: FE1E=FPOA+IND6FLD field.
RESET: FE1E=IND6FLD field.
SET: FE2E=FPOA+IND6FLD field.
RESET: FE2E=IND6FLD field.
SET: FE11=IND6FLD field.multidot.FE1E (ALES+AXPES+DESC1.multidot.AP0-4=0)+IND6FLD field.multidot.FE1E.multidot.DESCl.multidot.(AP0-5=0+APZN+ALZN)+IND6FLD field.
RESET: FE11=FPOA+IND6FLD field.
SET: FE12=IND6FLD field.multidot.FE1E.multidot.(ALES+AXPES+FE13).
RESET: FE12=FPOA+IND6FLD field.
SET: FE13=IND6FLD field.multidot.FE1E.multidot.ALES+IND6FLD field.
RESET: FE13=FPOA+IND6FLD field.
SET: FE2=IND6FLD field.multidot.FE2E.multidot.ALES+IND6FLD field. FE2E.multidot.DESC2.multidot.(AP0-4=0+AP0-5=0+APZN+ALZN)+(IND6FLD field) FE2E.multidot.DESC2+IND6FLD.
RESET: FE2=FPOA+IND6FLD field.
SET: FE3=IND6FLD field.multidot.DESC3.multidot.(AP0-4=0+AP0-5+APZN+ALZN)+IND6FLD field.multidot.DESC3+IND6FLD.
RESET: FE3=FPOA+IND6FLD field.
Wherein IND6FLD indicates a particular code;
ALES=AL=0 or AL-C;
AXPES=AXP=0 or AXP-C;
APZN=AP0-7.ltoreq.0; and,
ALZN=AL0-11.ltoreq.0.
The ZCSBRA switch 701-18 is normally enabled when the branch decision flip-flop RBD was set to a binary ONE in the previous cycle. The first position selects a 13-bit branch address from the current microinstruction applied via the BC5R register 701-20. The branch address enables any one of the locations of the ECS control store to be addressed directly. The second position selects the concatenation of the 6 low order address bits from the current microinstruction applied via MIC register 701-15 and the 7 upper bits of the branch address from the current microinstruction applied via the RSCR register 701-20. This permits branches within a 64-word page defined by the contents of the MIC register 701-15 (current location+1).
The third position selects the concatenation of 4 low order bits from the RVBO vector branch register, 6 bits from the branch field of the current microinstruction stored in RCSR register and the 3 upper bits of the address stored in the MIC register. This permits 16-way branches. The fourth position selects the concatenation of the 2 low order ZEROS with 4 bits from the vector branch register RVBO with the 4 most significant bits of the branch address field of the current microinstruction and the 3 upper bits of the current address stored in the MIC register. This permits 16-way branches with 3 control store locations between each adjacent pair of destination addresses.
The fifth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register RVB1, with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits branches with 4 possible destinations with 3 control store locations between each adjacent pair of destination addresses.
The sixth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register RVB2 with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits 4-way branches with 3 control store locations between each adjacent pair of destination addresses.
The output of switch 701-12 addresses a specific location within control store 701-2 which causes the read out of a microinstruction word having a format illustrated in FIG. 6b. Referring to that Figure, it is seen that this microinstruction word is coded to include a number of different fields which are used to control the various functional units within processor 700. Only those fields which are related to the present example will be described herein.
CONTROL LOGIC UNIT 704-1
This unit includes the sequence decode logic circuits 704-100 as mentioned whose outputs feed a plurality of I cycle control state flip-flops of block 704-102. These flip-flops in response to signals from the circuits 704-100 as well as microinstruction signals from register 701-4 (DMEMR038-40 which corresponds to the mem address field MEMADR of FIG. 6b) generate the various required I cycle control states required for the execution of program instructions. It is assumed that block 704-102 also includes gate circuits which generate register hold signals (HOLDE00 which are distributed throughout the processor 700.
As seen from FIG. 3c, the I cycle control state flip-flops receive control input signals via control lines including a line CPSTOP00 from cache unit 750. As explained herein, the state of the CPSTOP00 line determines whether processor operation continues in that when the line is forced to a binary ZERO, the hold or enabling signals for the I cycle control state flip-flops and other storage registers are also forced to ZEROS. The hold signals corresponding to signals [HOLDI00 and [HOLDE00 operate to hold or freeze the state of the processor 700. Since no incrementing of the control store address can take, the ECS control store reads out the same microinstruction word. The signals [HOLDI and [HOLDE are set in accordance with the following Boolean expressions: [HOLDI=CACHE HOLD+TERMB (DREQ-IF-DIR)+HOLD REL wherein the state of signal CACHE HOLD corresponds to the state of signal CPSTOP, the states of signals TERMB (DREQ-IF-DIR) are binary ONES during control state FPOA when the cache command specifies an I fetch or direct operation and the signal HOLD REL is a binary ONE until switched to a binary ZERO by the generation of a microprogram release signal; and [HOLD E=[HOLD I.
As seen from FIG. 3c, signals corresponding to the I cycle control states are applied as inputs to a plurality of control flip-flops of block 704-104, decoder circuits of block 704-106, a number of control logic circuits of block 704-108 and to a plurality of control flag indicator flip-flops of block 704-110. It is also seen that the various indicator flip-flops of block 704-110 also receive micorinstruction input signals via lines MEMD054-57 from execution control unit 701-4.
As seen from FIG. 3c, signals generated by the hardware control logic circuits 704-108 fall into one of three groups as a function of the units whose operations are being controlled. That is, the groups are instruction buffer control, hardware control and hardware memory control.
In each case, each group of signals are ored together with equivalent signals generated by other sources and then decoded. The other sources correspond to fields within the two different formats of the microinstruction word of FIG. 6a which are loaded into RCSR register 704-112 from the ECS output register 701-4.
One field corresponds to bits 32-83 of one format (large CU) and another field (short CU) corresponds to bits 32-41 of another format. These fields are decoded by a decoder 704-114 into the sets of bits indicated and combined within the decoders 704-116, 704-124, 704-126 and 704-128 as shown. Further decoding is done by the circuits of blocks 704-118, 704-135 and 704-120. The results of decoding such fields are either distributed throughout processor 700 or are stored in an RMEM register 704-130, an RSZ flip-flop 704-132, an FREQDIR flip-flop 704-136 and an FREQCAC flip-flop 704-134.
Additional decoding of the large and short CU fields and signals from the I cycle state circuits of block 704-112 is done via a decoder 704-106 and 704-107. The decoder 704-106 generates control signals for loading different ones of the registers and for enabling various multiplexer/selector switches within the processor 700. The decoder 704-107 operates to generate signals for setting and resetting a pair (RBASB) of base pointer B flip-flops 704-144. Other combinations of these signals are used to set and reset the descriptor number flip-flops of blocks 704-140 and 704-142.
As seen from FIG. 3c, the decoder 704-116 receives a control signal [EXH00 generated by the decoder circuits of block 704-117. These circuits receive signals from the RDESC register 704-140 and signals from the exhaust flip-flops of block 701-1. In accordance with the states of these signals, the circuits force signal [EXH000 to a binary ZERO to inhibit the generation of a cache memory command upon the occurrence of an exhaust condition. The signal [EXH000 is generated in accordance with the following Boolean expression:
The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word. When set to a binary ONE, this indicates that the descriptor being processed is a numeric type.
The different flip-flops of block 704-104 will now be discussed in greater detail. In greater detail, the flip-flop FCHAR provides certain changes in the control of address generation. When the FCHAR flip-flop is set to a binary ONE during the processing of a load type instruction specifying character modification, then the contents of the RDI register is not changed under hardware contro. This allows the RDI register to be loaded with data under microprogram control prior to starting the pipeline. Also, if the FCHAR flip-flop is set to a binary ONE during a store type instruction specifying character modification, then the execution address for this instruction is modified under hardware control to point to a unique address of the microinstruction sequence in the ECS control store that is to process this type of instruction.
The flip-flop FDT-FOUR provides additional control on the readout of the address register (ZAR.sub.0-19) of block 704-304. Flip-flop FADR-WD provides additional control for the ZDO switch 704-340. When this flip-flop is set to a binary ONE, then the ZAR position of the ZDO switch is forced to select a word address. The flip-flop FADR-B provides additional control for the ZDO multiplexer switch. When set to a ONE, then the ZAR position of the ZDO switch is forced to select a byte address. The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word. When set to a binary ONE, this indicates that the descriptor being processed is a numeric type. The flip-flop FIG-LEN provides additional control over the loading of registers within the unit 722 (length registers) and over memory operations. When set to a binary ONE, the RXP and RLN registers within unit 722 are not loaded from the RSIR register 704-154 during certain processor control states FPOP.
The FINH-ADR flip-flop inhibits the operation of the address preparation unit 704-3. When set to a binary ONE, an address cycle (FPOA/FPOP) consists of adding the contents of a temporary effective address register REA-T+ZERO. The register REA-T will have been loaded with the address prior to doing a FPOA/FPOP cycle. The FABS flip-flop enables the generation of absolute addresses. When set to a binary ONE, a 24-bit absolute address is used. As concerns the flag or indicator flip-flops of block 704-110, flip-flop FID when set to a binary ONE provides an indication that indirect address modification during an instruction is required on the descriptor loaded into the RSIR register.
The FRL flip-flop when set to a binary ONE indicates that the length is specified in a register associated with the instruction loaded into various instruction registers. The three flip-flops FINDA, FINDB and FINDC provide indications used in processing memory type instructions. Flip-flop FINDA is set to a binary ONE when length is specified in a register or when flip-flop FAFI is set to a ONE. Flip-flop FINDB is set to a binary ONE when the descriptor does not include nine bit characters. The flip-flop FINDC is set to a binary ONE when the descriptor does include six bit characters.
The FAFI flip-flop is set to a binary ONE when the processor circuits detect that indicator bit 30 of IR register 701-41 was set to a binary ONE during the execution of an EIS instruction indicative of a mid instruction interrupt (required to adjust pointer and length values because of interrupt). The FTRGP, TTNGO and FTRF-TST flip-flops are set to binary ONES in conjunction with transfer type instructions. More specifically, the FTRGP flip-flop provides a microprogram indication of being set to a binary ONE when the processor circuits detect the read out of a transfer type of instruction during the execution of an execute double (XED) or repeat (RPTS) instruction. The FTNGO flip-flop provides a microprogram indication of being set to a binary ONE when the condition of transfer signalled by the execution control unit 701 was transfer NO GO (i.e., transfer did not take place). The output of this flip-flop is applied to the NO GO line of interface 604. The FTRF-TST flip-flop of this group indicates when set to a binary ONE that the previous instruction executed by processor 700 was a transfer type instruction and that the curret I cycle is to be executed conditioned upon the presence of a transfer GO (TRGO) signal from control unit 701.
Additionally, the circuits of block 704-110 include a number of flip-flops used in performing indirect addressing operations under hardwired control for other than EIS instructions. These include FIR, FIRT, FIRL and FRI flip-flops which are switched to binary ONES as functions of the different types of indirect address modifications required to be performed. For example, the FRI flip-flop signals a register then indirect address modification and is switched to a binary ONE when a register indirect (RI) indicator is a binary one. The FIR flip-flop is switched to a binary ONE when an indirect then register (IR) indicator is a binary ONE. This flip-flop signals the beginning of an indirect then register address modification. The FIRL flip-flop is switched to a binary ONE when an indirect then tally indirect (IT-I) indicator is a binary ONE. This flip-flop signals a last indirect operation. Another flip-flop TSX2 provides an indication used in processing transfer and set index instructions while a STR-CPR flip-flop is used during the processing of store instructions.
As seen from FIG. 3c, the outputs from the control flag flip-flops of block 704-110 are applied as inputs to the branch indicator circuits of block 701-1. Also, output signals from the control flag flip-flops are also applied as inputs to the I cycle flip-flops of block 704-102.
REGISTER SECTION 704-150
As seen from FIG. 3c, the control logic unit 704-1 further includes a register section 704-150. This section contains the basic instruction register (RBIR) 704-152, the secondary instruction register (RSIR) 704-154, a base pointer A register (RBASA) 704-156 used for selecting one of the address registers RAR0 through RAR7 of block 704-304, a read index register A (RRDXA) 704-158 used for selection of index registers included within section 704-5 (not shown) and for selection of outputs from the ZDO multiplexer switch 704-340, a read index A save (RRDXAS) register 704-159, and a descriptor type register (RTYP) 704-160 indicating the type of data characters being pointed to by the descriptor value (e.g. 9-bit, 6-bit, 4-bit). The section 704-150 further includes a 1-bit instruction/EIS descriptor register designated R29 of block 704-162. The state of this bit in conjunction with the contents of the RBAS-A register 704-158 are used to select the particular address register used for address preparation. When register R29 of block 704-162 is set to a binary ZERO, this indicates that none of the address registers of block 704-304 are used during address preparation. The last registers of section 704-150 include the data in register (RDI) of block 704-164 and a read index register B (RRDXB) pointing to registers used by execution unit 714.
As seen from FIG. 3c, the RBIR register 704-152 is loaded via a two position switch 740-170 connected to receive signals from the sources indicated (i.e., a switch ZIB-B 704-172 and lines ZDI 0-35). The RSIR register 704-154 similarly receives signals from the ZDI lines and switch 704-172. The RBASA register 704-156 receives signals from the ZDI line 0-2 in addition to a further switch ZBASA of block 704-174. The RRDXA register and RTYP register receive signals from the ZDI lines as well as a switch 704-176 and 704-178 as shown. Also, the RRDXA register receives signals from the RRDXAS register 704-159.
The switch 704-172 is a two position switch which receives inputs from the switches ZIB and ZRESB from the cache unit 750 and execution unit 714 respectively. The switch 704-174 is a three input switch which receives two inputs from the execution units 714 and the output of the ZIB switch of cache unit 750.
Switch 704-176 is a four input switch which receives two of its inputs from the execution unit 714 and a single input from cache unit 750. The first position of the ZRDXA switch 704-176 selects the output of a ZRDXM switch 704-185. One position of this switch provides a tag field value from bit positions 5-8, 14-17, and 32-35 of the RBIR register 704-152 and bit positions 32-35 of the RSIR register 704-154 selected from ZIDD switch 704-180 and a two position ZMF switch 740-176.
The second position of switch 704-185 provides a constant value from the output of the ECS output register 704-1 (CCM field 32-34). The signals from the lines ZIDD 27-35 are applied as inputs to control flag flip-flops of block 704-110. The switch 704-178 receives an input from the control store 704-2, an input from cache unit 750 and an input from execution unit 714.
The data input register 704-164 receives a series of input signals from a ZIDD switch 704-180 which connects in series to a ZDIA switch 704-181 whose output provides one input of a further switch 704-182 which directly loads into the RDI register 704-164. The ZDIA switch 704-181 provides a further input to a three input switch 704-183 which receives the other inputs indicated from cache unit 750 and execution unit 714.
The ZIDD switch 704-180 receives an effective address via switch 704-186 from the address preparation unit 704-3 as well as inputs from the RBIR register 704-152, the RSIR register 704-154 and a two position ZMF switch 704-187. The positions 18 through 35 of the REA position of switch 704-180 are derived from the ZDIA switch 704-181 as shown. The ZDIA switch 704-181 receives signals from the ZDI lines 0-35, a constant value generated from the inputs to a first switch position in addition to signals from the output of the ZIDD switch 704-80 and the ZRESB switch in execution unit 714. The switch 704-182 receives the output of the ZDIA switch and signals from the ZDI lines 0-35. The RRDXB register 704-189 is loaded by a three position switch 704-188. The switch receives via a first position signals from a RREG register included in the execution unit, a constant value from control store 701-2 via a second position and signals from the ZIDD switch via a third position.
The section 704-150 further includes a two position switch 704-185 and a scratchpad pointer register 704-186 whose output is used by the AACU 722 to form addresses for access to the scratchpad memory of the EU 714. The first switch position provides a constant value and is selected under hardware control (FPOA.R29). The second switch position applies as an output the contents of the RBASA register 704-156. This position is selected under both hardware and microprogram control (i.e., FPOA.R29 or MISCREG field).
It will be appreciated that the required timing signals for operating section 704 as well as other sections of processor 700 and cache unit 750 are provided by centrally located clock circuits. For example, in the preferred embodiment of FIG. 1, the clock circuits are located within the input/output processor system. Such clock circuits can be considered as conventional in design and can comprise a crystal controlled oscillator and counter circuits. The timing or clocking signal from such clock circuits are distributed in a conventional manner to the various portions of the system of FIG. 1 for synchronized operation. From such timing signals, circuits within processor 700 derive additional clocking signals as required. This will be described in greater detail with respect to the cache unit 750 of FIG. 4.
ADDRESS PREPARATION UNIT 704-1
The address preparation unit 704-3 includes a number of registers and adders. The registers include a number of base registers (i.e., TBASE0 through TBASEB) of block 704-300 used for storing descriptor values of an instruction, a pair of temporary effective address registers (TEA0, TEA1) and a pair of instruction counters (ICBA, ICBB) included within block 704-302 used for addressing the instruction buffer and eight address registers (RAR0 through RAR7) of 704-304 used during address preparation operations. The unit 704-3 also includes an instruction counter 704-310.
The adders include adder 704-312 used to update instruction counter 304-310 via switches 704-311 and 704-314 and a pair of adders 704-320 and 704-322. The adder 704-322 is used to generate an effective address value which is stored in a register 704-342 applied as an input of the control unit 704-1. The effective address is generated from a number of sources which include ZY switch 704-326 whose output is applied via a number of AND gates of block 704-327, selected address registers of block 704-304 or selected temporary address registers TEA0 and TEA1 of block 704-302 applied via another switch 704-328 or the index address signals ZX0-20 from unit 704-5. Additionally, adder 704-322 is used to update the contents of the instruction counter of the cache instruction buffer.
As seen from FIG. 3d, the outputs from adder 704-322 are also applied as an input to the adder 704-320. The adder 704-320 is used to combine base value stored in any one of the temporary base registers TBASE0 through TBASEB with the address signals ACSOS0:-19 from adder 704-322. The resulting bits are applied as an input to a further adder network 704-320 which generates a logical address which is applied to the lines ASFA0-36 via an adder 704-321. This adder sums the operand inputs together with the carry inputs from blocks 704-300 and 704-320. The effective address is used to obtain an absolute address when the system is operated in a paged mode. Since this operation is not pertinent to the present invention, it will now be discussed further herein. For further information regarding such address development, reference may be made to U.S. Pat. No. 3,976,978.
The temporary base registers of block 704-300 are loaded via a switch 704-332. The switch receives an input from the execution unit 714 and the output from block 704-300. The execution unit 714 applies further inputs to the registers of block 704-302 via a switch 704-334 as well as to the address registers of block 704-304. An output multiplexer (ZDO) switch 704-340 enables the selection of the various registers within the address preparation unit 704-3 and unit 704-5 for transfer of their contents to the execution unit 714 via lines ZDO 0-35. Also, the ZDO switch 704-340 enables the contents of various ones of the registers and control flip-flops of unit 704-1 to be read out via a fourth position (ZDO-A). The fifth position enables the states of various indicators within the control store circuits of block 701-1 to be selected for examination.
DATA/ADDRESS OUTPUT SECTION 704-4 FIG. 3e
The section 704-4 includes the registers and switches used for transferring commands and data to the cache 750. Such transfer operations normally require at least two cycles, one for sending an address and another for sending the data. Bits 5-8 of a command word are derived from the output of a four position switch 704-40. This switch receives a first constant value via a first position, the contents of a RZN register 704-42 via a second position, a second constant value via a third position and a third constant value via a fourth position.
Bits 1-4 of a command are applied by the circuits of block 704-1 to an OR gate circuit 704-44 together with bits 5-8. The OR gate 704-44 also receives via a ZADO switch 704-46 bits 1-8 of an RADO register 704-48. The RADO register 704-48 is an address and data out register which receives via a first position of a ZADOB switch 704-48 a logical (virtual) address from address preparation unit 704-3 via the lines ASFA0-35 and data output signals from the EU 714 via lines ZRESB0-35. The positions of the ZADOB switch 704-48 is under the control of the FMTD field for small CU format and the RADO field in the case of large CU format.
As seen from the Figure, either the ZZN1-8 bits or the ZADO bits 1-8 are applied as outputs to the RADO/ZADO lines as a function of the state of control signal [RADO-ZADO. Bits O and I are always binary ONES while bits 10-35 are furnished by the RADO register 704-46.
For additional information regarding the remaining sections of processor 700 as well as the sections of FIGS. 3a through 3e, reference may be made to the copending applications referenced in the introductory portion of this application.
CACHE UNIT 750--FIG. 4
General Description
The cache unit 750 is divided into five primary sections: a transit buffer and command queue section 750-1 a cache section 750-3, a directory and hit control section 750-5, an instruction buffer section 750-7 and an instruction counter section 750-9.
Transit Buffer and Command Queue Section 750-1
The transit buffer and command queue section 750-1 includes as major elements a four word write command buffer 750-100 and a four word transit block buffer read command buffer 750-102 which are addressed via a pair of counter circuits 750-104 and 750-106 in addition to a command queue 750-107 with associated in and out address pointer and compare circuits of blocks 750-108 through 750-110. The write buffer 750-100 provides storage for two write single or one write double command while the transit block 750-102 provides storage for up to four read type commands. The transit block buffer 750-102 also stores information associated with such read commands used in controlling the writing of memory data words into assigned areas (i.e., levels) of cache section 750-3. The four registers allow up to four memory reads to be in progress at any given time.
Section 750-1 also includes a control section 750-112. This section includes sets of different control circuits such as the command decoder and control circuits of blocks 750-113 and 750-114, the interface control circuits of blocks 750-115 and 750-116 and hold control circuits of blocks 750-117.
The circuits of blocks 750-113 and 750-114 decode the signals applied to the DMEM lines representative of commands transferred by processor 700 via the RADO/ZADO lines of interface 604 and generate the control signals for making entries in the command queue 750-107, incrementing the setting values into the in pointer and out pointer circuits of blocks 750-108 and 750-109. Also, the circuits generate control signals for storing commands into either write buffer 750-100 or transit block buffer 750-102.
The interface control circuits of blocks 750-115 and 750-116 generate signals for controlling the transfer of data signals received from SIU 100 into section 750-7 and for commands including the transfer of such commands to the SIU respectively. The hold circuits of block 750-117 which receive signals from decoder circuit 750-113 generate control signals for holding the execution of commands in appropriate situations (e.g. directory section busy) and controlling the loading of data into section 750-7.
As seen from FIG. 2, the transfer of write command control words proceed from buffer 750-100 via the third position of four position (ZDTS) switch 750-118, a data register 750-119 and the first position of two position switch 750-120. The write data words are transferred from buffer 750-100 to SIU 100 via a write data register 750-121 and the second position of switch 750-120. The RWRT position of switch 750-120 is selected for one (write single command) or two (write double command) clock intervals following receipt of a signal from SIU 100 via the ARA line made in response to a signal placed on line AOPR by cache 750 for transfer of the write command. Read commands are transferred from the read command portion of transit block buffer 750-102 to SIU 100 via the fourth position (ZTBC) of the ZDTS switch 750-118, register 750-119 and the first position of switch 750-120.
The multiport identifier lines MITS receive zone bit signals via a RMITS register 750-124 and a two position switch 750-125 for the second data word in the case of a write double command. As seen from the Figure, this switch receives signals from command queue 750-107 and processor 700. That is, when cache 750 issues a read command, transit block number signals from queue 750-107 are loaded into bit positions 2 and 3 of RMITS register 750-124.
The transit block number signals are returned by SIU 100 on the MIFS lines with the read data word. These signals are loaded into an RMIFS register 750-127 via a multiposition switch 750-126. Thereafter, the contents of bit positions 2 and 3 are applied via the first position of a two position switch 750-128 to a pair of address input terminals of transit block buffer 750-102. A second RMIFSB register 750-129 primarily provides temporary storage of the transit block number signals for multiword transfers (i.e., quad read commands).
The output signals from switch 750-128 are also applied to the control input terminals of a four position ZTBA switch 750-130 for selecting the appropriate address signals to be applied to cache section 750-3 for storage of the data words. The address contents of the transit block buffer 750-102 are also applied to one set of input terminals of a predetermined one of a group of compare for circuits 750-132 through 750-135 for comparison with the address portion of a next command applied to a second set of input terminals of the comparator circuits via the RADO/ZADO lines. The result of the comparisons generated by a NAND gate 750-136 is applied to the hold control circuits of block 750-117.
As seen from FIG. 4, the zone bit signals of the ZAC command applied to the ZADOB lines 5-8, in the case of a write signal command, or for the even word of a write double command, are loaded into a RZONE register 750-140 when the write command is loaded into write command data buffer 750-100. The output of RZONE register 750-140 is applied to the first position of a two position ZONE switch 750-144. The zone bit signals, applied to the lines DZD0-3 by processor 700 for the odd word of a write double command, are loaded into a RDZD register 750-142. The output of RDZD register 750-142 is applied to the second position of ZONE switch 750-144. The output signals ZONE0-3 are applied to the circuits of section 750-9 for controlling the writing of processor data into cache 750-300 as explained herein.
Cache Section 750-3
The section 750-3 includes a cache store 750-300 having 8192 (8K) 36-bit word locations organized into 128 sets of eight, eight word blocks. The unit 750-300 is constructed from bipolar random access memory chips, conventional in design.
The cache storage unit 750-300 is addressed by a 10-bit address RADR 24-33 applied via any one of a number of 4.times.4 crossbar switches (e.g. 750-302a), conventional in design and the address registers associated therewith. As seen from the Figure, the crossbar switch receives address signals from several sources which include section 750-5, ZTBA switch 750-130 and section 750-7. The address signals appearing at the output of the crossbar switch are temporarily stored in the associated address register and applied to the address input terminals of cache storage unit 750-300.
During a write cycle of operation, the four sets of write control signals (WRT00100-WRT70100 through WRT03100-73100) generated by section 750-9, are applied to the cache storage unit 750-300 and are used to apply or gate clocking signals to the write strobe input terminals of the memory chips. This enables from one to four bytes of either a processor 700 data word from the ZADO/RADO lines or a memory data word from section 750-7 to be written into the addressed one of eight levels of cache storage unit 750-300. For processor data, the write signals are generated by decoding signals ZONE0-3 from switch 750-144. For memory data words, all of the zone signals are forced to binary ONES.
The appropriate level is established by the states of signals RTBLEV0100-2100 from transit block buffer 750-102 when writing memory data and by the hit level detected by directory circuits of block 750-512 when writing processor data. These signals are decoded by a decoder circuit 750-303 when enabled by a signal ENBMEMLEV100 from section 750-9.
During a read cycle of operation, the 36-bit word of each of the eight blocks (levels) is applied as an iput to a 1 of 8 ZCD switch 750-306. The selection of the appropriate word is established by the states of a set of hit level signals ZCD010-210 generated by section 750-5. These signals are applied to the control input terminals of ZCD switch 750-306.
As seen from the Figure, the selected word is applied to a pair of registers 750-308 and 750-310, a 1 of 8 ZDI switch 750-312 and a 1 of 4 ZIB switch 750-314. The RIRA and RIRB registers 750-308 and 750-310 apply their contents to different positions of the ZIB and ZDI switches 750-312 and 750-314. The ZIB switch 750-314 selects instructions which are applied to the instruction bus (ZIB) of processor 700 while the ZDI switch 750-312 selects data or instructions which are applied to the data in bus (ZDI) of processor 700.
In addition to applying instruction word signals read out from cache 750-300, the ZIB switch 750-314 also applies instruction word signals received from section 750-7 to processor 700. The ZDI switch 750-312 also applies data signals received from the ZCDIN switch 750-304 and section 750-7 to processor 700. The states of the control signals [ZIB010-110 and [ZDI010-210 applied to the control input terminals of switches 750-314 and 750-312 select the sources of instructions and data words to be transferred to processor 700 by such switches. The control signals are generated by the circuits of section 750-9.
In greater detail, the [ZIB010-110 signals are coded to select position #2 of switch 750-314 for a first instruction transfer in response to the detection of a directory hit for an I fetch 1 command or a directory hit for an I fetch 2 command following an I fetch 1 command to the last work in a block. The control signals are coded to select the RIRA position #1 for subsequent instruction transfers following a directory hit generated in response to an I fetch 1 or I fetch 2 command.
Where the I fetch 1 or I fetch 2 command results in a directory miss, the [ZIB010-110 signals are coded to select position #3 of ZIB switch 750-314 for transfer of instruction words received from section 750-7.
As concerns the ZDI switch 750-312, the ZCD position #1 is selected in response to the detection of directory hits and signals applied to the RDIBUF/ZDI line in response to a directory hit generated for a LDQUAD command. Memory data words are transferred to processor 700 via the ZDIN position #3 of the switch 750-312 following a directory miss. Following holding processor 700 for an instruction fetch from main memory, the signals [ZDI010-210 are coded to select the ZDIN position of switch 750-312 for transfer of the first instruction upon its receipt by section 750-7. The remaining instructions are transferred via ZIB switch 750-314.
The ZCDIN position #2 of switch 750-312 is used for diagnostic purposes to transfer signals from the ZADO-B/RADO lines. The remaining positions of ZDI switch 750-312 are used for display purposes (i.e., positions RIRB, ZRIB and RIRA). Also, position RIRB is selected to transfer data words to processor 700 in the case of a LDQUAD command when there is a directory hit.
Directory and Hit Control Section 750-5
This section includes an eight level control directory 750-500 and eight level set associative address directory 750-502. The directory 750-502 contains 128 locations, each location containing a 14-bit associative address for each level. A four position ZDAD switch 750-530 provides the random access memory (RAM) addresses for addressing directories 750-500 and 750-502 in addition to cache storage unit 750-300.
During a directory search cycle of operation, switch 750-530 under the control of signals SELZDADC0100-1100 generated by circuits within a block 750-526 selects RADO position 0. This applies the 14-bit address signals of a ZAC command from lines RADO 24-33 from processor 700 to the output terminals of the ZDAD switch 750-530. These signals are applied to the address input terminals of directories 750-500 and 750-502. During the search cycle, the contents of eight block/level addresses are read out and applied as one input of each of a group of eight comparator circuits 750-536 through 750-543. Each comparator circuit compares its block/level address with bits 10-23 of the ZAC command to determine a hit or miss condition. The results generated by the circuits 750-536 through 750-543 are applied to corresponding inputs of a group of AND gates 750-545 through 750-552. Each comparator circuit is made up of four sections, the results of which are combined in one of the AND gates 750-545 through 750-552. The final result hit signals ZHT0100 through ZHT7100 are applied as inputs to hit/miss network circuits of block 750-512 as explained herein.
The ZAC address signals are also saved in an RDAD register 750-532 when no hold condition is detected (i.e., signal [HOLD-DMEM from 750-112 is a binary ZERO). During the directory assignment cycle following the search cycle which detected a miss condition, signals SELZDADC0100-100 select RDAD position 1 of ZDAD switch 750-530. Also, a RDRIN register 750-534 is loaded with the 14-bit associative address signals from the ZADO-B lines 10-23 when the directory search cycle is completed for writing into the directory 750-502.
The control directory 750-500 also includes 128 locations, each having a predetermined number of bit positions for storing control information. Such information includes the full-empty (F/E) bits for the eight levels and a round robin (RR) count bits in addition to parity check bits (not shown).
The full-empty bits indicate whether the particular directory addresses have any significance (i.e., are valid). For a cache hit to occur, the F/E bit must be set to a binary ONE. A binary ZERO indicates the presence of an empty block or portion thereof. The round robin bits provide a count which indicates which block was replaced last. This count when read out via one of the two sets of AND gates of block 750-504 into a register 750-506 is normally incremented by one by an increment adder circuit 750-508. The resulting signals NXTRR0-RR2 are written into directory 750-500 to identify the next block to be replaced.
As seen from the Figure, the F/E bit contents of the location are read out via the positions of a two position ZFER selector switch 750-506 and applied as inputs to the directory hit/miss and hit control circuits of block 750-512. The ZFER switch 750-506 selects which half of a group of F/E bits are to be used by the circuits of block 750-512 for a hit/miss indication and which half of the group of F/E bits are to be used by such circuits for an alternate hit determination. An address bit signal ZDAD31 controls the selection of switch positions.
The circuits of block 750-510 include a multisection multiplexer circuit which generates the output signals FEDAT0100 and FEDAT1100 as a function of the hit and miss data pattern. Accordingly, these signals are set in response to the ALTHIT signal from the circuits of block 750-512. A pair of decoder circuits 750-520 and 750-521 operate to decode the level information signals ZLEV0100-2100 for generating appropriate sets of write enable strobe signals R/WFE010-210 and R/WLV010-710 for control directory 750-500 and address directory 750-502. Thus, level (ZLEV) switch 750-522 operates to control the level at which F/E bits are set or reset and the level in the address directory 750-502 at which new addresses are written during a directory assignment cycle of operation.
As seen from the Figure, the first position of ZLEV switch 750-522 when selected, applies to its output terminals signals OLDRR010-210 from directory 750-500. The second position of switch 750-522 when selected applies to its output terminals signals RLEVR0-R2 from a level register 750-524. The level register 750-524 is used to save the last set of hit level signals generated by the hit/miss level network circuits of block 750-512. This permits the hit level value to distribute to other sections of cache 750 for subsequent use (i.e., signals RHITLEV0-2).
The third position of switch 750-522 when selected applies to its output terminals, signals LEVR0-R2 generated by the circuits of block 750-512. The switch 750-522 is controlled by signals from control flip-flops included within block 750-526 (i.e., signals FBYPCAC and DIRBUSY). As seen from the Figure, the complements of the level signals stored in register 750-524 corresponding to signals RHITLEV010-210 are applied via a group of AND gates to control circuits within section 750-9.
During the search cycle of operation, the hit/miss level network circuits detect which level, if any, contains an address which matches the ZAC address. In the case of a match, it forces signal RAWHIT100 to a binary ONE and generates therefrom the sets of hit level signals ZCD010-210 and HITLEVC7010-7210 through an encoding circuit. The signals are generated in accordance with the states of the F/E bit signals ZFE010-710. That is, for a cache hit to occur at a given level, the F/E bit must be a binary ONE. As mentioned above, a binary ZERO indicates the presence of an empty block level. Each encoder circuit includes AND/OR gating circuits, conventional in design which generate the level signals in accordance with the Boolean expression L i=.sub.e=0.sup.2 .vertline..sub.j E.sub.=0 ZHTj.multidot.ZFEj. Additionally, the signals ZCD010-210 also may be generated from the level signals ZNICLEV000-2100 provided by section 750-9 during instruction fetches.
The block 750-512 also includes an alternate hit network which can also be used in the assignment of an eight word block by generating an alternate hit signal ALTHIT100 and a set of signals ALTHITLEV0100-2100 for loading into register 750-504 in place of the round robin assignment signals C7RR0100-2100. For the purpose of the present invention, such arrangements can be considered conventional in design. Reference may be made to U.S. Pat. No. 3,820,078 listed in the introductory portion of this application.
As seen from the Figure, the circuits of block 750-512 generate other hit signals HITTOTB100, HITTOC7100 and HITTOIC100. These signals are derived from signal RAWHIT100 in accordance with the following Boolean expressions:
1. HITTOC7100=RAWHIT100.multidot.BYPCAC000.
2. HITTOIC100=HITTOC7100.
3. HITTOTB100=RAWHIT100.multidot.BYPCAC000+PRERD100.multidot.BYPCAC100.
The circuits of block 750-512 receive the cache bypass signals BYPCAC000 and BYPCAC100 from block 750-526. As mentioned, this block includes a number of control state flip-flops which generate signals for sequencing the section 750-5 through various required operations for the processing of the various types of commands. Additionally, block 750-512 includes logic circuits for generating required control signals during such operations. For the purpose of the present invention, these circuits may be implemented in a conventional manner. Therefore, in order to simplify the description herein, only a brief description and the Boolean expressions will be given for certain control state flip-flops and control logic circuits as required for an understanding of the operation of the present invention.
CONTROL STATE FLIP-FLOPS
The FJAM1 flip-flop is set in response to a hit condition at the end of a directory search cycle for a read double command. The flip-flop holds the lower address bits in register(s) 750-32 enabling the accessing of the second word from cache storage unit 750-300 in the case of a read double command. Also, the flip-flop is set in response to a write single command to cause the selection of the RDAD position of the ZDAD switch 750-530 for providing or causing the same address to be applied to cache storage unit 750-500 for one more clock interval or cycle. In the absence of a hold condition (signal [HOLDDMEM=1), the FJAM1 flip-flop remains set for one cycle in accordance with the following Boolean expression:
SET=FJAM1=REQCOMB.multidot.RAWHIT.multidot.BYPCAC.multidot.(RDDBL+WRTSNG)+H OLDDMEM.multidot.FJAM2+HOLDDMEM.multidot.FJAM1.
The FJAM2 flip-flop is set in response to a hit condition at the end of a directory search cycle for a write double command. The setting of the FJAM2 flip-flop causes the setting of the FJAM1 flip-flop at the end of the next clock interval. The control state of the FJAM2 flip-flop together with the FJAM1 flip-flop causes the selection of the RDAD position of ZDAD switch 750-530 for providing the proper address for writing data into cache storage unit 750-300.
The FJAM2 flip-flop also remains set for one cycle in accordance with the following Boolean expression:
SET=FJAM2=REQCOMBO.multidot.RAWHIT.multidot.BYPCAC.multidot.WRTDBL+HOLDDMEM .multidot.FJAM2.
A flip-flop NRMPTC1 directly controls the ZDAD switch 750-530 and is set in accordance with the states of signals generated by the other control state flip-flops.
The NRMPTC1 flip-flop normally remains set for one cycle in accordance with the following Boolean expression:
SET=NRMPTC1=(WETDBL.multidot.REQCOMBO.multidot.RAWHIT.multidot.BYPCAC)+FJAM 2+SETFJAM1+REQCOMBO.multidot.(RDTYPE.multidot.BYPCAC+RDTYP.multidot.RAWHIT) .multidot.(FJAM1.multidot.FJAM2+HOLD).
The FDIRASN flip-flop specifies a directory assignment cycle of operation wherein associative address entry is written into address directory 750-500 in the case of miss conditions or cache bypass operations for read type commands.
The FDIRASN flip-flop is set for one cycle in accordance with the following Boolean expression:
SET=FDIRASN=REQCOMBO.multidot.RDTYP.multidot.(BYPCAC+RAWHIT).
The FICENAB flip-flop enables the loading of the instruction register and is set for one cycle in response to a 1/2 T clock pulse in accordance with the following Boolean expression.
SET=FHT100.
The FRCIC flip-flop is set for one cycle in response to a 1/2 T clock pulse in accordance with the following Boolean expression.
SET=FJAMZNICLEV.
CONTROL LOGIC SIGNALS
1. The ALTHIT signal indicates the presence of a psuedo hit condition.
ALTHIT=ALTLEV0+ALTLEV1+. . . ALTLEV7.
2. The signals ALTHITLEV0, ALTHITLEV1 and ALTHITLEV2 provide a three bit code which specifies the level at which a psuedo hit condition occurred. The signals are coded as follows:
a. ALTHITLEV0=ALTLEV4+ALTLEV5+ALTLEV6+ALTLEV7.
b. ALTHITLEV1=ALTLEV2+ALTLEV3+ALTLEV6+ALTLEV7.
c. ALTHITLEV2=ALTLEV1+ALTLEV3+ALTLEV5+ALTLEV7.
3. The signals ALTLEV0 through ALTLEV7 indicate which one of the eight levels, if any, has detected a psuedo hit condition. ##EQU1## 4. The DIRADDE signal is an enabling signal for decoder 750-521 which allows the generation of write strobe signals applied to address directory 750-500.
DIRADDE=NOGO.multidot.FDIRASN.
5. The DIRBUSY signal indicates when the directories 750-500 and 750-502 are busy.
DIRBUSY=FLSH+FJAM2+FJAM1+FDIRASN.
6. The FEDCODE signal is an enabling signal for decoder 750-520 which allows the generation of write strobe signals applied to control directory 750-500.
FEDCODE=FDIRASN.multidot.NOGO.
7. The FORCEBYP signal enables a cache bypass operation to take place.
FORCEBYP=FSKIPRR+FBYPCAC.
8. The GSRCH signal indicates when a search cycle of operation is to take place.
GSRCH=RDDBLZCDE.multidot.FICENAB.multidot.FRCIC.
9. The signals HITLEVC70, HITLEVC71 and HITLEVC72 provide a 3-bit code which specifies the level at which hit condition has occurred.
a. HITLEVC70=HITLEV4+HITLEV5+HITLEV6+HITLEV7.
b. HITLEVC71=HITLEV2+HITLEV3+HITLEV6+HITLEV7.
c. HITLEVC72=HITLEV1+HITLEV3+HITLEV5+HITLEV7.
10. The signals HITLEV0 through HITLEV7 indicate which one of the eight levels, if any, has detected a hit condition. ##EQU2## 11. The RAWHIT signal indicates the detection of a hit condition. RAWHIT=HITLEV0+. . . +HITLEV7.
12. The HITTOC7 and HITTOIC signals each indicates the detection of a hit condition to certain circuits within section 750-9.
HITTOC7=HITTOIC=RAWHIT.multidot.BYPCAC.
13. The HITTOTB signal indicates the detection of a hit condition or a pre-read command when in the bypass mode to the transit block buffer circuits.
HITTOTB=RAWHIT.multidot.BYPCAC+PRERD.multidot.BYPCAC.
14. The LDRAD signal enables the loading of the RDAD register 750-532.
LDRDAD=HOLDDMEM.
15. The LDRDRIN signal enables the loading of RDRIN register 750-534.
LDRDRIN=FDIRASN.
16. The signal RDDBLZCDE is used to enable the ZCD switch 750-306 in the case of a read double command.
RDDBLZCDE=FICENAB.multidot.(FDIRASN+FJAM1+FJAM2).
17. The REQCOMBO signal indicates the presence of a cache request.
REQCOMBO=NOGO.multidot.HOLDDMEM.multidot.[CANCELC.multidot.DREQCAC.
18. The ZCD0, ZCD1 and ZCD2 signals are used to control the operation of the ZCD switch 750-306.
a. ZCD0=ZCDL4+ZCDL5+ZCDL6+ZCDL7+ZNICLEV0.multidot.ZCDICENAB+RDDBLLO.
b. ZCD1=ZCDL2+ZCDL3+ZCDL6+ZCDL7+ZNICLEV1.multidot.ZCDICENAB+RDDBLL1.
c. ZCD2=ZCDL1+ZCDL3+ZCDL5+ZCDL7+ZNICLEV2.multidot.ZCDICENAB+ARDDBLL2
wherein the term(s) ZCDLi is ZCDLEVi.
19. The ZFEDATWT1 signal is a data write strobe signal used for writing F/E bit signals FEDAT0100 and FEDAT1100 into directory 750-500.
ZFEDATWT1=FDIRASN.multidot.ZDAD31.
20. The FEDAT0100 signal correspnds to the first full/empty bit.
FEDAT0100=FBYPCAC000+FALTHIT100.
21. The FEDAT1100 signal corresponds to the second full/empty bit.
FEDAT1100=FALTHIT100+FBYPCAC000.
22. The SELZDADC1 signal controls the operation of the ZDAD switch 750-530.
SELZDADC1=NRMPTC1.
23. The RWRR signal is a round robin write signal used for writing the RR bit signals back into directory 750-500.
RWRR=FDIRASN.multidot.NOGO.multidot.$CLOCK.
It will be seen from the Figure that the different decoded command signals are generated by a decoder circuit 750-528 in response to the signals applied to the DMEM lines 0-3 by processor 700. The decoder 750-528 is enabled by a signal from the DREQCAC line. The decoded command signals (e.g. WRTDBL, WRTSNG, PRERD, RDTYPE) together with other control signals such as [HOLDDMEM, FSKIPRR00 and those from the lines [CANCELC and BYPCAC are applied as inputs to the circuits of block 750-526.
INSTRUCTION BUFFER SECTION 750-7
This section receives memory data and instructions from the DFS lines which are transferred to processor 700 via the ZDI switch 750-312 and ZIB switch 750-314 respectively. The memory signals are loaded into an RDFS register 750-702 via one position of a two position switch 750-700.
Memory data fetched as a result of a miss condition upon receipt applied to the ZDI switch 750-312 via the RDFS position #0 of a 1 of 4 position (ZDIN) switch 750-708. In the case of a load quad command, memory data is loaded into the 4 location (LQBUF) buffer 750-706 when the [LQBUF signal is forced to a binary logical ONE. The write/read address signals [WRTBUF010-110/[RDBUF010-110 from section 750-112 control the writing and reading of data into and from the locations of buffer 750-706.
The memory data stored in the LQBUF buffer 750-706 is then transferred to the ZDI via the RLQBUF position #2 of the ZDIN switch 750-708.
In the case of a read double command, the even word of the pair is transferred into a REVN register 750-710. Thereafter, the even word is transferred to the ZDI switch 750-312 via position #1 of ZDIN switch 750-708 for execution of a read double odd command request or upon receipt of a RD-EVEN signal from processor 700.
As seen from the Figure, each memory data word is also loaded into the RDFSB register 750-712 and thereafter written into cache storage unit 750-300 via the ZCDIW switch 750-304 at the level specified by the contents of the RADR register 750-32.
In the case of instruction transfers, each instruction received from memory is loaded into one of the 4 storage locations of a specified one (IBUF1/IBUF2) of a pair of instruction buffers 750-715 and 750-717. The IBUF1 and IBUF2 buffers 750-715 and 750-717 are used to buffer up to two four word blocks that can be accessed from memory in response to I fetch 1 or I fetch 2 commands for which a miss condition has been detected.
The instructions are written into the location of one of the IBUF1 and IBUF2 buffers 750-715 and 750-717 specified by signals [WRTBUF0100-1100 under the control of write strobe signals [IBUF1/[IBUF2. Read control signals [RDBUF0100-1100 enable the read out of such instructions for transfer to processor 700 whenever the IBUF1 or IBUF2 location specified by the signals [ZEXT0100-1100 contains an instruction. The instruction is transferred to processor 700 via positions 1 or 2 of a two position switch 750-720 and the ZRIB switch position of the ZIB switch 750-314.
The IBUF1 and IBUF2 buffers 750-715 and 750-717 apply output valid signals IBUF1V100 and IBUF2V100 to IBUFREADY circuits of block 750-722. These circuits force IBUFRDY line to a binary ONE indicating that there is at least one instruction in the I buffer being addressed (current instruction block). As seen from the Figure, the IBUFREADY circuits receive input signals (e.g. USETBRDY, IFETCHRDY) from control circuits within section 750-9.
INSTRUCTION COUNTER SECTION 750-9
This section stores cache address signals (24-33) for indicating the next instruction to be accessed, in one of two instruction address registers (RICA/RICB) 750-900 and 750-902. The cache address signals 24-33 are loaded into the instruction register RICA/RICB not being used when an IFETCH1 command is received from processor 700. The cache address is transferred via the RADO position of ZDAD switch 750-530 and a ZDAD position #0 of a 4 position ZICIN switch 750-904.
Each time processor 700 accesses an instruction, the contents of the instruction register RICA/RICB read out via one position of a two position ZIC switch 750-906 is incremented by one via an increment circuit 750-908. The incremented contents are returned to the instruction register RICA/RICB via the RNIC position #1 of ZICIN switch 750-904.
As seen from the Figure, each instruction register stores two level fields for fetching first and second blocks of instructions in response to IFETCH1 and IFETCH2 commands. The two pairs of level field signals are applied to the different switch positions of a 4 position crossbar switch 750-910. The selected level signals ZNICLEV0100-2100 applied as inputs to block 750-512 are used to control the operation of ZCD switch 750-306 for accessing the instructions specified by the instruction register RICA/RICB. The level field signals correspond to signals HITLEVC70100-2100 which are generated by the circuit of block 750-512. These signals are loaded into one of the instruction registers following a directory assignment cycle of operation.
In addition to the level field signals, the RICA and RICB instruction address registers store other signals used for various control purposes which will be discussed herein to the extent necessary.
The incoming cache address signals from the ZDAD switch 750-530 is incremented by one via another increment circuit 750-912. The incremented address signals are loaded into the RICA/RICB instruction register via the INC position #3 of ZICIN switch 750-904. The least significant two bits 32-33 of the cache address provide the IBUF1 or IBUF2 address (i.e., signals ZEXT0100-1100) to read out instruction blocks accessed from memory.
It will be noted that the pair of level field signals LEV1 and LEV2 from other outputs of switch 750-910 are applied as inputs to a pair of comparator circuits 750-912 and 750-914. The circuits 750-912 and 750-914 compare the level signals LEV1 and LEV2, of the current instruction block from switch 750-910 with the input level signals C7RR0100-2100 corresponding to the round robin count for the next available block. Also, the comparator circuit 750-912 receives as inputs memory level signals RTBLEV0100-2100 and instruction level signals ZNICLEV0100-2100 from switch 750-910 for comparison in addition to level signals ZIC0100-2100 for comparison with signals C7RR0100-2100. The cache address signals are incremented by 4 by an increment circuit 750-918 and applied as an input to the round robin skip control circuits of block 750-916. These circuits receive as another pair of inputs the input cache address signals 24-30 from ZDAD switch 750-530 and the cache address signals of the current instruction block from ZIC switch 750-906 for comparison by circuits included therein.
The results of the pairs of cache address signals and level signal comparison are combined within other circuits within the round robin skip control circuits of block 750-916. The circuits of block 750-916, in response to decoded signals from a decoder circuit 750-922, generate output control signals which avoid addressing conflicts. For a further discussion of the operation of such circuits, reference may be made to the copending application of Marion G. Porter, et al titled "Cache Unit Information Replacement Apparatus" referenced in the introduction of this application.
The output control signals from block 750-916 are applied as inputs to the circuits of IC control block 750-920. Additionally, the control circuits of block 750-920 receive the results of the decoding of command signals applied to the DMEM lines by the decoder circuit 750-922 when it is enabled by a signal from the DREQCAC line. Together with the other signals from sections 7501 and 750-5 are applied to block 750-920, the control circuits of block 750-920 generate address and control signals for sequencing section 750-9 through the required cycles of operation for processing certain types of commands (e.g. IFETCH1, IFETCH2 AND LDQUAD commands).
The block 750-920 includes a number of control state flip-flops and logic circuits for generating the required control signals. For the same reasons mentioned in connection with section 750-5, only a brief description and the Boolean expressions will be given for certain state flip-flops and control circuits.
CONTROL STATE FLIP-FLOPS
FABCURLEV1 flip-flop defines the current level for the RICA/RICB instruction register. This flip-flop is set and reset in response to a T clock timing signal in accordance with the following Boolean expressions. The set condition overrides the reset condition. When FA/FBCURLEV is a binary ZERO, it selects level 1 and when a binary ONE, it selects level 2.
SET=DECODEIF1.multidot.F-PPIMEIS.multidot.[HOLDDMEM.multidot.[CANCELC.multi dot.ZDAD08.multidot.ZDAD09.multidot.HIT.multidot.FACTVRIC100/000+ZEXTO.mult idot.ZEXT1.multidot.RDIBUF.multidot.HOLDEXECRDIBUF.multidot.FA/FBCURLEV000. multidot.DECODELDQUAD.multidot.FLDQUAD.multidot.DECODEEIS.multidot.FACTVRIC 100/000.multidot.NOGO+ZEXTRO.multidot.ZEXT1.multidot.FLDQUAD.multidot.RDIBU F.multidot.HOLDEXECRDIBUF.multidot.FACTVRIC100/000.multidot.NOGO.
RESET=DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDDMEM.multidot.[CANCELC.mult idot.FACTVRIC100/000+DECODELDQUAD.multidot.]HOLDDMEM.multidot.[CANCELC.mult idot.FACTVRIC100/000+ZEXT0.multidot.ZEXT1.multidot.DECODELDQUAD.multidot.FL DQUAD.multidot.DECODEIF1.multidot.FA/PBCMPLEV100.multidot.FACTVRIC000/100.m ultidot.RDIBUF.multidot.HOLDEXECRDIBUF.multidot.NOGO.
The FACTVRIC flip-flop specifies the currently active instruction register RICA/RICB. When the flip-flop is set to a binary ONE, it specifies the RICA register and when a binary ZERO, it specifies the RICB register. It is set and reset in response to a T clock timing pulse signal in accordance with the following Boolean expressions.
FACTVRIC=FACTVRIC.multidot.TGLACTVRIC
wherein TGLACTVRIC=DECODEIF1.multidot.[HOLDDMEM.multidot.[CANCELC.multidot.FFPIMEI S+FNEWIF1.multidot.NOGO.
FACTVRIC=FACTVRIC.multidot.TGLACTVRIC wherein
TGLACTVRIC=(DECODEIF1+[HOLDDMEM30 [CANCELC+FFPIMEIS).multidot.(FNEWIF1+NOGO).
The FCPUWRTREQ flip-flop defines the time during which processor data is be written into cache. It is set and reset in response to a T clock timing pulse in accordance with the following Boolean expressions.
SET=(DECODEWRTSNGL+DECODEWRTDBL).multidot.HIT.multidot.[HOLDDMEM.multidot.[ CANCELC.multidot.
RESET=FWRTDBL.multidot.HOLDCACHECPUWRTSEQ.multidot.
The FDBLMISS flip-flop defines a read double type miss condition and is used to select the ZDIN position of ZDI switch 750-312 during the cycle following data recovery. It is set and reset in response to a T clock timing pulse in accordance with the following Boolean expressions.
SET=(DECODERDDBL+DECODERDRMT).multidot.[HOLDDMEM.multidot.[CANCELC.multidot .MIS.multidot.
RESET=FRDMISS.
The FEVENODD flip-flop specifies which word of the two word pairs processor 700 is waiting for when a read single type miss condition occurs. The flip-flop also defines the order that the data words are to be returned to processor 700 in the case of a read double type miss condition.
Further, the flip-flop is used during a read double hit condition to access the second data word. It is set and reset in response to a T clock timing pulse in accordance with the following Boolean exxpressions.
SET=(DECODERDSNGL+DECODEIF1.multidot.FFPIMEIS).multidot.[HOLDDMEM.multidot. [CANCELC.multidot.ZDAD09+DECODERDDBL.multidot.[HOLDDMEM.[CANCELC.multidot.D SZ1.multidot.
RESET=(DECODERDSNGL+DECODEIF1).multidot.[HOLDDMEM.multidot.[CANCELC.multido t.ZDAD09+DECODERDDBL.multidot.[HOLDDMEM.multidot.[CANCELC.multidot.DSZ1+DEC ODERDRMT.multidot.[HOLDDMEM.multidot.[CANCELC.
The FFPIMEIS flip-flop specifies that the last processor state was an FPIMEIS state which means that the IF1 command on the DMEM lines is a request for additional EIS descriptors. This flip-flop is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.
SET=FPIMEIS.
RESET=DECODEIF1.multidot.[CANCELC.multidot.[HOLDDMEM.
The FHOLDIF1 flip-flop defines when processor 700 is being held because of an IF1 miss condition so that when the instruction is received from memory, the current instruction register RICA/RICB can be updated by the FDATARECOV flip-flop. The flip-flop is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.
SET=DECODEIF1.multidot.IFPIMEIS.multidot.[HOLDDMEM.multidot.[CANCELC.multid ot.MISS.
RESET=FNEWIF1.multidot.NOGO+FDATARECOV.
The FINHRDY flip-flop is used to inhibit the signaling of an IBUFRDY condition to processor 700 when a conflict occurs between the instruction (IC) level and memory data level at the time processor 700 took the instruction loaded into RIRA/RIRB from cache. It is set in response to a T clock pulse and is reset unconditionally on the next T clock pulse when no set condition is present. It is set in accordance with the following Boolean expression.
SET=MEMWRTREQ.multidot.RDIBUF.multidot.[HOLDDMEM.multidot.NOGO.
RESET=SET.
The FJAMZNICLEV flip-flop is used to force the level signals ZNICLEV000-2100 of the next instruction to be applied to the control input terminals of ZCD switch 750-306 (i.e., signals ZCD010-210) following an IF1 command which did not specify the last word in the block. The flip-flop is set in response to a T clock pulse in accordance with the following Boolean expression. It is reset on the occurrence of the next T clock pulse.
SET=DECODEIF1.multidot.FFPIMEIS.multidot.HIT.multidot.[HOLDDMEM.multidot.[C ANCELC.multidot.[CANCELC.multidot.(ZDAD08.multidot.ZDAD09).
The FNEWIF1 flip-flop defines the cycle after an IF1 command is received from processor 700. It is set for one cycle in response to a T clock pulse in accordance with the following Boolean expression.
SET=DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDDMEM.multidot.[CANCELC.
The FRDIBUF flip-flop is used to specify that a signal on the RDIBUF line was received from processor 700 during the last cycle of operation. It is set in accordance with the following Boolean expression. It is reset during the next cycle in the absence of a set condition.
SET=RDIBUF.multidot.HOLDEXECRDIBUF.multidot.NOGO.
The FRDMISS flip-flop is used to cause the holding of processor 700 upon detecting a miss condition for any read type command. It is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.
SET=(DECODERDSNGL+(DECODEIF1.multidot.FFPIMEIS)+DECODERDRMT+DECODERDCLR+DEC ODERDDBL).[HOLDDMEM.multidot.[CANCELC.multidot.MISS.
RESET=FDATARECOV+FNEWIF1.multidot.NOGO.
The FRDREQ flip-flop defines when the second word fetched in response to a RDDBL command for a hit condition is to be read out from cache. It is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.
SET=DECODERDDBL.multidot.HIT.multidot.[HOLDDMEM.multidot.[CANCELC.
RESET=[HOLDDMEM.
The FDATARECOV flip-flop inhibits the incrementing of the instruction register RICA/RICB when the IF1 command is to the last word in the block and the IF2 command is cancelled. It is set and reset in response to a T clock pulse in accordance with the following Boolean expressions:
SET=DATARECOV.multidot.FLASTINST.multidot.[HOLDDMEM.multidot.[CANCELC+DATAR ECOV.multidot.FLASTINST.multidot.[CANCELC.multidot.[HOLDDMEM+DATARECOV.mult idot.FLASTINST.
RESET=[HOLDDMEM.multidot.FDATARECOV.
CONTROL LOGIC SIGNALS
1. The FA/FBLEV1VAL signal is used to define the state of a first valid bit position of the RICA/RICB instruction register. It is set and reset on a T clock pulse in accordance with the following Boolean expressions. The reset condition overrides the set condition.
a. FA/FBLEV1VALSET=DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDDMEM.multidot.[C ANCELC.multidot.FACTVRIC100/000+DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDD MEM.multidot.[CANCELC.multidot.EISIF2.multidot.FACTVRIC000/100+DECODELDQUAD .multidot.[HOLDDMEM[CANCELCFACTVRIC100/000.
b. FA/FBLEVIVAIRESET=DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDDMEM.multidot. [CANCELC.multidot.HIT.multidot.ZDAD08.multidot.ZDAD09.multidot.FACTVRIC100/ 000+ZEXT0.multidot.ZEXT1.multidot.DECODEIF1.multidot.DECODELDQUAD.multidot. FLDQUAD.multidot.RDIBUF.multidot.HOLDEXECRDIBUF.multidot.FACTVRIC000/100.mu ltidot.FA/FBCMPLEV000.multidot.NOG0+ZEXT0.multidot.ZEXT1.multidot.FLDQUAD.m ultidot.RDIBUF.multidot.HOLDEXECRDIBUF.multidot.FACTVRIC100/000 NOGO.
wherein RICA=FACTVRIC=1 and RICB=FACTVRIC=1.
2. The FA/FBLEV2VAL signal is used to define the state of a second valid bit position of the RICA/RICB instruction register. It is set and reset on a T clock pulse in accordance with the following Boolean expressions.
a. FA/FBLEV2VALSET=DECODEIF2.multidot.[HOLDDMEM.multidot.[CANCELC.multidot.FA CTVRIC000/100.multidot.NOGO+DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDDMEM. multidot.[CANCELC.multidot.FACTVRIC000/100.multidot.EISIF2.
b. FA/FBLEV2VALRESET=DECODEIF1.multidot.FFPIMEIS.multidot.[HOLDDMEM.multidot. [CANCELC.multidot.FACTVRIC100/000+DECODELDQUAD.multidot.[HOLDDMEM.multidot. [CANCELC.multidot.FACTVRIC100/000+ZEXT0.multidot.ZEXT1.multidot.DECODEIF1.m ultidot.DECODELDQUAD.multidot.FLDQUAD.multidot.FA/FBCURLEV.multidot.FACTVRI C000/100.multidot.RDIBUF.multidot.HOLDEXECRDIBUF.multidot.NOGO.
wherein RICA=FACTVRIC=1 and RICB=FACTVRIC=1.
3. The [ZIB0 and [ZIB1 signals control the ZIB switch for transfers of instructions from cache 750 to processor 700 via the ZIB lines.
a. [ZIB0=IFETCHRDY.multidot.FNEWIF1.
b. [ZIB1=IFETCHRDY.
4. The [ZDI0, [ZDI1 and [ZDI2 signals control the ZDI switch for transfers of instructions and data from cache 750 to processor 700 via the ZDI lines. Control signal [ZDI0, which corresponds to the most significant bit of the three bit code, can be assigned to be a binary ZERO unless positions 4 through 7 are being used for display purposes.
a. [ZDI1=DATARECOV+FDBLMISS+RDEVEN.
b. [ZDI2=RDIBUF/ZDI.multidot.(HITTOIC+FRDREQ).
5. The [ZICIN0 and [ZICIN1 signals control the ZICIN switch for loading address signals into the RICA and RICB instruction address registers 750-900 and 7450-902.
a. [ZICIN0=ALTCMD100.multidot.FEFN2HT.multidot.[HOLDDMEM.
b. [ZICIN1=FDFN1HT.multidot.FNEWIF1+FDFN2HT.
6. The signals ENABRIC1 and ENABRIC2 are used to enable the loading RICA and RICB registers.
a. ENABRIC1=FHOLDIF1.multidot.FNEWIF1.multidot.FJAMZNICLEV.multidot.[HOLDDMEM .multidot.FDATARECOV.revreaction.FHOLDIF1.multidot.DATARECOV.
b. ENABRIC2=FINHRDY.multidot.SETINHRDY.multidot.DFN2HT
wherein SETINHRDY=DFN2T.multidot.[MEMWRTREQ (ZEXT0 ZEXT1.multidot.EXECIF2.multidot.[CANCLCMD+FINHRDY+PSUEDOIF1+PSUEDOIF2)+CMP DATA/ICLEV].
7. The signal DATARECOV defines the time that new data has been loaded into the processor's registers (e.g. RDI or RBIR) and when the processor is released. This signal is generated by a flip-flop of section 750-1 which is set to a binary ONE in response to a T clock pulse upon detecting an identical comparison between the address signals specifying the word requested to be accessed by processr 700 and signals indicating the word being transferred to cache unit 750. The comparison indicates that signals DATA, MIFS2, MIFS3, MIFS1 and DATAODD are identical to signals FHT, FHOLDTB0, FHOLDTB1, RADR32 and DOUBLEODD respectively
wherein
signal FHOLDTB0=FRDMISS.multidot.LDTBVALID.multidot.FIF2ASSIGN.multidot.FTBPTR0;
signal FHOLDTB1=FRDMISS.multidot.LDTBVALID.multidot.FIF2ASSIGN.multidot.FTBPTR1;
signal DOUBLEODD=FEVENODD.multidot.FDPFS; and
signal DATA=FARDA+FDPFS.
DETAILED DESCRIPTION OF SECTION 750-1
FIG. 7a shows in greater detal different ones of the blocks of section 750-1. It will be noted that for the purpose of facilitating understanding of the present invention, the same reference numbers have been used to the extent possible for corresponding element in FIG. 4. In many cases, a single block depicted in FIG. 4 includes several groupings of circuits for controlling the operation thereof and/or for generating associated control signals. Therefore, some blocks with appropriate reference numbers are included as part of the different blocks of section 750-1.
Referring to the Figure, it is seen that certain portions of block 750-102 are shown in greater detail. The transit block buffer 750-102 is shown as including a first group of circuits for keeping track of data words received from memory in response to a read quad type command. These circuits include a plurality of clocked pair count flip-flops which comprise a four-bit position register 750-10200, a multiplexer circuit 750-10202, a plurality of NAND gates 750-10204 through 750-10210 and a decoder circuit 750-10212. It will be noted that there is a pair count flip-flop for each transit buffer location.
Additionally, the first group of circuits includes a plurality of clocked transit block valid flip-flops which comprise a four-bit position register 750-10214. The binary ONE outputs of each of the flip-flops are connected to a corresponding one of the four pair count flip-flops as shown.
In response to a read quad command, a first pair of words is sent to cache 750. This is followed by a gap and then the second pair is sent to cache 750. The pair count flip-flop associated with the transit block buffer location being referenced as specified by the states of signals MIFS2110 and MIFS3110 is switched to a binary ONE via a first AND gate in response to T clock signal [CLKT022 when signal DATAODD100 is forced to a binary ONE by the circuits of block 750-114. Signal RESETTBV100 is initially a binary ZERO and decoder circuit 750-10212 operates to force one of the first four output signals SETPC0100 through SETPC3100 in accordance with the states of the MIFS2110 and MIFS3110 from switch 750-128.
The pair count flip-flop is held in a binary ONE state via the other input AND gate by a transit block valid signals associated therewith being forced to a binary ONE. The appropriate one of the transit block valid bit flip-flops designated by decoder circuit 750-10601 (i.e., signals IN0100 through IN3100) is set to a binary ONE via a first AND gate when switching takes place to increment signal INCTBIN100 is forced to a binary ONE state in response to T clock signal [CLKT022.
The multiplexer circuit 750-10202 in accordance with the states of the signals DMIFS2100 and DMIFS3100 from switch 750-128 select the appropriate binary ONE out of the four pair count flip-flops to be applied to NAND gate 750-10204. This causes NAND gate 750-10204 to force signal LASTODD100 to a binary ZERO. This results in NAND gate 750-10206 forcing signal LASTDTAODD000 to a binary ONE.
When the next pair of data words are received, this causes NAND gate 750-10206 to force signal LASTDTAODD000 to a binary ZERO. This, in turn, causes NAND gate 750-10210 to force reset signal RESETTBV1100 to a binary ONE. The decoder circuit 750-10212 is conditioned by signal RESETTBV100 to force one of the four output terminals 4 through 7 to a binary ONE. This, in turn, resets the appropriate one of the transit block valid bit flip-flops via the other AND gate. A soon as the TB valid flip-flop resets, it resets the pair count flip-flop associated therewith via its other AND gate. It will be appreciated that such switching occurs in response to T clock signal [CLKT022.
As seen from FIG. 7a, the first group of circuits of block 750-102 further includes a plurality of NAND gates 750-10216 through 750-10222, each of which is connected to receive a different one of the binary ONE outputs from register 750-10214. The binary ONE outputs FTBV0100 through FTBV3100 are also connected to the control input terminals of the transit block address comparator circuits 750-132 through 750-136.
Each of the NAND gates 750-10216 through 750-10222 also are connected to receive a different one of the signals IN0100 through IN3100 from decoder circuit 750-10601. The outputs from these gates are applied to an AND gate 750-10224. The signals VALID000 through VALID3000 are used to indicate when a transit block register location is available for writing. That is, when a selected transit block valid bit flip-flop is in a reset state, AND gate 750-10224 maintains signal VALIDIN000 in a binary ONE state.
The VALIDIN000 signal conditions a further AND/NAND gate 750-10226 to force a control signal [RTB100 to a binary ONE during the second half of a cycle of operation (i.e., signal FHT020 is a binary ONE) in the case of a read command (i.e., signal DREQREAD100 is a binary ONE) at the time a directory assignment is not being made (i.e., signal FLDTBVALID000 is a binary ONE).
As seen from FIG. 7a, control signal [RTB100 is applied via a driver circuit 750-10228 to a decoder circuit 750-10230. The control signal [RTB110 causes the decoder circuit 750-10230 to force an appropriate one of the output signals [RTB0100 through [RTB3100 designated by the states of signals FTBPTR0100 and FTBPTR1100 applied via a pair of driver circuits 750-10232 and 750-10234 to a binary ONE state. This in turn causes bit positions 24-31 of one of the transit block register locations to be loaded with address signals applied via the RADO lines 24-31. The complement signal [RTB000 is applied as an input to block 750-107 for controlling the loading of command queue 750-107.
A second group of circuits of block 750-102 shown in greater detail includes the transit block buffer flag storage section 750-10238 of buffer 750-102. This section as well as the section of buffer 750-102, not shown, is constructed from a 4.times.4 simultaneous dual read/write memory. The memory is a 16-bit memory organized as 4 words of 4 bits each, only three bits of which are shown. Words may be independently read from any two locations at the same time as information is being written into any location. The signals FTBPTR0100 and FTBPTR1100 are applied to the write address terminals while the read addresses are enabled by the VCC signal applied to the G1 and G2 terminals. The Y bit locations are selected in accordance with the states of read address signals MIFS3100 and MIFS2100 from switch 750-128. The Z bit locations are selected in accordance with the states the signals DMIF3100 and DMIF2100 from switch 750-128. Since these locations are not pertinent they will not be discussed further herein.
The memory may be considered conventional in design, for example, it may take the form of the circuits disclosed in U.S. Pat. No. 4,070,657 which is assigned to the same assignee as named herein. Upon the receipt of memory data, the flag bit contents of the transit block location specified by signals MIFS2100 and MIFS3100 are applied to the Y output terminals. These signals are in turn applied to blocks 750-102, 750-115 and 750-117, as shown. During the directory assignment cycle for a cache read miss, the flag bit positions of the transit block location specified by signals FTBPTR0100 and FTBPTR1100 are loaded with the signals FORCEBYP000, FRDQUAD100 and FLDQUAD100 generated by the circuits of blocks 750-5 and 750-114.
It is also seen from FIG. 7a that block 750-102 further includes a group of instruction fetch flag circuits which are associated with the operation of transit block buffer 750-102. These circuits include two sets of input AND gates 750-10240 through 750-10243 and 750-10250 through 750-10253, a pair of multiplexer selector circuits 750-10255 and 750-10256, an IF1 and IF2 flag storage register 750-10258 and an output multiplexer circuit 750-10260 arranged as shown.
The binary ONE outputs of the individual IF1 and IF2 flip-flops are connected to corresponding ones of the sets of AND gates 750-10240 through 750-10243 and 750-10250 through 750-10253. These AND gates also receive input signals from the circuits of block 750-106 generated in response to the in pointer signals FTBPTR0000 and FTBPTR1000 used for addressing the different register locations within the buffer 750-102 as mentioned previously.
The multiplexer circuit 750-10255 is connected to receive as a control input, signal FIF1ASSIGN100 from FIF1ASSIGN flip-flop 750-11418. The multiplexer circircuit 750-10256 is connected to receive as a control input signal FIF2ASSIGN100 from FIF2ASSIGN flip-flop 750-1410. This enables the setting and/or resetting of the IF1 and IF2 flip-flops of register 750-10258 in response to the signals FIF1ASSIGN100 and FIF2ASSIGN100. The switching occurs in response to T clock signal [CLKT022 during the loading of a transit block register location when a control signal LDTBVALID100 is switched to a binary ONE via an AND gate 750-11428.
It will be noted that register 750-10258 contains an IF1 and IF2 flag bit position for each transit block register location. That is, the register includes flip-flops FIF10, FIF20 through FIF13, FIF23 for transit block register locations 0 through 3 respectively. Each of the binary ONE outputs from the IF1 and IF2 flag flip-flops are also applied to the different input terminals of the output multiplexer circuit 750-10260. The circuit 750-11450 contains two sections. This permits DMIFS2100 and DMIFS3100 signals applied to the control terminals of the multiplexer circuit 750-10260 from block 750-128 to select as outputs, input signals from both an IF1 and IF2 flag flip-flop. The selected pair of signals, in turn, provide flag signals ZIF1FLG100 and ZIF2FLG100 which are applied to block 750-115. These signals are used to control the writing of memory information into the IBUF1 and IBUF2 buffers 750-715 and 750-717. Additionally, the complements of the outputs from multiplexer circuit 750-10260 which correspond to signals ZIF1FLG000 and ZIF2FLG000 are applied to a pair of input terminals of a multisection comparator circuit 750-110/750-11435.
It will be noted that the last section of each of multiplexer circuits 750-10255 and 750-10256 are connected in series for generating the enable transit block buffer ready signal ENABTBRDY100 applied to block 750-114. As shown, the "0" input terminal of the last section of multiplexer circuit 750-10255 connects to a voltage VCC (representative of a binary ONE) while the "1" input terminal connects to ground (representative of a binary ZERO). The output terminal of the last section of multiplexer circuit 750-10255 connects to the "0" input terminal of the last section of multiplexer circuit 750-10256 while the "1" input terminal connects to ground. The multiplexer circuits 750-10255 and 750-10256 operate to force signal ENABTBRDY100 to a binary ONE only after the completion of an instruction fetch assignment cycle when both signals FIF1ASSIGN100 and FIF2ASSIGN100 are binary ZEROS. Therefore, the "0" input terminals are selected as outputs by the multiplexer circuits 750-10255 and 750-10256 which results in signal ENABTBRDY100 being forced to a binary ONE. This presents the inadvertent generation of the IBUFRDY100 signal as explained herein.
As seen from FIG. 7a, the circuits of the transit buffer in pointer block 750-106 includes a clocked two-bit position register 750-10600 and a decoder circuit 750-10601. The register 750-10600 has associated therewith a NAND/AND gate 750-10602 and a two input AND/OR gate 750-10604 connected in a counter arrangement. That is, the NAND gate 750-10602 in response to load signal FLDTBVALID111 from block 750-114 and signal NOGO020 force an increment signal INCTBIN100 to a binary ONE. This causes the address value stored in register 750-10600 to be incremented by one. The increment signal INCTBIN100 is applied to the circuits of block 750-102.
The most significant high order bit position of register 750-10600 is set to a binary ONE via the gate 750-10604 in response to either signals FTBPTR0100 and FTBPTR0100 or signals FTBPTR1100 and FTBPTR000 being forced to binary ONES. The complemented binary ONE output signals of the register bit positions corresponding to signals FTBPTR0000 and FTBPTR1000 are decoded by decoder circuit 750-10601. The circuit 750-1061 in response to the FTBPTR0000 and FTBPTR1000 signals forces one of the four pairs of output terminals to a binary ONE.
The command control circuit block 750-114 includes an instruction fetch 2 search (FIF2SEARCH) synchronous D type flip-flop 750-11400. The flip-flop 750-11400 is set to a binary ONE state in response to T clock signal [CLKT020 when a two input AND/OR gate 750-11402 and an AND gate 750-11404 force a set signal SETIF2SEARCH100 to a binary ONE. This occurs when either an IF1 command which is a hit or an IF2 command is received from processor 700 during an IF1 assignment cycle.
In the case of an IF1 command, this presumes that there is no hold condition (i.e., signal [HOLDDMEM000 from block 750-117 is a binary ONE) and that a directory search generated a hit (i.e., signal HITTOTB100 is a binary ONE) indicating that the requested instruction block resides in cache store 750-300. For an IF2 command, it is assumed that there has been a directory assignment cycle following a directory search in which there was a miss made in response to the IF1 command (i.e., signal FIF1ASSIGN100 is a binary ONE).
In either of the situations mentioned, the gate 750-11402 forces the signal SETIF2TIME100 to a binary ONE. When the instruction fetch command was caused by a transfer or branch instruction, which is not a NOGO (i.e., signal NOGO030 is a binary ONE) indicating that it should process the IF2 command currently being applied to the command lines (i.e., indicated by signal DREQCAC112 being forced to a binary ONE), AND gate 750-11404 forces signal SETIF2SEARCH100 to a binary ONE. This switches flip-flop 750-11400 to a binary ONE when signal [CANCEL012 is a binary ONE.
As seen from FIG. 7a, the binary ZERO output from flip-flop 750-11400 is applied as an input to the hold circuits of block 750-117. The signal FIF2SEARCH000 is delayed by a buffer circuit 750-11406 and applied to one input of an input NAND gate 750-11408 of an instruction fetch 2 assignment (IFIF2ASSIGN) flip-flop 750-11410.
The signal FIF2SEARCH010 together with the signal EISIF2000 (indicates a non-EIS type instruction) causes the NAND gate 750-11408 to switch FIF2ASSIGN flip-flop 750-11410 to a binary ONE in response to a gating signal SETBVALID100 and T clock signal [CLKT020. The state of this flip-flop as the others is gated as an output when signal FLDTBVALID111 is a binary ONE.
It will be noted that signal FLTBVALID111 is switched to a binary ONE via an AND gate 750-11412, a clocked flip-flop 750-11414 and a delay buffer circuit 750-11416 in the case of a miss condition (i.e., signal HITTOTB010 is a binary ONE) generated in response to a directory search made for a read type command (e.g. IF2). This assumes that there is no hold condition (i.e., signal [HOLDDMEM000 is a binary ONE), that in the case of an IF2 command it was not due to a transfer NOGO (i.e., signal NOGO020 is a binary ONE) and that there is no cancel condition (i.e., signal [CANCELC010 is a binary ONE) for a read type operation decoded by the circuits of block 750-113 in response to the read command applied to the command lines (i.e., signal DREQREAD100 is a binary ONE wherein DREQREAD100=READ100.multidot.DREQCAC112).
Under similar conditions, an instruction fetch 1 assignment (FIF1ASSIGN) flip-flop 750-11418 is switched to a binary ONE via an input AND gate 750-11420 in response to an IF1 command (i.e., when signal IF1100 is a binary ONE) in which there was a miss detected (i.e., signal SETTBAVALID100 is a binary ONE). The load transit buffer valid flip-flop 750-11414 remains set until signal SETLDTBVALID100 switches to a binary ZERO. It will be noted that the binary ZERO output signal FLDTBVALID000 is applied to circuits included as part of block 750-102.
The other pair of flip-flops are 750-11422 and 750-11424 set in response to signal SETLDTBVALID100 in the case of a miss condition. The load quad flip-flop 750-11424 is set to a binary ONE state when the command applied to the DMEM command lines is decoded as being a LDQUAD command (i.e., signal LDQUAD100 from decoder 750-113 is a binary ONE) and that the ZAC command applied to the ZADOB lines is coded as requiring a read quad operation (e.g. IF1, IF2, LDQUAD, PRERD and RDSNGLE commands specified by signal ZADOB04100 being set to a binary ONE).
The RDQUAD flip-flop 750-11422 is set to a binary ONE via an AND gate 750-11426 when a signal CQIN1100 from the circuits included within command queue block 750-107 is a binary ONE indicative of a double precision command (i.e., signal ZADOBO2100 is a binary ONE).
As seen from FIG. 7a, block 750-114 further includes a comparator circuit 750-11435. This circuit may be considered conventional in design and, for example, may take the form of the circuits disclosed in U.S. Pat. No. 3,955,177.
The comparator circuit 750-11435 is enabled by signals USETBRDY100 and DATA100. The signal USETBPDY100 indicates that the cache is waiting for instructions from memory to be loaded into the IBUF1 or IBUF2 buffers. The signal DATA100 is forced to a binary ONE by a NAND gate 750-11436 indicating receipt of information from memory. The comparator circuit includes two sections. One section compares the command queue input pointer signals and output pointer signals from blocks 750-108 and 750-109 respectively. This section forces signals CQCMP100 and CQBMP000 to a binary ONE and binary ZERO respectively when the pointer signals are equal. The section corresponds to block 750-110 in FIG. 4.
The other section compares input terminals A1, A2 and B1, B2, the control signals [ZRIB100, [ZRIB010 applied to input terminals A1, A2 to the states of the I fetch 1 and I fetch 2 flag signals ZIF1FLG000, ZIF2FLG000 applied to terminals B1, B2. When equal, this indicates that the information being received from memory at this time is either in response to an I fetch 1 or I fetch 2 command. It will be noted that control signal [ZRIB100 controls ZRIB switch 750-720.
The input terminals A4, A8 compare signals ZEXT0100, ZEXT1100 against signals MIFS1100 and DATAODD100 applied to the B4, B8 terminals. This indicates whether the information being addressed within the instruction buffer equals the information being received. More specifically, signals ZEXT0100 and ZEXT1100 are generated by the circuits of block 750-920 from the least two significant bit address of the instruction stored in the RIRA register. Thus, they specify the word location being addressed within the I buffer. Signal MIFS1100 is coded to specify whether the first or second half of the block is being received. Signal DATAODD100 specifies whether the first or second word of the first two word pairs is being received. The signal DATAODD100 is generated by an AND gate 750-11437.
Lastly, the comparator circuit 750-11435 compares a signal ENABTBRDY100 applied to terminal A16 from block 750-102 with the voltage VCC representative of a binary ONE applied to terminal B16. In the presence of a true comparison between the two sets of all six signals, the circuit 750-11435 forces its output to a binary ONE. This results in the complement output terminal forcing signal IBUFCMPR000 to a binary ZERO. This causes block 750-722 to force the IBUFRDY100 signal to a binary ONE as explained herein.
Additionally, section 750-114 includes an AND gate 750-11417. During the first half of a cache cycle (i.e., signal FHT120 from delay circuit 750-11810 is a binary ONE) when the FLDTBVALID flip-flop 750-11414 is a binary ONE, the AND gate 750-11417 forces control signal [RTB5-8100 to a binary ONE. This signal is applied as a clock strobe input to the level storage section of transit block buffer 750-102. This section is constructed from a 4.times.4 simultaneous dual read/write 16-bit memory organized as four words each 4 bits in length similar to the memory device of block 750-10238 and the memory devices used in constructing the 36-bit read command buffer section of block 750-102 as well as the write command/data buffer 750-100.
FIG. 7a shows that the data reception and control block 750-115 includes a plurality of NAND gates 750-11500 through 750-11510 and a plurality of AND gates 750-11511 through 750-11514 connected as shown to generate the control strobe enable signals [LQBUF100, [IBUF1100 and [IBUF2100, reset buffer signal RESETBUF100 and write control buffer signal [WRTBUF0100. These signals are used to control the operation of the buffer circuits of section 750-7. As seen from FIG. 7a, the other write control buffer signal [WRTBUF1100 is generated by a buffer delay circuit 750-11515 in response to signal FARDA010. The signal [WRTBUF0100 is derived from the output of the two input data selector/multiplexer circuit 750-128 which selects either the signal RMIFS1100 from register 750-127 or signal RMIFSB1100 from register 750-129. The selection is made in accordance with the state of signal FARDA000 produced from the accept line ARDA of data interface 600. The multiplexer circuit 750-128, in accordance with the state of signal FARDA000, generates the two sets of signals MIFS2100, MIFS3100 and DMIFS2100, DMIFS3100 which are applied to the read address inputs of buffer 750-102.
It will be noted that section 750-115 also includes a double precision (FDPFSX) D type flip-flop 750-11517 which is set in response to clocking signal [CLKT020 to a binary ONE state via a first AND gate input in accordance with the state of the signal PTXDPFS100 applied to the AND gate via amplifier circuit 750-11518 from the DPFS line by SIU 100. The DPFS line when set indicates that two words of data are being sent from SIU 100. Switching occurs when SIU100 forces the signal PTXARDA100 applied thereto via an amplifier circuit 750-11519 from the ARDA line of interface 600 to a binary ONE. The ARDA line indicates that the read data requested by cache 750 is on the DFS lines from SIU100. The output of a FARDA flip-flop (not shown) which delays signal ARDA by one clock period is applied to a second hold AND gate input along with signal FDPFSX100. The FDPFSX flip-flop 750-11517 remains set for two clock periods. That is, the flip-flop 750-11517 is set in accordance with the number of SIU responses (DPFS signals). In the case of a read single command, the SIU generates two SIU responses, each response for bringing in a pair of words. In each case, this permits the writing of the two words into cache when signal RWRCACFLG100 is a binary ONE.
The binary ZERO output of flip-flop 750-11517 is inverted by a NAND/AND gate 750-11521 and delayed by a buffer delay circuit 750-11522 before it is applied to AND gate 750-11512. The same binary ZERO output without being inverted is delayed by a buffer delay circuit 750-11523 and applied to circuits which reset the states of bit positions of a transit buffer valid bit register which forms part of transit buffer 750-102.
It will also be noted that the double precision signal FDPF110 is combined in an AND gate 750-11524 with a write cache flag signal RWRTCACFLG100 from transit block buffer flag storage portion of buffer 750-102. The AND gate 750-1152 generates a memory write request signal MEMWRTREQ100 which is forwarded to section 750-9 for enabling memory data to be written into cache (i.e., controls address switch(s) selection).
As seen from FIG. 7a, the initiating request control circuits block 750-116 includes an active output port request flip-flop 750-11600. The flip-flop is a clocked D type flip-flop which includes two input AND/OR gating circuits. Flip-flop 750-11600 is set to a binary ONE state in response to clock signal [CLKT020 when block 750-114 forces a pair of signals ENABSETAOPR100 and SETAOPR100 to binary ONES. When set to a binary ONE, this, in turn, sets the AOPR line of interface 600, signalling the SIU100 of a data transfer request. The binary ZERO side of flip-flop 750-11600 is inverted by an inverter circuit 750-11602, delayed by a delay buffer circuit 750-11604 and applied to a hold AND gate. The flip-flop 750-11600 remains set until the clock time that signal FARA020 switches to a binary ZERO indicating that the SIU100 accepted the cache memory request.
The hold control block 750-117, as shown, includes an inhibit transit buffer hit FINHTBHIT flip-flop 750-11700, an AND gate 750-11702 and a plurality of AND/NAND gates 750-11704 through 750-11716. The flip-flop 750-11700 is set to a binary ONE state via a first input AND gate and a NAND gate 750-11701 in response to a T clock signal [CLKT020 when signals INHTBHIT100 and TBHIT100 are binary ONES. The NAND gate 750-11701 forces signal INHTBHIT100 to a binary ONE in the case of a cancel condition (i.e., signal [CANCELC012 is a binary ZERO).
The complement output side of flip-flop 750-11700 applied signal FINHTBHIT000 as one input to AND gate 750-11702. A directory busy signal DIRBUSY000 from block 750-526 is applied to the other input of AND gate 750-11702. When the directory is not performing a search (i.e., signal DIRBUSY000 is a binary ONE) and signal INHTBHIT100 is a binary ONE, AND gate 750-11702 forces signal INHTBACMP000 to a binary ONE. This, in turn, causes the gate 750-11704 to force signal TBHIT100 to a binary ONE when the AND gate 750-136 forces a transit block address compare signal TBACMP100 to a binary ONE. At the same time, gate 750-11704 forces signal TBHIT000 to a binary ZERO.
The AND/NAND gates 750-11708 through 750-11710 generate signals CPSTOP000 through CPSTOP003 which are forwarded to processor 700 for indicating a hold condition. The other AND/NAND gates 750-11714 through 750-11716 generate signals [HOLDDMEM000 through [HOLDDMEM003 to specify an internal hold condition for preventing the other sections of cache 750 from executing the command applied to the command lines by processor 700. Whenever there is a hold command condition (i.e., signal HOLDCMD000 is a binary ZERO), a miss condition (i.e., signal FRDMiSS020 is a binary ZERO), a hold quad condition from block 750-916 (i.e., signal HOLDLDQUAD000 is a binary ZERO) or a transit block hit condition (i.e., signal TBHIT000 is a binary ZERO), the gates 750-11708 through 750-11710 force their respective output signals CPSTOP003 through CPSTOP000 to binary ZEROS and signals CPSTOP103 through CPSTOP100 to binary ONES. This, in turn, causes the processor 700 to halt operation.
Under similar conditions, in addition to a hold search condition (i.e., signal HOLDSEARCH000 is a binary ZERO) as indicated by AND gate 750-11712 forcing signal [EARLYHOLD000 to a binary ZERO or a hold cache condition (i.e., signal [HOLDCCU000 is a binary ZERO), the gates 750-11714 through 750-11716 force their respective output signals [HOLDDMEM000 through [HOLDMEM003 to binary ZEROS and signals [HOLDDMEM100 through [HOLDDMEM103 to binary ONES.
Referring to the Figure, it is seen that the timing circuits of block 750-118 include a synchronous D type flip-flop 750-11800 with two AND/OR input circuits. The flip-flop 750-11800 receives a half T clocking signal [CLKHT100 via gate 750-11802 and inverter circuit 750-11804. A definer T clock signal DEFTCLK110 is applied to one of the data inputs via a pair of delay buffer circuits 750-11806 and 750-11808. Each buffer circuit provides a minimum delay of 5 nanoseconds.
Both the signals [CLKHT100 and DEFTCLK110 are generated by the common timing source. In response to these signals, the half T flip-flop 750-11800 switches to a binary ONE state upon the trailing edge of the DEFTCLK110 signal. It switches to a binary ZERO state upon the occurrence of the next [CLKHT100 signal (at the trailing edge).
The signals FHT100 and FHT000, in addition to signals FHT120, FHT010 and FHT020 derived from the binary ONE and binary ZERO output terminals of flip-flop 750-11800 are distributed to other circuits of section 750-1 as well as to other sections (i.e., 750-5, 750-9 and 750-114). The signals FHT120, FHT020 and FHT010 are distributed via another pair of delay buffer circuits 750-11810 and 750-11812 and a driver circuit 750-11814 respectively.
The T clock signals such as [CLKT020 and [CLKT022 generated by the common timing source are distributed in their "raw" form to the various flip-flops of registers. When there is a need to generate a 1/2 T clock signal, the 1/2 T clock signal [CLKTHT020 is gated with the 1/2 T definer signal (FHT100) at the input of the flip-flop or register. The state of signal FHT100 is used to define the first and second halves of a T cycle. When signal FHT100 is a binary ONE, this defines a time interval corresponding to the first half of a T clock cycle. Conversely, when signal FHT100 is a binary ZERO, this defines a time interval corresponding to the second half of a T clock cycle.
For the purpose of the present invention, the data recovery circuits can be considered conventional in design and may, for example, take the form of the circuits described in the referenced patent applications. These circuits generate a data recovery signal for forwarding to processor 700 by "ANDING" the 1/2 T clock signal FHT000 with a signal indicating that data is being strobed into the processor's registers. This causes the data recovery signal to be generated only during the second half of a T clock cycle when such data is being strobed into the processor's registers.
In the case of sections 750-5 and 750-9, the signal FHT100 is used to control the switching of other timing and control flip-flops as explained herein.
DETAILED DESCRIPTION OF SECTION 750-3
FIG. 7b shows in greater detail specific ones of the blocks of section 750-3. Corresponding reference numbers have been used where possible.
Referring to FIG. 7b, it is seen that the control circuits of block 750-303 in their simplest form include a first AND gate 750-30302 and a second AND gate 750-30304. The AND gate 750-30302 is connected to force output signal [ZADR01100 to a binary ONE when signals ENBMEMLEV100 and ENBADR1100 are forced to binary ONES by the circuits of block 750-920. The second AND gate 750-30304 is connected to force output signal [ZADR00100 to a binary ONE when signals ENBMEMLEV000 and ENBADR1100 are forced to binary ONES by the circuits of block 750-920.
Predetermined combinations of the set of control signals [ZADR01100 and [ZADR00100 is applied to the control input terminals of the crossbar address selection switch 750-302 as shown. It is seen that the crossbar switch includes a number of sections, each section includes three parts indicated by the heavy lines between sections. For simplicity, the number of sections of the switch is shown together. For simplicity, the control portion of each section is shown only once since it is the same for all the sections which are required to make up the switch.
As seen from the Figure, depending upon the states of the pair of control signals [ZADR00100 and [ZADR0100, the signals from one of the three sources are applied to the set of W output terminals.
DETAILED DESCRIPTION OF SECTION 750-5
FIG. 7c shows in greater detail specific ones of the blocks of section 750-5 as explained previously. Corresponding reference numbers have been used where possible.
Referring to FIG. 7c, it is seen that the directory hit/miss control circuits of block 750-512 include an encoder network comprising a plurality of NAND gates 750-51200 through 750-51220 and a plurality of amplifier circuits 750-51224 through 750-51228. The NAND gate circuits are connected to encode the set of signals ZFE1100 through ZFE7100 from block 750-506 and the set of signals ZHT1100 through ZHT7100 from the blocks 750-546 through 750-552 into the 3-bit code for controlling the operation of switch 750-306.
The signal GSRCH100 is generated by the circuits of block 750-526. As explained herein, this signal is only forced to a binary ONE during the second half of a T clock cycle. Thus, an output from one of the NAND gates 750-51200 through 750-51208 is generated only during that interval. More specifically, the hit signal specified by the state of the full-empty bit causes one of the signals ZCDLEV1000 through ZCDLEV7000 to be forced to a binary ZERO state. This, in turn, conditions NAND gates 750-51216 through 750-51220 to generate the appropriate 3-bit code.
Signal ZCDICENAB100 also generated by the circuits of block 750-526 is forced to a binary ONE only during the first half of a T clock cycle. Thus, outputs from NAND gates 750-51210 through 750-51214 are generated only during that interval. That is, the instruction address level signals ZNICLEV0100 through ZNICLEV2100 from block 750-910 produce signals ICL0000 through ICL2000 which, in turn, produce signals ZCD0100 through ZCD2100. It will be noted that the signals ZCD0100 through ZCD2100 correspond to ZNICLEV0100 through ZNICLEV2100.
The signals RDDBLL0000 through RDDBLL2000 are used to define the second cycle of operation for a read double command. Accordingly, when any one of the signals RDDBLL0000 through RDDBLL2000 are in a binary ZERO state, this forces a corresponding one of the signals ZCD0100 through ZCD2100 to a binary ONE.
The signals ZCD0100 through ZCD2100 are applied to different inputs of corresponding ones of the amplifier driver circuits 750-51224 through 750-51228. These circuits apply the control signals [ZCD0100 through [ZCD2100 to the control terminals of switch 750-306.
A next block shown in greater detail in FIG. 7c is block 750-526. As mentioned previously, block 750-526 includes a number of directory control flip-flops. The control state flip-flops shown include the directory assignment (FDIRASN) control state flip-flop 750-52600 and a plurality of timing flip-flops of a register 750-52610.
The flip-flop 750-52600 is a clocked D type flip-flop which is set to a binary ONE via first input AND gate in the case of a command request (i.e., signal REQCOMB0100 is a binary ONE) for a read type command (i.e., RDTYP100 is a binary ONE) when processor 700 requests data from memory and not cache 750 (i.e., signal BYPCAC110 is a binary ONE). In greater detail, in the absence of a hold condition (i.e., signal HOLD000 applied via an AND gate 750-52602 is a binary ONE), a go transfer (i.e., signal NOGO021 is a binary ONE), no cancel condition (i.e., signal CANCELC010 is a binary ONE) and processor 700 has signalled a request (i.e., signal DREQCAC111 is a binary ONE) and AND gate 750-52604 forces signal REQCOMB0100 to a binary ONE.
An AND gate 750-52606 forces the signal SETONBYP100 to a binary ONE in the case of read type when decoder circuit 750-528 forces signal RDTYP100 to a binary ONE when processor 700 forces the bypass cache signal BYPCAC110 to a binary ONE. The result is that the FDIRASN flip-flop 750-52600 switches to a binary ONE for specifying a directory assignment cycle of operation.
The flip-flop 750-52600 is also set to a binary ONE via a second input AND gate in the case of a command request (i.e., signal REQCOMB0100 is a binary ONE) when a miss condition is detected for the block requested to be read (i.e., signal SETONMISS100 is a binary ONE). The signal SETONMISS100 is forced to a binary ONE by an AND gate 750-52608 when signal RDTYP100 is a binary ONE and signal RAWHIT000 from block 750-512 is a binary ONE. The flip-flop 750-52600 is reset to a binary ZERO state upon the occurrence of clock signal [CLOCK112 generated from the common source in the absence of a set output signal from the two input AND gates.
A first flip-flop (FICENAB) of register 750-52610 is used to define the interval of time within a T clock cycle when instructions or operands are to be fetched from cache 750.
This flip-flop is switched to a binary ONE state via a first AND gate in response to a clock signal [CLOCKD120 when signal FHT100 generated by the timing circuits of block 750-112 is a binary ONE. Clock signal [CLOCKD120 from the common timing source is applied via an AND gate 750-52612 and an inverter circuit 750-52612 and an inverter circuit 750-52514. The FICENAB flip-flop resets on the following clock signal when signal FHT100 has been switched to a binary ZERO.
The second flip-flop of register 750-52610 is used to define an interval during which operands (not instructions) are being fetched from cache 750 as a consequence of a special condition caused by an IF1 command which did not specify the last word in an instruction block. The FRCIC flip-flop is switched to a binary ONE via a first input AND gate in response to a clock signal [CLOCKD120 when signal FJAMZNICLEV000 is a binary ONE. The FRCIC flip-flop resets on the following clock pulse when signal FJAMZNICLEV000 has been switched to a binary ZERO.
As shown, the signal at the binary ZERO output terminal of the FICENAB flip-flop corresponds to the gate half T clock signal GATEHFTCHLK110 which is distributed to the circuits of block 750-920.
The signal FICENAB000 is combined with signal FRCIC000 and signal RDDBLZCDE000 within an AND gate 750-52616 to produce signal GSRCH100. The signal RDDBLACDE000 is from decoder circuit. This gate forces signal GSRCH100 to a binary ONE during the second half of a T clock cycle when operands are being fetched (i.e., signal FICENAB000 is a binary ONE) except in the case of a read double command (i.e., signal RDDBLZCDE000 is a binary ONE).
The binary ZERO output of the FICENA flip-flop is combined with signal FRCIC000 within a NAND gate 750-52618. The NAND gate 750-52618 operates to force signal ZCDINCENAB100 to a binary ONE during the first half T interval when instructions are being fetched (i.e., signal FICENAB000 is a binary ZERO) or in the case of the type IF1 command described above (i.e., signal FRCIC000 is a binary ZERO).
The circuits of block 750-526 further include a NAND gate 750-52620 and a plurality of AND gates 750-52622 through 750-52628 connected, as shown. The circuits generate a first enable control signal DIRADDE100 for controlling the operation of decoder circuit 750-521. Additionally, they generate a second enable control signal FEDCODE100 for controlling the operation of a decoder circuit 750-52000 of block 750-520.
In greater detail, during a directory assignment cycle (i.e., signal FDIRASN100 is a binary ONE) in the absence of a transfer no go condition (i.e., signal NOGO21 is a binary ONE), AND gate 750-52626 forces signal DIRNOGO100 to a binary ONE. When a signal FSKIPRR000 from the circuits of block 750-916 is a binary ONE, this causes the AND gate 750-52628 to force signal DIRADDE100 to a binary ONE which enables decoder circuit 750-521 for operation. When either signal DIRNOGO100 or FSKIPRO000 is forced to a binary ZERO, this causes AND gate 750-52628 to disable decoder circuit 750-521 by forcing signal DIRADDE100 to a binary ZERO.
Under the same conditions, the AND gate 750-52624 forces signal FEDCODE100 to a binary ONE which enables decoder circuit 750-52000 for operation. The AND gate 750-52630 causes an amplifier circuit 750-52632 to force signal FORCEBYP000 to a binary ONE when both signals FSKIPRR000 and FBYPCAC00 are binary ONES. The FORCEBYP000 is applied to the transit block flag section of block 750-102. The signal FBYPCAC000 is generated in a conventional in accordance with the signal applied to the line BYPCAC by processor 700. The signal is stored in a flip-flop, not shown, whose binary ZERO output corresponds to signal FBYPCAC000.
The circuits of block 750-520, as shown, include the decoder circuit 750-52000 and a pair of mutiplexer circuits 750-52002 and 750-52004. It is assumed that normally the signals applied to the "0" input terminals of multiplexer circuits 750-52002 and 750-52004 are selected to be applied as outputs (i.e., the signal applied to the G input is a binary ZERO). Therefore, when the decoder circuit 750-520000 is enabled, the output signals FED0100 through FED7100 result in the generation of signals RWFE0100 through RWFE7100 in response to clock signal [CLOCK000. The FIG. 7c also shows in greater detail register 750-504 as including a clocked four stage register 750-50400 and a plurality of amplifier circuits 750-50402 through 750-50602. The register 750-50400 includes D type flip-flops, the first three of which are connected for storing round robin signals OLDRR0100 through OLDRR2100. The fourth flip-flop is connected to indicate the presence of an alternate hit condition having been detected by the circuits of block 750-562, now shown. That is, it is set to a binary ONE state when signal ALTHIT100 is a binary ONE.
It will be noted that the flip-flops of register 750-50400 are only enabled in response to clock signal [CLOCK122 when signal FDIRASN000 is a binary ONE indicative of no directory assignment cycle beig performed (a hit condition).
In the case of a hit condition detected within the half of a block being referenced, signal ALTHIT000 is forced to a binary ZERO. This causes the first three flip-flops of register 750-50400 to be loaded via a first set of input AND gates with the round robin signals RR0100 through RR2100 from block 750-500. When there is a hit condition detected within the other half (alternate) of the block being referenced, the circuits of block 750-512 force signal ALTHIT100 to a binary ONE. This causes the three flip-flops to be loaded via a second set of input AND gates with the alternate level signals ALTHITLEV0100 through ALTHITLEV2100 generated by the circuits of block 750-512.
The binary ONE signals of register 750-50400 are applied as inputs to the amplifier driver circuits 750-50402 through 750-50406 for storage in the transit block buffer 750-102. The same signals are applied to the A operand input terminals of an adder circuit of block 750-508. The adder circuit adds or increments the signals OLDRR0100 through OLDRR2100 by one via the binary ONE applied to the C1 terminal of the adder circuit. The sum signals NXTRR0100 through NXTRR2100 generated at the F output terminals are written into the round robin section of control directory 750-500.
Lastly, the signals OLDRR0100 through OLDRR2100 are applied as inputs to another set of amplifier driver circuits 750-50408 through 750-50412 for stoarge in one of the instruction address registers 750-900 and 750-902 of FIG. 7e.
DETAILED DESCRIPTION OF SECTION 750-7
FIG. 7d shows in greater detail different ones of blocks of section 750-7. As seen from FIG. 7d, block 750-722 includes a plurlity of series connected NAND gates 750-72230 through 750-72234. The NAND gates 750-72230 and 750-72231 are connected to receive instruction buffer valid and instruction control signals IBUF1V100, [ZRIB010 and IBUF2V100, [ZIRB100 from I buffers 750-715 and 750-717 and block 750-920. The IBUF1V100 and IBUF2V100 signals indicate the instruction buffer into which information is being loaded. That is, when signal IBUF1V100 is a binary ONE, that specifies that I buffer 750-715 is loaded. When signal IBUF2V100 is a binary ONE, that specifies that I buffer 750-717 is loaded with an instruction word.
The control signals [ZRIB010 and [ZRIB100 specify which instruction buffer valid bit is to be examined which corresponds to the instruction buffer being addressed. That is, when signal [ZRIB010 is a binary ONE, the IBUF1 valid bit is specified by the circuits of block 750-920. When signal [ZRIB100 is a binary ONE, that specifies the IBUF2 valid bit. When either signal IBUF1RDY000 or signal IBUF2RDY000 is forced to a binary ZERO, NAND gate 750-72232 forces signal TBIBUFRDY100 to a binary ONE indicative of a ready condition.
The circuits of block 750-920 force an enabling signal USETBRDY100 to a binary ONE following the switching of the appropriate I buffer valid bit. This causes the NAND gate 750-72233 to force the TBRDY000 signal to a binary ZERO. The result is that NAND gate 750-72234 forces the IBUFRDY100 to a binary ONE signalling the ready condition.
It will also be noted that NAND gate 750-72234 also forces the IBUFRDY100 signal to a binary ONE when an instruction fetch ready signal IFETCHRDY000 is forced to a biary ZERO by the circuits of block 750-920. Signal IFETCHRDY000 is a binary ONE except when the instructions are being pulled from a block in cache. Lastly, NAND gate 750-72234 forces IBUFRDY100 signal to a biary ONE when an instruction buffer compare signal IBUFCMPR000 is forced to a binary ONE by comparator circuit 750-11435.
DETAILED DESCRIPTION OF SECTION 750-9
FIG. 7e shows in greater detail specific ones of the blocks of section 750-9. Corresponding reference numbers have been used where possible.
Referring to FIG. 7e, it is seen that the block 750-920 includes a first group of circuits of block 750-92000 which generate the four sets of write control signals WRT00100 through WRT70100, WRT001100 through WRT71100, WRT02110 through WRT72100 and WRT03100 through WRT73100. As seen from FIG. 7e, these circuits include a pair of multiplexer circuits 750-92002 and 750-92004, a register 750-92006 and four octal decoder circuits 750-92008 through 750-92014, connected as shown.
The multiplexer circuit 750-92002 has signals RHITLEV0100 through RHITLEV2100 from block 750-512 applied to the set of "0" input terminals while signals RTBLEV0100 through RTBLEV2100 applied to the set of "1" input terminals. During the first half of a T cycle when signal FDFN2HT100 applied to the control terminal G0/G1 is a binary ZERO, the signals RHITLEV0100 and RHITLEV2100 are applied to the output terminals. They are clocked into the top three flip-flops of register 750-92006 in response to T clock signal [CLKHT02. This enables processor operands to be written into cache 750-300 during the second half of the T clock cycle. During the second half of a T cycle when signal FDFN2HT100 is forced to a binary ONE, the signals RTBLEV0100 through RTBLEV2100 are clocked into the register 750-92006 in response to the T clock signal [CLKHT02. This enables memory data to be written into cache 750-300 during the first half of the next cycle.
The second mutiplexer circuit 750-92004 has signals ZONE0100 through ZONE3100 from switch 750-144 applied to the set of "0" input terminals while signal MEMWRTREQ100 from block 750-112 is applied to the set of "1" input terminals. When signal FDFN2HT100 is a binary ZERO, the signals ZONE0100 through ZONE3100 are applied to the output terminals. They are clocked into the bottom four flip-flops of register 750-9206 in response to T clock signal [CLKHT02. During the first half of a T clock cycle, NAND gate 750-92005 forces signal ENBWRT100 to a binary ONE which enables the previously loaded signals to be applied to the output terminals. This enables the processor zone bits to be used in specifying which operand bytes are to be updated when writing processor data into the specified level of cache. When signal FDFN2HT100 is forced to a binary ONE, the signal MEMWRTREQ100 is clocked into the register 750-92006. This causes all the zone bits to be forced to binary ONES for causing all of the bytes of each data word received from memory to be written into the specified level of cache during the first half of the next T clock cycle.
As seen from FIG. 7e, different ones of the signals RWRTLEV0100 through RWRTLEV2100 are applied to the enable input terminals of octal decoder circuits 750-92008 through 750-92014. The signals RWRTLEV0100 through RWRTLEV2100 are applied to the input terminals of each of the octal decoder circuits 750-92008 through 750-92014.
The block 750-920 includes a second group of circuits of block 750-92020. These circuits generate the half T clock signal applied to the circuits of block 750-92000, the enable memory level signal ENABMEMLEV100, and enable address signal ENADR1100 applied to the circuits of block 750-303. They also generate the sets of control signals [ZIC010, [ZIC110 and [RICA100, [RICB100 applied to the circuits of instruction address registers 750-900 and 750-902 in addition to control signals [RIRA100 and [RIRB100 applied to the registers 750-308 and 750-310.
The circuits of block 750-92020 include a pair of half definer flip-flops of a register 750-92022, a group of three control flip-flops of register 750-92024 and a clocked flip-flop 750-92026. The circuits also include a number of AND gates, NAND gates, AND/NAND gates and AND/OR gate 750-92030 through 750-92041.
The series connected AND/NAND gate 750-92030, AND/OR gate 750-92032 and AND gates 750-92034 and 750-92035 in response to a signal FLDQUAD100 from 750-916, a signal FWFIDESC010 from processor 700 and signals FACTVRIC000 and FACTVRIC100 from register 750-92024 generate control signals [ZIC000, [ZIC010 and [ZIC110. These signals are used to control the operation of ZIC switch 750-906 and the different sections of registers 750-900 and 750-902 (e.g. level valid bit storage and level bit storage) in addition to registers associated therewith.
The series connected AND gate 750-92036, the AND/NAND gate 750-92037 and NAND gates 750-92038 through 750-92041 operate to generate register strobe signals [RICA100 and [RICB100. These signals control the loading of registers 750-900 and 750-902. The AND gate 750-92036 forces signal VALRDIBUF100 to a binary ONE when a hit condition was detected in the case of a read command (i.e., signal FRDMISS000 is a binary ONE) and the transfer was a go (i.e., signal NOGO020 is a binary ONE).
The signal FRDMISS000 is obtained from the binary ZERO output of the flip-flop, not shown, which as mentioned is set in accordance with the Boolean expression: FRDMISS=(RDCMD.multidot.[HOLDDMEM.multidot.HITTOIC.multidot.[CANCELC). The signals GOODFTCHA100 and GOODFTCHB100 generated by circuits, now shown, indicate whether the RICA register 750-900 or RICB register 750-902 is being used at that time and its contents are therefore incremented. For example, signal GOODFTCHA100 is generated in accordance with the following Boolean expression: GOODFTCHA=INSTIF1.multidot.FLDQUAD.multidot.FACTVRIC.multidot.FDFN2HT+FDFN 2HT.multidot.FLDQUAD.multidot.FACTVRIC. Signal GOODFTCHB is generated in a similar fashion except for the reversal in states of signals FACTVRIC and FACTVRIC.
It is seen that when signal EXECRDIBUF100 is forced to a binary ONE when processor 700 forces signal RDIBUF110 to a binary ONE, the NAND gate 750-92039 causes NAND gate 750-92041 to force signal [RICA100 to a binary ONE when signal GOODFTCHA100 is a binary ONE. The signal ENBSTRBA000 indicates when the RICA register 750-900 is being initially loaded. That is, when signal ENBSTRBA000 is forced to a binary ZERO, it causes NAND gate 750-92041 to force signal [RICA100 to a binary ONE. More specifically, signal ENBSTRBA is generated in accordance with the following Boolean expression:
ENBSTRBA=FLDQUAD.multidot.FACTVRIC.multidot.FNEWIF1.multidot.FDFN1HT+FDFN1H T.multidot.FACTVRIC.multidot.FJAMZNICLEV.multidot.FHOLDIF1+(INSTIF1+DCDLDQU AD).multidot.FACTVRIC.multidot.FDFN2HT.multidot.[CANCLCMD+FDFN2HT.multidot. [ZIC.multidot.INH2HT.multidot.ENAB2HT.
wherein ENAB2HT=ENABRIC1+ENABRIC2 and INH2HT=[CANCLCMD.multidot.FLASTINST. Under either set of conditions, signals [RICA100 and [RICB100 enable the strobing of their correspondig registers when they are either being initially loaded or following incrementing as when instructions are being fetched or pulled out from cache.
The NAND gate 750-92042, AND/NAND gate 750-92043 and NAND gates 750-92044 through 750-92049 are connected to generate register strobe signals [RIRA100 and [RIRB100 in a fashion similar to the generation of register strobe signals [RICA100 and [RICB100.
The NAND gate 750-92046 forces signal [RIRA100 to a binary ONE in the case of a new instruction fetch (i.e., signal NEWINST000 is a binary ZERO) or when the processor 700 takes an instruction from RIRA register 750-308 (i.e., signal TAKEINST000 is a binary ZERO). The NAND gate 750-92049 forces signal [RIRB100 in the case of a new operand fetch (i.e., signal NEWDATA000 is a binary ZERO) or when processor 700 takes a data word from RIRB register 750-310 (i.e., signal TAKEDATA000 is a binary ZERO).
The AND gate 750-93050 and AND/NAND gate 750-92051 generate signal ENBMEMLEV100 during the second half of a T clock cycle (i.e., signal FDFN2HT101 is a binary ONE) when the circuits of block 750-112 force memory write request signal MEMWRTREQ100 to a binary ONE. The NAND gate 750-92052 generates signal ENBADR1100 during the second half of a T clock cycle (i.e., signal FDFN1HT101 is a binary ZERO) or when the instruction counter is in use (i.e., signal USEIC000 is a binary ZERO).
As concerns the flip-flop registers, it is seen that the flip-flop of register 750-92026 is switched to a binary ONE state via a first AND gate when AND gate 750-92053 is conditioned to force signal INSTIF1100 to a binary ONE in response to an IF1 command being decoded by decoder circuit 750-922 (i.e., signal DCDIF1100 is a binary ONE) which does not require additional descriptors (i.e., signal FFPIMEIS020 from processor 700 is a binary ONE) and AND gate 750-92054 forces signal [CANCELCMD000 to a binary ONE in response to a no cancel condition (i.e., signal [CANCELC010 is a binary ONE) and a no hold condition (i.e., signal [HOLDDMEM001 is a binary ZERO).
The flip-flop register 750-92026 is reset to a binary ZERO via a second input AND gate which receives signals ENABNEWINST000 and NEWIF1FDBK100 from a pair of NAND gates 750-92042 and 750-92043 and AND gate 750-92055. The binary ONE output of the flip-flop register 750-92026 is applied to NAND gate 750-92056. NAND gate 750-92056, during the first half of a T clock cycle (i.e., signal FDFN1HT100 is a binary ONE), switches signal USEIC000 to a binary ZERO when signal FNEWIF1100 is switched to a binary ONE.
The second flip-flop register 750-92022 includes the pair of timing flip-flops which are both set to binary ONES in response to signal GATEHFTCLK100 from section 750-5 in response to 1/2 T clock signal [CLKHT021. The flip-flops of register 750-92022 are reset to binary ZEROS in response to the next 1/2 T clock signal [CLKHT021.
The flip-flops of register 750-92024, as mentioned previously, provide various state control signals. The first flip-flop (FRDIBUF) is switched to a binary ONE state when NAND gate 750-92060 forces signal SETRDIBUF100 to a binary ONE in response to read I buffer request from processor 700 (i.e., signal EXECRDIBUF000 is a binary ZERO) or an inhibit ready condition (i.e., signal FINHRDY010 is a binary ZERO) when AND gate 750-92061 forces signal ENABSETRDIBUF100 to a binary ONE. The signal ENABSETRDIBUF100 is forced to a binary ONE in the case of a command which is not a load quad command (i.e., signal FLDQUAD000 is a binary ONE) or an instruction fetch 1 command (i.e., signal GOODIF1000 is a binary ONE). The FRDIBUF flip-flop is reset a clock period later in response to T clock signal [CLKT021 via a second input AND gate.
The second flip-flop (FACTVRIC) of register 750-92024 is set and reset in accordance with the Boolean expressions previously given via the NAND gates 750-92062 and 750-92064, the AND gate 750-92063 and AND/NAND gate 750-92065. The third flip-flop (FRDDATA) is set to a binary ONE state via a first input AND gate in response to signal SETRDIBUF100 when the command is a load quad command (ie., signal FLDQUAD100 is a binary ONE). The FRDDATA flip-flop is reset to a binary ZERO state a clock period later via a second input AND gate in response to the T clock signal [CLKT021.
The next group of circuits included within block 750-920 include the circuits of block 750-92070. As seen from FIG. 7e, these circuits include a first plurality of AND gates, AND/NAND gates and NAND gates 750-92071 through 750-92086, connected as shown. These gates generate control signals SETACURLEV100, [RICACNTL100 and RSTACURLEV2000 which control the setting and resetting of the current level and level valid bit positions of RICA register 750-900 in accordance with the states of signals SETALEV1VAL100, RSTALEV1VAL000 and SETLEV2VAL100. These signals are generated by another plurality of AND gates and NAND gates 750-92087 through 750-92095.
A second plurality of AND gates, AND/NAND gates and NAND gates 750-92100 through 750-92116, in a similar fashion, generates signals SETBCURLEV100, RSTBCURLEV200 and [RICBCNTL100 which set and reset the current level and valid bits for the RICB register 750-902 in accordance with signals SETBLEV1VAL100, RSTBLEV1VAL000 and SETBLEV2VAL100. These signals are generated another plurality of AND gates and NAND gates 750-92120 through 750-92125.
A plurality of AND gates 750-92126 through 750-92129, in response to signals SETALEV1VAL100, SETBLEV1VAL100, SETALEV2VAL100 and SETBLEV1VAL100, generate control signals [RICALEV1100 through [RICBLEV2100 when signal [CANCELCMD000 is a binary ONE. These signals are applied to the control input terminals of the level bit storage sections of the RICA and RICB registers 750-900 and 750-902 for controlling the loading of hit level signals from section 750-512.
A further plurality of AND/NAND, AND/OR gates and NAND gates 750-92130 through 750-92137, in response to signals from the level valid bit storage and level storage sections of registers 750-900 and 750-902, generate the use transit buffer ready signal USETBRDY100 and the control signals [ZRIB010 and [ZRIB100 which are applied to the circuits of block 750-114.
It is also seen that block 750-92070 includes a four D type flip-flop register 750-92140, and the pair of AND gates 750-92141 and 750-92142 connected as shown. The flip-flops of register 750-92140 are loaded with the contents of bit positions 8 and 9 of the RICA and RICB register 750-900 and 750-902 in response to T clock signal [CLKHT020 under the control of signals [RICA100 and [RICB100. That is, the top pair of register flip-flops are clocked when signal [RICA100 is applied to terminal C1 is forced to a binary ONE while the bottom pair of register flip-flops are clocked when signal [RICB100 applied to terminal G2 is forced to a binary ONE. The signals [ZIC000 and [ZIC100 applied to terminals G3 and G4 control independently the generation output signals from the top pair of flip-flops and bottom pair of flip-flops respectively at the corresponding sets of output terminals.
Pairs of binary ZERO output signals are combined within AND gates 750-92141 and 750-92142 to generate address signals ZEXT0100 and ZEXT1100 which are applied to the buffer circuits of section 750-7.
A last group of circuits include a flip-flop register 750-92150 and a plurality of AND gates, an AND/NAND gate, NAND gates and AND/OR gate 750-92151 through 750-92156. These circuits are connected to generate signal IFETCHRDY000 which is applied to the circuits of section 750-114. The gates 750-92153 and 750-92154 are connected to generate timing signals DFN2HT101 and DFN2HT100 in response to signal FHT010 from block 750-112. These signals are forced to binary ONES during the second half of a T clock cycle of operation.
The flip-flop register 750-92150 is set to a binary ONE via a first input AND gate when AND gates 750-92151 and 750-92152 force signals SETINHRDY100 and CANCELINHRDY000 to binary ONES. It is reset to a binary ZERO via a second input AND gate when NAND gate 750-92155 force signal RSINHRDY000 to a binary ZERO. The binary ZERO output of register 750-92150 is applied to AND/or gate 750-92156. When signal FINHRDY000 is forced to a binary ZERO, it causes gate 750-92156 to force signal IFETCHRDY000 to a binary ONE state.
DESCRIPTION OF OPERATION
With reference to FIGS. 1 through 7e and the timing diagram of FIG. 8, the operation of the preferred embodiment of the present invention will now be described.
As mentioned, the split cycle arrangement of the present invention divides a T clock cycle into first and second halves as illustrated by waveform D in FIG. 8. That is, when signal FHT100 is a binary ONE, shown as the negative going portion in the Figure, this defines the first half of a T clock cycle. When signal FHT100 is a binary ZERO, shown as the positive portion, this defines the second half of a T clock cycle.
During the first half of the T clock cycle, either instructions are fetched or memory data is written into cache 750-300. In both cases, the level to be accessed is already established. That is, for instructions, the level is stored in either the RICA or RICB instruction address register at the time an IF1 or IF2 command received from processor 700 was executed. For memory data, the level is stored in one of the register locations of transit block buffer 750-102 as a result of the circuits of block 750-520 having detected a miss condition which caused cache 750 to fetch the requested data from memory. During the second half of a T clock cycle, either operand data is accessed from cache or processor data is written into cache in accordance with the results of a directory search.
To illustrate the above operations, it will be assumed by way of example that processor 700 is going to process the sequence of instructions including a load A instruction (LDA), a store A instruction (STA), a load A instruction (LDA), a store A instruction (STA), and a next instruction, as shown in FIG. 8. The format of these instructions is shown in the cited copending patent applications and in the publication "Series 60 (Level 66)/6000 MACRO Assembler Program (GMAP)" by Honeywell Information Systems Inc., Copyright 1977, Order Number DDOBB, Rev. 0. It will be appreciated that the processor 700 executes the four instructions in pipelined fashion which is illustrated in detail in copending patent application "A Microprogrammed Computer Control Unit Capable of Efficiently Executing a Large Repertoire of Instructions for a High Performance Data Processig Unit", referenced herein.
As indicated herein, processor 700 carries out various operations during I, C and E cycles of operation in executing instructions. This results in the issuance of cache commands by processor 700 to cache unit 750 as described herein. For ease of explanation, it is assumed that the instructions reside in cache unit 750-300.
It will be appreciated that at some point during instruction processing, processor 700 loads one of the instruction address registers RICA/RICB with address and level information. This usually comes about as a consequence of the processor executing a transfer or branch instruction which results in processor 700 generating an IF1 command followed by an IF2 command. Following the execution of these commands by cache unit 750, the fetching of instructions during the first half of a T clock cycle and operands during the second half T clock cycle proceed as illustrated in FIG. 8.
For ease of explanation, it will be assumed that the IF1 command includes an address which specifies the fetching of the first instruction word of a block of instructions in cache which includes the above mentioned sequence of instructions. The operation of cache unit 750 in executing the IF1 and IF2 commands now will be described briefly. The IF1 command upon receipt by cache unit 750 is decoded by the decoder circuits 750-922. The decoder circuits 750-922 cause the circuits of block 750-920 to generate signals for loading the alternate instruction address register which is assumed to be RICA with signals corresponding to the incremented value of the address included within the IF1 command. That is, during the first T clock cycle, the address signals from switch 750-530 are incremented by one by circuit 750-912 and loaded into the RICA instruction address register 750-900 in response to 1/2 T clock signal [CLKHT100 when signal [RICA100 is a binary ONE. The signal [RICA100 is forced to a binary ONE by the circuits 750-920 when signal ENBSTRBA000 of FIG. 7e is forced to a binary ZERO during the first half of the first T clock cycle. During the first half of the first T clock cycle, the IF1 command address is loaded into RADR register 750-301 via the ZADR switch 750-302 in response to signal [CLKHT100. During the first half of the T clock cycle, signal ENBMEMLEV100 is a binary ZERO. Also, signal ENBADR1100 is a binary ZERO (i.e., the control state FNEWIF1 flip-flop 750-92026 switches on the T clock in response to signal [CLKT021, as explained herein). Therefore, both signals [ZADR01100 and [ZADR00100 are binary ZEROS causing position 0 to be selected as an address source.
The IF1 command address is also applied as an input to the directory circuits of block 750-502 via ZDAD switch 750-530 for a search cycle of operation. Since the instruction block is in cache, the circuits of block 750-512 generate the appropriate hit signal HITTOC7100 which is applied to section 750-9. The decoding of the IF1 command causes the hit level signals HITLEVC70100-2100 generated by the circuits of block 750-512 to be loaded into the RICA instruction address register. Also, the level 1 valid bit and hit/miss bit positions of the RICA register 750-900 are forced to binary ONES (i.e., hit signal HITTOC7100 switches the hit/miss bit position to a binary ONE). The stored level value is thereafter used to control the operation of the ZCD switch 750-306 during subsequent instruction fetches as explained herein.
The first instruction accessed from the location specified by the IF1 address is transferred as an operand word to processor 700 during the second half of the first T clock cycle via position 1 of the ZDI switch 750-312 during the end of the first T clock cycle. The first instruction is clocked into the RBIR register 704-152 of processor 700 on the T clock in response to signal [CLKT100.
The signal FJAMZNIBLEV000 enables the next instruction to be transferred to processor 700 during the second half of the second T clock cycle. It is assumed that this instruction corresponds to the LDA instruction of FIG. 8. The signal FJAMZNICLEV000 is forced to a binary ZERO by the circuits of block 750-900. The signal FJAMZNICLEV000 causes the level signals ZNICLEV000-2100 obtained from RICA register 750-900 to be applied as inputs to the control input terminals of ZCD switch 750-306 following execution of the IF1 command. That is, referring to FIG. 7c, it is seen that signal FJAMZNICLEV000 switches signal FRCIC000 to a binary ZERO. This causes NAND gate 750-52618 to force signal ZCDINCENAB100 to a binary ONE during the second half of the second T clock cycle. Signal ZCDINCENAB100 conditions NAND gates 750-51210 through 750-51214 to generate signals [ZCD0100 through [ZCD2100 from signals ZNICLEV0100 through ZNICLEV2100.
Also, the IF1 command decoded by decoder circuit 750-922 caused the FNEWIF1 flip-flop 750-92026 to be switched to a binary ONE. As mentioned previously, it defines the operations during the cycle (second) after the IF1 command was received on the T clock in response to signal [CLKT020. More specifically, during the first half of the second T clock cycle, the NEWIF1 flip-flop 750-92026 causes NAND gate 750-92056 to switch signal USEIC000 to a binary ZERO. The signal USEIC000 conditions NAND gate 750-92052 to force the signal ENBADR1100 to a binary ONE. Since there is no memory data transfer taking place at this time due to the IF2 command being processed (i.e., signal MEMWRTREQ100 from 750-112 is a binary ZERO), AND/NAND decoder circuit 750-92051 forces signal ENBMEMLEV100 to a binary ZERO and signal ENBMEMLEV000 to a binary ZERO during the second half of the T clock cycle.
The AND circuit 750-30304, in turn, applies the binary ONE signal to its output terminals which results in output signal [ZADR0100 being forced to a binary ONE while AND circuit 750-30302 forces signal [ZADR1100 to a binary ZERO. The pair of signals conditions switch 750-302 to select as a source of address signals, the RICA instruction address register connected to switch position 1 during the first half of the second T clock cycle.
Accordingly, the RADRO register 750-320 is loaded via the ZIC switch 750-906 with the address signals from RICA register 750-900 in response to the 1/2 T clock signal [CLKHT100 during the first half of the second cycle. The RICA register 750-900 is selected since at this time signal [ZIC100 is a binary ZERO. That is, signal ENBALT100 is a binary ZERO and signal FACTRIC100, from the binary ZERO output of FACTRIC flip-flop of register 750-92024, is a binary ZERO. These signals condition AND/OR gate 750-92032 to force signal [ZIC100 to a binary ZERO. The address contents applied to cache unit 750-300 cause a second instruction from each level to be read out to ZCD switch 750-306. The level signals ZNICLEV0100-2100 select the instruction at the level specified by the contents of the RICA register 750-900 to be applied to the ZIB lines. It is applied to the ZIB lines via position 0 of the ZIB switch 750-314.
During the second half of the second cycle, the address signals from RICA register 750-900 are incremented by one by circuit 750-902 and loaded into the RICA register 750-900 via position 1 of ZICIN switch 750-902 in response to 1/2 T clock signal [CLKHT100 when signal [RICA100 is a binary ONE. Again, signal [RIRCA100 is forced to a binary ONE when signal ENBSTROBA00 is forced to a binary ZERO during the second half of the second T clock cycle. At T clock time, the address of the third cycle resides in the RICA register 750-900. This instruction corresponds to the LDA instruction of FIG. 8.
The signal FJAMZNICLEV000 when forced to a binary ZERO causes NAND gate 750-92044 to force signal NEWINST000 to a binary ZERO during the second half of the second T clock cycle. This causes NAND gate 750-92046 to force signal [RIRA100 to a binary ONE. On the T clock at the end of the second T clock cycle, the second instruction read out from ZCD switch 750-306 is also loaded into the RIRA register 750-308. This enables processor 700 to load the second instruction into its RBIR register in response to T clock signal [CLKT100 at the end of the second T clock cycle when it has completed execution of the previous instruction.
That is, when processor 700 has completed executing the first instruction, it forces the RDIBUF line to a binary ONE. The signal applied to the RDIBUF line by processor 700 causes the circuits of block 750-92020 to switch the FRDIBUF flip-flop of register 750-92024 to a binary ONE in response to T clock signal [CLKT020. Hence, signal FRDIBUF100 corresponds to the signal applied to the RDIBUF line delayed by one clock period. Thus, it specifies that a signal on the RDIBUF line was received from processor 700 during the last cycle. This indicates whether the RIRA register 750-308 has to be refilled with another instruction during the first half of the third T clock cycle. If processor 700 does not complete the execution of the previous instruction, the RDIBUF line signal will not be generated. Since the next instruction to be accessed has already been loaded into the RIRA register 750-308, the register is not refilled during the first half of the next T clock cycle of operation.
The execution of the IF2 command by cache unit 750 is similar to the IF1 command. However, the address contained in the IF2 command is only used for a directory search in the case of a hit as assumed in this example. The result is that the level signals generated by the circuits of block 750-512 are loaded into the level 2 bit positions of the RICA register 750-900. Also, the valid bit and hit/miss bit positions are forced to binary ONES (i.e., a go condition is assumed).
In this example, it is assumed that processor 700 completed its execution of the previous instruction and forced the RDIBUF line to a binary ONE as illustrated by the first negative portion of waveform E in FIG. 8. During the first half of the third T clock cycle, the signal FRDIBUF100 causes the LDA instruction specified by the contents of the RADR register 750-301 to be loaded into the RIRA register 750-308 (waveform K) and the RICA register contents to be incremented by one and reloaded into the RICA register 750-900. The RADR register 750-301, as mentioned above, was loaded from the RICA register 750-308 via the ZIC position of ZADR switch 750-320 on the T clock of the previous cycle.
During the first half of the third cycle, the address applied to cache unit 750-300 causes instructions to be read out from the same addressed locations from each of the eight levels. During the first half of the third cycle, the circuits of block 750-526 of FIG. 7c force signal ZCDICENAB100 to a binary ONE (i.e., signal FICENAB000 is forced to a binary ZERO). This conditions the circuits of block 750-512 to apply signals ZNICLEV0100 through ZNICLEV2100 as control signals [ZCD0100 through [ZCD2100 to ZCD switch 750-306. This causes the LDA instruction to be selected for loading into RIRA register 750-308 by ZCD switch 750-306 (i.e., see waveform K). Thereafter, the LDA instruction is loaded into the RBIR register of processor 700 on the T clock in response to signal [CLKT100.
During the first T clock cycle (fourth cycle which corresponds to an I cycle), processor 700 processes the LDA instruction. This involves the formation of an address which is included in a read single command forwarded to cache 750 by processor section 704-4 of FIG. 3e. The command is coded to specify a memory read quad operation for fetching a 4 word block from memory 800. In greater detail, the generated address loaded into the RADO register 704-46 serves as the command address. Additionally, command bits 1-4 and 3 one bits 5-8 are generated by the circuits 704-118 of FIG. 5c and switch 704-40. The zone bits 5-8 are set to binary ONES, since they are not used for read commands. Command bits 1-4 are connected to a command code of 0111 by the decoder circuits of block 704-118 (i.e., quad operation). The circuits of block 704-108 generate the cache command signals specifying a read single command applied to the DMEM lines. The decoder 704-120 forces the DREQCAC line to a binary ONE. As seen from FIG. 8, during the next T clock cycle, which corresponds to a C cycle, processor 700 signals cache 750 of the cache request by forcing the DREQCAC line to a binary ONE (i.e., waveform G).
The address contained within the read command is applied via ZDAD switch 750-530 to ZADR switch 750-302 in addition to the directory circuits of blocks 750-500 and 750-502. As seen from FIG. 7c, during the first half of the fifth cycle, AND/NAND gate 750-92051 and NAND gate 750-92052 force signals ENBMEMLEV100 and ENBADR1100 to binary ZEROS. The result is that the circuits of block 750-303 cause control signals [ZADR00100 and [ZADR01100 to be binary ZEROS. Accordingly, ZADR switch 750-302 selects as an address source, ZDAD switch 750-532.
As seen from FIG. 8, the read command address is loaded into the RADR register 750-301 for application to all levels on a 1/2 T clock in response to signal [CLKHT100 (i.e., waveform H). When a hit condition is detected by the circuits of block 750-512, this causes the operand address word at the specified level to be read out from ZCD switch 750-306 during the second half of the T clock cycle as illustrated in FIG. 8 (i.e., waveform I).
In greater detail, with reference to FIG. 7c, it is seen that the circuits of block 750-526 force signal GSRC11100 to a binary ONE during the second half of a T clock cycle. The hit signals ZHT1100 through ZHT7100 from circuits 750-546 through 750-552 are used to control the operation of ZCD switch 750-306 in accordance with the results of the search operation just performed. In the case of a hit condition, when one of the signals ZHT1100 through ZHT7100 is forced to a binary ONE, this causes one of the signals [ZCD0100 through [ZCD2100 to be forced to a binary ONE. This results in the operand address word from the level at which the hit occurred to be applied to the ZDI lines via position 1 of ZDI switch 750-312. As seen from FIG. 8, the comparison of bits 10-23 of the read command address, the encoding of the hit level signals when there is a hit and the enabling of the ZCD switch 750-526 requires a full T clock cycle of operation.
The operand word applied to the ZDI lines is loaded into the processor's RDI data register 704-164 of FIG. 3c in response to T clock signal [CLKT100 (waveform I of FIG. 8).
When a hit condition is not detected, the output signals applied to the ZDI lines are still loaded into RDI data register 704-164, but the processor 700 is prevented from further processing or held via the CPSTOP line. When the requested information is obtained from memory by cache unit 750, the contents of RDI data register 704-164 are replaced at which time the DATARECOV line is forced to a binary ONE and processor 700 is permitted to continue processing (i.e., the CPSTOP line is forced to a binary ONE).
While it is seen that the read command address from processor 700 was loaded into the RADR register 750-301 on the 1/2 T clock in response to signal [CLKHT100, other addresses also are loaded into the RADR register 750-301 during the other 1/2 T clock times, but they are not meaningful. Hence, they are not shown in FIG. 8.
It will be noted from FIG. 8 that processor 700 prior to generating the read command forces the RDIBUF line to a binary ONE a second time during the third cycle. This signals cache unit 750 that the processor 700 has taken the first LDA instruction on the previous T clock. Hence, during the first half T of the fourth cycle, cache unit 750 refills the RIRA register 750-308 with the next instruction. This corresponds to the STA instruction in FIG. 8.
In greater detail, it is seen from FIG. 7c that the circuits of block 750-526 force signal ZCDICENAB100 to a binary ONE. This conditions the circuits of block 750-512 to apply level signals ZNICLEV0100 through ZNICLEV2100 from RICA instruction register 750-900 as control signals [ZCD0100 through [ZCD2100 to ZCD switch 750-306. This causes the STA instruction at the location specified by the address contents of RADR register 750-301 loaded on the previous T clock (waveform J) to be selected for loading into RIRA register 750-308 by ZCD switch 750-360 (i.e., waveform K). Thereafter, the LDA instruction is loaded into the RBIR register of processor 700 on the T clock in response to signal [CLKT100 (i.e., waveform L).
The LDA instruction remains in the RBIR register only for one clock period. Therefore, the STA instruction is loaded into the RBIR register on the T clock as discussed above. The STA instruction causes the processor 700 to generate a second cache request to cache unit 750. In greater detail, the STA instruction requires two processor cycles for completion. During the first cycle, processor 700 carries out operations similar to those required for the LDA instruction which results in generating the address. This address is included in the write single command which processor 700 forwards to cache unit 750 and the end of the first cache cycle. At that time, processor 700 forces the DREQCAC line to a binary ONE (waveform M).
As seen from FIG. 8, the write command address applied to the ZADOB/RADO lines is loaded into RADR register 750-301 from position 1 of ZADR switch 750-302. During the first half of the sixth cycle, since there is no memory data transfer, the circuits of block 750-92000 of FIG. 7e force signals ENBMEMLEV100 and ENBADR1100 to binary ZEROS. This causes the circuits of block 750-303 to force signals [ZADR00100 and [ZADR01100 to binary ZEROS. Accordingly, ZADR switch 750-302 connects the address output of ZDAD switch 750-530 as the address input to RADR register 750-301. While the command write address is clocked into RADR register on the 1/2 T clock in response to signal [CLKHT100 and applied to all of the levels, nothing happens at this time, since the directory search must be performed for the write command (i.e., no write signals are generated). The write command address is saved in the RDAD register 750-532 for writing the processor data word during the next T clock cycle.
The write command address is also applied via the RDRIN register 750-514 to directories 750-500 and 750-502 for carrying out a search cycle of operation. As mentioned, the search operation requires a full T clock cycle. As seen from FIG. 8, the write command address saved in the RDAD register 750-532 is applied via position 0 of ZDAD switch 750-530 to the ZDAD switch 750-532 during the first half of the seventh clock cycle. Again, ZADR switch 750-302 connects the address output of ZDAD switch 750-530 as the address input to RADR register 750-301. The write command address is again clocked into RADR register 750-301 on the 1/2 T clock in response to signal [CLKHT100.
Referring to FIG. 7e, it is seen that during the second half of the seventh T clock cycle, the multiplexer circuit 750-92002 applies the hit level signals RHITLEV0100 through RHITLEV2100 from the circuits of block 750-512 as inputs to register 750-92006. These signals are clocked into register 750-92006 in response to 1/2 T clock signal [CLKHT021 and applied to the inputs of decoder circuits 750-92008 through 750-92014. At the same time, the zone signals ZONE0100 through ZONE3100 from switch 750-144 obtained from processor 700 are also loaded into register 750-92006 during the second half of the cycle.
During the second cycle of the STA instruction, processor 700 transfers the data word via the RADO lines and the RADO register to cache unit 750. At this time, the circuits of block 750-526 condition ZCDIN switch 750-304 to apply the processor data word via position 1 as an input to all of the levels of cache store 750-300. The decoder circuits of block 750-920000 force one of the write signals of one of the sets of write signals (e.g. signal WRT00100) for writing the data word into the appropriate zone (waveform 0).
As seen from FIG. 8, during the third cycle, processor 700 again forces the RDIBUF line to a binary ONE indicating that the STA instruction was loaded into the RBIR register. During the first half of the fifth cycle, the RDIBUF flip-flop of register 750-92024 set by the RDIBUF signal causes the second LDA instruction, stored at the location specified by the contents of RADR register 750-301, to be loaded into RIRA register 750-308 (waveform K). That is, the RDIBUF flip-flop causes signal TAKEINST000 to be forced to a binary ZERO, which forces signal [RIRA100 to a binary ONE.
The RADR register 750-301 is loaded with an address from RICA instruction register 750-900 during the second half of the fourth cycle via ZIC switch 750-906 and position 1 of ZADR switch 750-302 (waveform J). This address is applied to the address inputs of all levels of cache storage unit 750-300. Also, during the first half of the fifth cycle, the address contents of the RICA register 750-900 are incremented by one and loaded back into the register 750-900. The read out of the appropriate instruction from ZCD switch 750-306 proceeds under the control of the level signals ZNICLEV0100-2100 from switch 750-910 which are used to generate signals ZCD0100-2100.
While the RIRA register 750-308 is loaded with the second LDA instruction, it is seen from FIG. 8 that it is not transferred to the RBIR register until the sixth cycle (waveform F). The reason is that the STA instruction, as mentioned previously, requires two cycles.
Following the completion of the I cycle execution of the STA instruction, processor 700 forces the RDIBUF line to a binary ONE (waveform E). As seen from FIG. 8, the second LDA instruction, following its loading into the RBIR register, results in processor 700 forwarding a second read command to cache 750, as signalled by the forcing of the DREQCAC line to a binary ONE (waveform G). In the manner previously described, the read command address from processor 700 is loaded into RADR register 750-301 during the first half of the eighth cycle in response to signal [CLKHT100 (waveform H). During the second half of the cycle, the operand address word, from the level at which the bit condition occurred, is loaded into the processor RDI register via the ZDI lines.
Because the RDIBUF line was forced to a binary ONE during the sixth cycle, this again causes a new instruction corresponding to the second STA instruction to be loaded into RIRA register 750-308, during the first half of the seventh cycle (waveform K). The STA instruction is loaded into the processor RBIR register on the T clock during the second half of the seventh cycle (waveform L).
In the manner previously described, the processor 700 generates a second write command which is forwarded to cache unit 750 during the ninth cycle and signalled by forcing the DREQCAC line to a binary ONE (waveform M). The write command address is loaded into the RADR register 750-301 from the RADO lines and RDAD register 750-532 on the 1/2 T clock in response to signals [CLKHT100 (waveform N). During the second half of the tenth cycle, the processor data word is written into cache unit 750-300. Also, the next instruction is loaded into RIRA register 750-308 during the first half of the eighth cycle (waveform K).
From the foregoing, it is seen how the arrangement of the preferred embodiment enables instructions to be accessed from cache storage unit 750-300 during the first half of a T clock cycle and the writing or read out of processor operands into and from cache storage unit 750-300 during the second half of the same T clock cycle.
It will be appreciated that in a system which has a high hit ratio such as the preferred embodiment, considerably more instructions are accessed from cache then memory data being written into cache. Hence, the split cycle arrangement minimizes interference between such instruction and processor operand accesses.
Also, the arrangement prevents interference between the writing of memory data and processor operand accesses. As mentioned, during the first portion of each T clock cycle, when there is data to be written into cache storage unit 750-300, the circuits of block 750-115 force the memory write request signal to a binary ONE. This results from the MIFS steering signals returned by main memory 800. Bits 2 and 3 are used to select the address contents of one of the transit block buffer locations for read out into the RADR register 750-301.
Referring to FIG. 7e, it is seen that signal MEMWRTREQ100 from 750-115 causes AND/NAND gate 750-9205 to force signal ENBMEMLEV100 to a binary ONE and signal ENBMEMLEV000 to a binary ZERO. This causes AND gates 750-30302 and AND gate 750-30304 to force control signals [ZADR01100 and [ZADR00100 to a binary ONE and a binary ZERO, respectively. The result is that the ZADR switch 750-302 selects position 2 (ZTBA) instead of position 1. Accordingly, the transit block buffer is connected as the address source for the RADR register 750-301.
On the T clock signal, the transit block buffer address is loaded into the RADR register. On the 1/2 T clock following that T clock, the memory data signals which are loaded into RDFSB register 750-712 are written into cache storage unit 750-300 via ZCDIN switch 750-304 at the address read out from buffer 750-102.
As seen from FIG. 7e, the signal MEMWRTREQ100 forces the bottom three flip-flops of register 750-92006 to binary ONES. This enables all of the decoder circuits 750-92008 through 750-92014 for operation. Accordingly, each of these circuits decodes the level signals RTBLEV0100 through RTBLEV2100 and forces one of its outputs to a binary ONE. This causes all four bytes of the data word to be written into cache unit 750-300. It will be appreciated that the remaining words of the data block are written into cache unit 750-300 in the same manner during the first half of successive T clock cycles of operation.
It will be noted that in those instances where memory data is being received preventing instruction accesses, the circuits of block 750-920 prevent the IBUFRDY line from indicating a ready condition. That is, the signal MEMWRTREQ100 causes the inhibit instruction ready FINHRDY flip-flop 750-92150 to be forced to a binary ONE. This causes AND/OR gate 750-92156 to force signal IFETCHRDY000 to a binary ONE. The result is that signal IBUFRDY100, generated by the circuits of block 750-115, is forced to a binary ZERO indicating a non-ready condition.
For further discussion, reference may be made to the copending application "A Cache Arrangement for Performing Simultaneous Read/Write Operations".
From the foregoing, it is seen how the arrangement of the preferred embodiment minimizes the interference among the different types of operations required to be performed by a cache system. Accordingly, this results in improved systems performance in terms of efficiency and hit ratio.
While in accordance with the provisions and statute, there has been illustrated and described the best form of the invention known, certain changes may be made to the system described without departing from the spirit of the invention as set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.
Claims
What is claimed is:
1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a buffer store including a plurality of addressable word locations for storing said information; address switch selection means having a number of inputs for receiving a corresponding number of addresses from a corresponding number of address sources and an output; address register means coupled to said output and to said buffer store, said address register means for storing the address specifying the word location to be accessed during a cache cycle of operation; control circuit means coupled to said address switch selection means for generating coded control signals identifying which address source is connected to supply said address to said address register means; and, timing means for generating timing signals for defining a number of intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during one of said intervals to enable said address selection means to select an address for loading into said address register means from one of said address sources and said control means being conditioned during another one of said intervals to enable said address switch selection means to select an address for loading into said address register means from another one of said address sources for enabling the accessing of said information specified by both address sources during the same cache cycle without interference.
2. The cache unit of claim 1 wherein said information includes data and instructions and said buffer store word locations are organized into a plurality of levels, and wherein said timing means generates first and second timing signals for defining first and second intervals corresponding to said number of intervals.
3. The cache unit of claim 2 wherein said levels are organized vertically for accessing information on a word basis.
4. The system of claim 2 wherein said timing means includes: a clocked bistable element having a clock input terminal, a gate input terminal and at least one output terminal; first input means for receiving a first series of clock pulses for defining a time interval which is one-half the duration of said cache cycle, said first input means being connected to said clock input terminal; and, said input means for receiving a definer clock pulse signal, said second input means being connected to said gate input terminal, said bistable element being conditioned by said clock pulses and said definer clock pulse signal to produce at said output terminal, a bistate signal whose first and second states define said first and second intervals of said cache cycle.
5. The cache unit of claim 2 wherein control means includes: first gating means coupled to receive said first timing signal from said timing means and said gating means being operative to generate an output signal for enabling the loading of address information into said address register means during said first interval for accessing information from said levels of said buffer store during said second interval of said cache cycle; second gating means coupled to receive said second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register means during said second interval for enabling access to information stored in said levels of said buffer store during said first interval of said cache cycle; and, said address switch selection means having control inputs connected to said first and second gating means, said address switch selection means being conditioned by said coded signals for enabling said address switch selection means to load said address register means with said addresses from said address sources during said first and second intervals of said same cache cycle of operation.
6. The cache unit of claim 5 wherein said one of said address sources includes: an instruction address register coupled to said one of said inputs of said address switch selection means, said instruction address register including a number of bit positions, a group of said bit positions for storing an address specifying a next word location within said levels of said buffer store from which an instruction word is to be accessed during said first interval of said cache cycle.
7. The cache unit of claim 6 wherein each of said commands includes a command code and an address and said another one of said address sources includes: an input circuit means coupled to said processing unit for receiving said address of each said command and said input circuit means being connected to said another one of said inputs of said address switch selection means, said input circuit means being operative to apply said command address specifying a word location within each of said levels of said buffer store from which an operand word is to be fetched or into which an operand word is to be written during said second interval of said cache cycle.
8. The cache unit of claim 7 wherein further one of said address sources includes: a buffer for storing at least one address derived from a command which has a command code specifying a read type operation, said address specifying the word location within said buffer store into which the information requested from said main store by said command is to be written; and, means coupled to said buffer and to said address switch selection means, said means for applying said address to a further one of said inputs of said address switch selection means for loading into said address register means enabling the writing of said information into said buffer store during said first interval of said cache cycle.
9. The cache unit of claim 8 wherein said buffer is arranged to store a set of level signals specifying which one of said levels in which said requested information is to be written and said cache unit further including: input switch means including at least one set of input terminals coupled to receive information to be written into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store; and, write control circuit means comprising decoder means for receiving said set of level signals from said buffer, said decoder circuit being enabled in response to said set of level signals to generate a set of write control signals for writing said information into the location and level of said buffer store specified by said buffer during said first interval.
10. The cache unit of claim 9 wherein said unit further includes: an input data register coupled to receive data words from said main store transferred in response to one of said commands having a command code specifying a read type operation previously stored in said buffer, said input data register being coupled to said one set of input terminals of said input switch means for enabling said data words to be applied to said levels of said buffer store during said first intervals of said cache cycle for writing into the designated level.
11. The cache unit of claim 8 wherein said control means further includes third gating means for generating memory write enable signals enabling said requested information to be written into said buffer store during said first interval, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch selection means to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into said address register means.
12. The cache unit of claim 11 wherein said unit further includes: instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said buffer store; and, inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said buffer store during said first interval.
13. The cache unit of claim 10 wherein said third gating means generates first and second memory write enabling signals designated as ENBMEMLEV and ENBMEMLEV respectively in accordance with the expressions: ENBMEMLEV=MEMWRTREQ.multidot.FDN2HT and ENBMEMLEV=MEMWRTREQ.multidot.FDN2HT wherein signal MEMWRTREQ indicates that said requested information is to be written into said buffer store and signal FDN2HT defines said second interval, and said first and second gating means generates first and second coded control signals [ZADRO and [ZADRO respectively in accordance with the expressions: [ZADRO=ENABMEMLEV.multidot.ENBADR and [ZADRO=ENABMEMLEV.multidot.ENBADR wherein signal ENBADR is a binary ONE during said second interval, for selecting an address from said instruction address register, said buffer and said input circuit means for loading into said address register means when signals [ZADRO, ZADRO have the values 00, 01 and 10 respectively.
14. The cache unit of claim 12 wherein said control means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first interval, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said predetermined type of command to force signal ENBADR to a binary ONE enabling said address switch selection means to select an address from said instruction address register means for loading into said address register means during said first interval for accessing an instruction from said levels of said buffer store during said second interval.
15. The cache unit of claim 13 wherein said predetermined type of command includes a command code specifying an operation for loading the address of a next block of instructions into said instruction address register means for enabling said data processing unit to access further instructions from said buffer store during subsequent cache cycles.
16. The cache unit of claim 2 wherein each of said commands includes a command code and an address and wherein each level of said buffer store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache unit further including: a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said buffer store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address; comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said buffer store; and, directory level control means coupled to said timing means to said comparison means and to said buffer store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second interval of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without interfering with transferring instruction words requested by said data processing unit.
17. The cache unit of claim 16 wherein said cache unit further includes: output multiposition switch means including a number of sets of input terminals corresponding to the number of levels, a plurality of output terminals and a set of control input terminals; and a number of conductor means, each coupling a different one of said number of sets of input terminals to said buffer store for receiving signals read out from a different one of said levels of said buffer store and said control input terminals being connected to receive said set of hit level signals, said multiposition switch means being conditioned by said set of hit level signals to apply to said output terminals said signals from one of said levels designated by said level signals as the operand word to be transferred to said data processing unit during said second interval of said next cache cycle.
18. The cache unit of claim 17 wherein said cache unit further includes: input switch means including at least one set of input terminals coupled to receive information to be written into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store; and, write control circuit means comprising: decoder circuit means including first input means for receiving said set of hit level signals and second input means for receiving write control signals specifying those portions of said information applied from said input switch means to be written into said buffer store, said decoder circuit means being operative in response to said set of hit level signals to generate a set of write control signals for writing said information into the designated one of said levels of said buffer store during said intervals.
19. The cache unit of claim 18 wherein each of said commands whose command code specify a write operation further includes: a number of data words to be written into said main store, and wherein said input switch means includes another set of input terminals, said cache unit further including input conductor means coupled to said another set of input terminals for enabling said number of data words to be applied to all of said levels of said buffer store during said second interval of said cache cycle for writing therein when said hit detection signals indicate that the block of information words specified by said command resides in said buffer store.
20. A cache unit for use with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a buffer store including a plurality of addressable word locations organized into a plurality of levels for storing said data and instructions; multiposition address switch selection means having a number of sets of input terminals for receiving a corresponding number of sets of address signals from a corresponding number of address sources, a plurality of output terminals and a plurality of control input terminals; an address register coupled to said plurality of output terminals and to said buffer store, said address register for storing the address specifying the word location within said levels to be accessed during a cache cycle of operation; control circuit means coupled to said plurality of control input terminals of said multiposition address switch selection means, said control means generating coded control signals identifying which address source is connected to supply said address to said output terminals; and, split cycle timing means for generating timing signals for defining first and second intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during said first interval to enable said address selection means to select an address for loading into said address register applied to a first one of said sets of input terminals by a first one of said address sources and said control means being conditioned during said second interval to enable said address switch selection means to select an address for loading into said address register applied to a second one of said sets of input terminals applied by a second one of said address sources for enabling the performance of different types of operations without interference involving the accessing of data and instructions specified by said first and second address sources during the same cache cycle.
21. The cache unit of claim 20 wherein said levels are organized vertically for accessing information on a word basis.
22. The cache unit of claim 20 wherein control circuit means includes: first gating means coupled to receive a first timing signal from said timing means and said gating means being operative to generate an output signal for enabling the loading of address information into said address register during said first interval for accessing information from said levels of said buffer store during said second interval of said cache cycle; second gating means coupled to receive a second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register during said second interval for enabling access to information stored in said levels of said buffer store during said first interval of said cache cycle; and, said plurality of control input terminals of said address switch selection means being connected to said first and second gating means, said address switch selection means being conditioned by said coded signals for enabling the loading of said address register with said addresses from said address sources during said first and second intervals of said same cache cycle of operation.
23. The cache unit of claim 22 wherein each of said commands includes a command code and an address and said first one of said address sources includes: an input circuit means coupled to said processing unit for receiving said address of each said command and said input circuit means being connected to said first one of said sets of input terminals of said address switch selection means, said input circuit means being operative to apply said command address specifying a word location within each of said levels of said buffer store from which an operand word is to be fetched or into which an operand word is to be written during said second interval of said cache cycle.
24. The cache unit of claim 23 wherein said second one of said address sources includes: an instruction address register coupled to said second one of said sets of input terminals of said address switch selection means, said instruction address register including a number of bit positions, a group of said bit positions for storing an address specifying a next word location within said levels of said buffer store from which an instruction word is to be accessed during said first interval of said cache cycle.
25. The cache unit of claim 24 wherein further one of said address sources includes: a buffer for storing at least one address derived from a command which has a command code specifying a read type operation, said address specifying the word location within said buffer store into which the information requested from said main store by said command is to be written; and, means coupled to said buffer and to said address switch selection means, said means for applying said address to a third one of said sets of input terminals of said address switch selection means for loading into said address register enabling the writing of said information into said buffer store during said first interval of said cache cycle.
26. The cache unit of claim 25 wherein said control circuit means further includes third gating means for generating memory write enable signals enabling said requested information to be written into said buffer store during said first interval, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch selection means to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into said address register.
27. The cache unit of claim 26 wherein said unit further includes: instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said buffer store; and, inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said buffer store during said first interval.
28. The cache unit of claim 27 wherein said control circuit means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first interval, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said predetermined type of command to generate a control signal for conditioning said address switch selection means to select an address from said instruction address register for loading into said address register during said first interval for accessing an instruction from said levels of said buffer store during said second interval.
29. The cache unit of claim 20 wherein each of said commands includes a command code and an address and wherein each level of said buffer store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache unit further including: a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said buffer store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address; comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said buffer store; and, directory level control means coupled to said split cycle timing means to said comparison means and to said buffer store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second interval of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without interfering with transferring instruction words requested by said data processing unit.
30. A cache system for use with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit by a number of address sources in response to commands received from said data processing unit, said cache system comprising: a cache store including a plurality of addressable word locations organized into a plurality of levels for storing said data and instructions, said levels being arranged vertically for accessing information on a word basis; a multiposition address switch having a number of sets of input terminals for receiving a corresponding number of sets of address signals from said number of address sources, a plurality of output terminals and a plurality of control input terminals; an address register coupled to said plurality of output terminals and to said cache store, said address register for storing the address specifying the location within said levels whose contents are to be accessed during a cache cycle of operation; control circuit means coupled to said multiposition address switch input control terminals for generating coded control signals identifying which one of said number of address sources is connected to supply said address to said output terminals; and, split cycle timing means for generating timing signals for defining first and second halves of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during said first half to enable said address switch to select an address for loading into said address register applied to a first one of said sets of input terminals by a first one of said address sources for enabling access of data during said second half of said cache cycle and said control means being conditioned during said second half to enable said address switch to select an address for loading into said address register applied to a second one of said sets of input terminals by a second one of said address sources for enabling the accessing of instructions during said first half of said cache cycle without interference.
31. The cache system of claim 30 wherein said split cycle timing means includes means for distributing to different sections of said cache system first and second sets of clock pulses having a 180.degree. phase relationship for defining said first and second halves of said cache cycle.
32. The cache system of claim 30 wherein control circuit means includes: first gating means coupled to receive a first timing signal from said timing means and said gating means being operative to generate an output signal for enabling the loading of address information into said address register during said first half of said cache cycle for accessing information from said levels of said cache store during said second half of said cache cycle; second gating means coupled to receive a second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register during said second interval for enabling access to information stored in said levels of said cache store during said first half of said cache cycle; and, said address switch input control terminals being connected to said first and second gating means, said address switch being conditioned by said coded signals for enabling said address switch to load said address register with said addresses from said first and second address sources during said first and second halves of said same cache cycle of operation.
33. The cache system of claim 32 wherein each of said commands includes a command code and an address and said another one of said address sources includes: an input circuit means coupled to said processing unit for receiving said address of each said command and said input circuit means being connected to said first one of said sets of input terminals of said address switch, said input circuit means being operative to apply said command address specifying a word location within each of said levels of said cache store from which an operand word is to be fetched or into which an operand word is to be written during said second half of said cache cycle.
34. The cache system of claim 33 wherein said one of said address sources includes: an instruction address register coupled to said second one of said sets of input terminals of said address switch, said instruction address register including a number of bit positions, a group of said bit positions for storing an address specifying a next word location within said levels of said cache store from which an instruction word is to be accessed during said first half of said cache cycle.
35. The cache system of claim 34 wherein further one of said number of address sources includes: a buffer for storing at least one address derived from a command which has a command code specifying a read type operation, said address specifying the word location within said cache store into which the information requested from said main store by said command is to be written; and, means coupled to said buffer and to said address switch, said means for applying said address to a further one of said sets of input terminals of said address switch for loading into said address register enabling the writing of said information into said cache store during said first half of said cache cycle.
36. The cache system of claim 35 wherein said control circuit means further includes third gating means for generating memory write enable signals enabling said requested information to be written into said cache store during said first half of said cache cycle, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into said address register.
37. The cache system of claim 36 wherein said system further includes: instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said cache store; and, inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said cache store during said first half of said cache cycle.
38. The cache system of claim 37 wherein said control means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first half of said cache cycle, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said predetermined type of command to generate a control signal for conditioning said address switch to select an address from said instruction address register for loading into said address register during said first half for accessing an instruction from said levels of said cache store during said second half of said cache cycle.
39. The cache system of claim 30 wherein each of said commands includes a command code and an address and wherein each level of said cache store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache system further including: a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said cache store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address; comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said cache store; and, directory level control means coupled to said split cycle timing means to said comparison means and to said cache store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second half of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without interfering with transferring instruction words requested by said data processing unit.