Flash Lamp Drive Circuit

The present invention relates to a flash lamp drive circuit of the type wherein energy is stored by a capacitance and supplied to the lamp when an ionization pulse is applied thereto.

Although flash lamp drive circuits of this type are known in the art, high energy must be supplied by the capacitance in such drive circuits when high intensity ultraviolet radiation is to be generated by the lamp. Known drive circuits accomplish this by first charging the capacitance to a high voltage level and at some later time applying an ionization pulse to the lamp which then draws the stored energy from the capacitance. The high voltage capacitors which must be utilized in such high intensity ultraviolet applications are expensive and have a shortened life expectancy due to the length of the energy storage duration encountered in prior art flash drive circuits. Therefore, such circuits require continual attention and their maintenance costs are very high.

The flash lamp drive circuit of this invention extends the life expectancy of the high voltage capacitors in its energy storing capacitance by charging them to a threshold energy level in response to a trigger signal and by applying the ionization pulse to the lamp to discharge that capacitance therethrough when the stored energy level reaches a desired threshold. This circuit considerably shortens the period for which the high voltage capacitors must store energy. In one preferred embodiment, a power supply means for selectively charging the capacitance to store energy therein and a delay means for applying the ionization pulse to the lamp are simultaneously activated by the trigger signal. After some predetermined delay time, the ionization pulse is applied when the threshold energy level has been stored in the capacitance. A reset means for inactivating both the power supply means and the delay means after each trigger signal is also included in this embodiment.

In the drawing, a block diagram of the invention is illustrated in the sole FIGURE, and a schematic diagram of the preferred embodiments is also incorporated therein.

In the sole FIGURE, a flash drive circuit 10 is shown of the type wherein energy is stored in a capacitance 12 and supplied to a Xenon lamp 14 when an ionization pulse is applied thereto. Flash drive circuit 10 also includes a control means 16 for charging the capacitance 12 to a threshold energy level in response to a trigger signal and for applying an ionization pulse to the lamp 14 to discharge the capacitance 12 therethrough when the threshold energy level is reached. Capacitance 12 may include any number of capacitors connected in any electrical arrangement that is suitable to the required threshold energy level, such as a voltage multiplying arrangement. The flash occurs while the energy stored in capacitance 12 is being discharged through the lamp 14 and the capacitance 12 remains discharged thereafter until another trigger signal is applied. Consequently, energy is only stored in the capacitance 12 during each flash cycle for the time between when the trigger signal is applied and when the threshold energy level is reached. Therefore, the energy storage duration encountered by the capacitance 12 in the flash drive circuit 10 is essentially minimized.

Although many embodiments of the control means 16 are possible, the block diagram of one preferred embodiment thereof is illustrated in the sole FIGURE where the trigger signal simultaneously activates a power supply means 18 for selectively charging the capacitance 12 to store energy therein and a delay means 20 for applying an ionization pulse to the lamp 14 at some predetermined time subsequent to the trigger signal. This embodiment also includes a reset means 22 for inactivating both the power supply means 18 and the delay means 20 after each trigger signal is applied. Because the power supply means 18 and the delay means 20 are simultaneously activated, charge is stored in the capacitance 12 for the delay time that elapses prior to when the ionization pulse is applied. Consequently, the threshold energy level that is supplied to the lamp 14 by the capacitance 12 is directly proportional to that delay time. Furthermore, the power supply means 18 and the delay means 20 are inactivated after the trigger signal has been applied, so that the lamp 14 could be continuously flashed at a frequency having a period substantially equal to the delay time.

Although many embodiments of the invention are possible in regard to the power supply means 18, the delay means 20 and the reset means 22, schematic diagrams for particular embodiments of these elements are shown in the sole FIGURE. Within the power supply means 18, an AC source 24 is connected through a switch means 26 for selectively controlling current flow in response to the trigger signal and applied to a rectifier means 28 for converting AC to DC. The output terminals of the rectifier means 28 are connected across the capacitance 12. Within the delay means 20, the secondary winding of a transformer 32 is disposed to direct stored energy from the capacitance 12 through the lamp 14 to a reference voltage rail such as ground, while the primary winding thereof has one side connected to ground and the other side connected to a voltage rail V through a capacitor C.sub.1. Also connected between the rail V and ground is the main conduction path of an SCR 34 having its gate electrode connected through a relaxation oscillator 36 to respond to the trigger signal. Within the reset means 22, a DC source 38 is applied to the rail V through a series regulator 40 and a capacitor C.sub.2 is connected between the rail V and a reference voltage input of the series regulator 40. Also connected between the rail V and ground is a resistor R.sub.1 in series with the main conduction path of an SCR 42 having its gate electrode connected to the trigger signal. The input to both the switch means 26 in the power supply means 18 and the relaxation oscillator 36 in the delay means 20 are connected between R.sub.1 and the SCR 42 to respond to the trigger signal.

Power supply means 18 is activated when switch means 26 is rendered conductive by the trigger signal to pass alternating current from source 24 to rectifier means 28 and charge is then applied to the capacitance 12 so that energy is stored therein. Delay means 20 is activated when relaxation oscillator 36 is energized by the trigger signal to render SCR 34 conductive during its first cycle of operation. C.sub.1 is then discharged through SCR 34 to cause current flow in the primary winding of transformer 32, responsive to which the ionization pulse for the lamp 14 is thereby induced in the secondary winding of transformer 32. Power supply means 18 and delay means 20 are activated simultaneously by the voltage change that occurs across R.sub.1 when the trigger signal is applied to render SCR 42 conductive within the reset means 22. The level of rail V is developed within the reset means 22 from the source 38 through the operation of the series regulator 40 and C.sub.2 within the reset means 22 is discharged simultaneously with C.sub.1 when SCR 34 becomes conductive within the delay means 20 to load down the rail V. Conduction through the series regulator 40 is terminated when the discharge pulse of C.sub.2 is applied to the reference voltage input thereof and holding current is then no longer maintained through the SCR's 34 and 42 which become nonconductive. Although conduction through the series regulator 40 resumes immediately thereafter to restore the level of the rail V and thereby recharge C.sub.1 and C.sub.2, SCR's 34 and 42 remain non-conductive. Therefore, the power supply means 18 and the delay means 20 are reset, in that they remain inactivated until the next trigger signal is applied to energize the relaxation oscillator 36 and to render the switch means 28 conductive. During this reset interval, capacitance 12 remains discharged to lessen the high voltage stress duration encountered by the capacitors therein.

It should be understood by those skilled in the art that many variations are possible in the circuitry of the power supply means 18, or the delay means 20, or the reset means 22. In the power supply means 18, a transformer means 44 for regulating the input voltage level of the rectifier means 28 could be utilized, which in one embodiment (not specifically shown) that has been reduced to practice included regulating, amplitude setting, and step-up stages. The switch means 26 could be of solid state construction and could be included in an integrated circuit along with digital circuitry for generating the trigger signal. Also, the rectifier means 28 could be of a conventional type such as the diode bridge which is shown in the sole FIGURE. Furthermore, a DC source (not shown) having predetermined output characteristics could be utilized to charge the capacitance 12 through the switching means 26 to thereby do away with both the AC source 24 and the rectifier means 28 in the sole FIGURE. In the delay means 20, the relaxation oscillator 36 would be of a conventional type such as that shown in the sole FIGURE where a unijunction transistor Q.sub.1 having its emitter connected between a resistor R.sub.2 and a capacitor C.sub.3 which are series connected across R.sub.1 in the reset means 22. The base-one and base-two of Q.sub.1 are series connected across R.sub.1 through resistors R.sub.3 and R.sub.4 respectively, while the oscillatory output is applied to the gate electrode of the SCR 34 from between Q.sub.1 and R.sub.3. Furthermore, the transformer 32 is shown to be a step-up type; however, this is not a requirement where the rail V is of sufficient magnitude. In the reset means 22, the series regulator 40 would be of a conventional type such as that shown in the sole FIGURE where bipolar transistors Q.sub.2, Q.sub.3 and Q.sub.4 of the same conductivity type are disposed in a regulator circuit arrangement similar to that disclosed in the applicant's U.S. Pat. No. 3,560,842. Q.sub.2 and Q.sub.3 are connected in a Darlington arrangement which is driven through the main conduction path of Q.sub.4. The base electrode of Q.sub.4 is connected between resistors R.sub.5 and R.sub.6 which are series connected from the rail V to ground, while the base of Q.sub.3 is connected to the rail V through a resistor R.sub.7. Furthermore, the emitter electrode of Q.sub.4 is connected between a resistor R.sub.8 and a Zener diode D.sub.1 which are series connected from the DC source 38 to ground. C.sub.2 is connected from the rail V to the emitter electrode of Q.sub.4 which is the reference voltage input whereat conductivity through the series regulator 40 is controlled. Also, the series regulator 40 could be driven from the AC source 24 within the power supply means 18 through a rectifier means (not shown) for converting AC to DC to thereby do away with the separate DC source 38. Furthermore, a resistor (not shown) could be connected between the rail V and the anode of the SCR 34 to facilitate turning that SCR off by limiting current flow therebetween. However, this resistor as well as C.sub.2 could be replaced by another SCR in an embodiment (not specifically shown) that has been reduced to practice. The main conduction path of this SCR would be connected to shunt the reference voltage input of the regulator 40 to ground and its gate electrode would be connected through the relaxation oscillator 36 to respond to the trigger signal. This SCR assures termination of current flow through the SCR's 34 and 42 by terminating the output from the regulator 40 concurrently with SCR 34 being rendered conductive through the oscillator 36 by the trigger signal.

Consequently this invention has been disclosed herein by describing only a few embodiments thereof and numerous changes in the details of construction and the combination or arrangement of parts could be made in these described embodiments without departing from the true scope and spirit of the invention. Therefore, the present disclosure should be construed as illustrative rather than limiting.