System for Indicating and Controlling Dispensing of Beverages

The present invention relates generally to a system for indicating and controlling the dispensing of beverages from a plurality of remote locations, and, more particularly, to a beverage dispensing system wherein a central station includes a data processor and a keyboard, and each of the remote stations includes a data processor that is addressed by signals from the central station.

A commercial system has been developed whereby beverages are dispensed from a plurality of reservoirs, at each of a plurality of remote locations, such as hotel rooms. In response to each dispensing operation, a signal is transmitted to a central location, such as the front desk of the hotel. At the central location, a counter responds each time a beverage is dispensed from each location, to provide a count indicative of the total number of dispensing operations at each location. Generally, alcoholic beverages are dispensed from the reservoirs whereby the count is indicative of the total number of drinks that are served in a hotel room. When a user of the hotel room checks out, the total number of drinks, as indicated by the counter, is multiplied by a fixed factor, indicative of the cost of each drink, to derive an indication of the amount of money to be added to a room rental bill of an occupant of the room.

The prior art system employs relays at the remote locations and electromechanical counters at the central station. For each remote location, there is a separate lead extending from the central console to the relays. Hence, installation and maintenance of the prior art system are difficult, time consuming and expensive, and become onerous for a system involving more than 20 remote locations. In addition, the space required at the central console for more than 20 units is extensive.

The prior art system also suffers because it is relatively inflexible. If beverages, such as liquor, can be dispensed only during certain times, manual operations must be performed to disable the remote stations. Also, if it is desired to change the location of the dispensing apparatus, for example, from one room to another, or to selectively install more than one dispensing installation in a single room, as may be desirable for receptions, a general rewiring is necessary. Obviously, such a rewiring is generally not feasible. In the prior art system, the use of only one wire between each remote location and the central console, severely limits the amount of data which can be transmitted between the remote locations and the central stations. Thereby the transmission between the remote location and central console of valuable information is limited; exemplary of this information are indications of which reservoirs are empty and which locations are properly operating. It is therefore necessary for an actual inspection to be made of the remote location dispensing installation to determine auxiliary information, such as which reservoirs are empty and which need maintenance. In the prior art system, it is necessary for the charge for each dispensing operation to be the same, regardless of the nature of the liquid being dispensed. This is because there is a summation of the total number of dispensing operations from each remote location, rather than an indication of the number of dispensing operations from individual reservoirs at a particular location.

It is, accordingly, an object of the present invention to provide a new and improved system for indicating and controlling the dispensing of beverages from a plurality of locations in response to communications established between the remote locations and a central station.

Another object of the invention is to provide a new and improved, flexible system that enables only a single pair of leads to communicate information from a central location to each of a plurality of remote locations, at each of which is located a plurality of beverage reservoirs.

Still another object of the invention is to provide a new and improved remote control and indicating system for plural reservoirs at each of several remote locations, wherein for each location there are performed several operations, such as determining which reservoirs are empty, as well as diagnostic procedures.

A further object of the invention is to provide a new and improved communication system for indicating and controlling the dispensing of beverages from a plurality of liquid reservoirs, at each of a plurality of locations remote from a central location, wherein the communication system and circuits associated therewith require a relatively small amount of maintenance, and wherein control and diagnostic procedures for units at the remote locations can be performed exclusively at the central station.

In accordance with the present invention, a new and improved system for indicating and controlling the dispensing of beverages from plural reservoirs at each of a plurality of remote location units includes a central console for deriving the indications and control signals for the remote units. The remote units also derive command signals in response to dispensing command inputs from customers and transduced signals responsive to reservoir conditions, such as a reservoir being empty. The console includes a keyboard for deriving data and command signals, as well as a data processor responsive to the keyboard signals as well as locally and remotely derived command signals. The data processor responds to these signals to derive addressing signals for the remote units. The console includes an electronic display responsive to the keyboard data and to the command signals.

At each of the units, a plurality of liquid flow controllers are provided, whereby one of the flow controllers is provided for each reservoir. A dispensing command input that can be activated by a room occupant is provided at each unit for each flow controller. A data processor at each remote unit selectively derives control signals for the flow of liquid from the reservoirs in response to the dispensing command input. The data processor at each unit derives signals indicative of the amount of beverage dispensed from each reservoir, i.e., counts the number of dispensed drinks. The data processor at each unit feeds signals indicative of the number of each type of dispensed drink to the central console data processor in response to an address of the unit at the particular location being transmitted to the unit data processor from the console data processor.

By employing an addressing system for the remote unit data processors, information between all of the remote units and the central console can be transmitted via only a pair of leads extending between the central console and all of the remote units. In a preferred configuration, the leads are the AC power leads of the building or buildings where the system is located. Hence, there is no need to install and maintain a multi-wire communication system.

The keyboard and data processor at the central console, and the data processor at each of the remote units, enable the present invention to have great flexibility. For example, remote indications of empties can be derived either in response to a keyboard entry for a particular remote location or in response to an automatic sequencing arrangement wherein indications of only which bottles in which remote units are displayed at the console. In addition, the present invention includes clock circuitry that keeps track of time, as a function of fractions of a second, seconds, minutes, hours, days of the week, and days of the month. The timing feature also enables automatic maintenance of legal hours for different situations, such as different legal hours on different days of the week, as well as an automatic signalling of an indication that only a few minutes remain before the remote station must become inoperative because legal hours are about to expire. In addition, different rates can be charged for drinks dispensed from different reservoirs and different rates can be charged as a function of time (happy hours). The dispensing times automatically established by the clock circuitry can be overriden at the front desk if it is desired to prevent a customer from purchasing any beverages, because, e.g. of election day.

The flexibility of the present invention enables diagnostic testing of the remote units to be performed by the single press of a key on the keyboard. It is also possible to assign multiple dispensing units, each including a plurality of dispensing reservoirs, to a single location, as may be necessary in connection with receptions. Another feature of the invention is that an alarm signal is activated at the console in response to tampering at the remote unit. Also, the flexibility of the electronic system enables features to be easily added by making a slight modification to the data processor at the central console without changing any connections between the central console and the remote locations.

It is, therefore, a further object of the invention to provide a new and improved system for indicating and controlling dispensing of beverages from a plurality of units remote from a central location, wherein the remote units and central location are connected to each other exclusively by power lines of a building or group of buildings where the system is located.

A further object of the invention is to provide a new and improved highly flexible, easily modified system for indicating and controlling the dispensing of liquids from a plurality of remote locations that are interconnected with a central console.

The above and still further objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description of one specific embodiment thereof, especially when taken in conjunction with the accompanying drawing.

FIG. 1 is an overall system diagram of a preferred embodiment of the present invention;

FIG. 2 is a view of the topological arrangement of a keyboard adapted to be utilized in connection with the system of FIG. 1;

FIGS. 3(A)-(E) are a block diagram of the data processor at the central location of the system of FIG. 1;

FIGS. 4(A)-(E) are a block diagram of the data processor at a remote location in the system of FIG. 1;

FIGS. 5(A)-(B) are a flow diagram of the operations performed at the station data processor; and

FIGS. 6(A)-(B) are a flow diagram of the operations performed at the console data processor.

Reference is now made to FIG. 1 of the drawing wherein there is illustrated a central station or front desk console 11 that is interconnected by a pair of leads 12 of a power wiring system to units 14 at remote locations. Power leads 12 are part of a hotel power distribution system activated by a suitable AC source 15, while console 11 is at the hotel front desk. Each of units 14 is in a different room of the hotel, with the units for rooms 1, 2, . . . , K being shown in the drawing. It is to be understood that more than one unit can be assigned to a particular room or location, as described infra.

Detailed aspects of unit 14 at only room K are illustrated, because the apparatus at each of units 14 can be considered as identical. Conventional 2 to 3 prong outlet connectors 17 at the front desk and in each of the rooms supply power to console 11 and to all of units 14 via power leads 12 which also interconnect the console and units for communication purposes. There is no substantial interference between the AC power on leads 12 and pulse signals transmitted between stations 14 and console 11 on leads 12 because the pulses have a much higher frequency than the AC power. If AC power source 15 includes noise or transients that might appear as pulses transmitted between stations 14 and console 11, the signal communicated between the stations and console has a format that enables errors to be detected. Console 11 includes an AC to DC power converter 21 connected directly to plug 17 and which supplies appropriate DC power levels to each of the electronic devices included in console 11, viz.: keyboard 22, 16-character, 16-segment alphanumeric, electronic display 23 (preferably of the light emitting diode, LED, type), and data processor 24 that includes an oscillator, microprocessor, buffers, memory, drivers, and a universal asynchronous receiver-transmitter, and auxiliary power supply 25. Power supply 25 includes a rechargeable battery so that in the event of a failure of AC source 15, volatile, erasable memory elements of data processor 24 are not adversely affected. Data processor 24 includes a pair of output leads 26, connected to plug 17, which enable serial data bits to be transmitted from data processor 24 to a data processor at each of units 14 via power leads 12. Front desk console 11 also includes a speaker 27 responsive to signals from data processor 24 to activate an audio alarm in the response to certain signals, such as an indication that tampering has occurred at a remote unit 14. Console 11 also includes a key lock switch 28 which can be closed to activate the console only by insertion of an appropriate key into a locking mechanism.

Keyboard 22, display 23, and data processor 24 are interconnected with each other so that signals from the keyboard are supplied to the data processor and signals from the data processor are supplied to the display. Display 23 responds to signals from data processor 24 to derive alphanumeric indications of signals derived from keyboard 22, as well as signals supplied to data processor 24 by units 14.

Keyboard 22 is connected to data processor 24 by an 11-lead bus 31. Six of the leads in bus 31 are provided for a six parallel bit signal that is derived in response to activation of 22 data keys of keyboard 22. Four of the leads of bus 31 are provided for four function keys of keyboard 22, while the remaining lead of bus 31 is provided for a strobe signal that is derived from keyboard 22, with each key activation of the keyboard.

Keyboard 22, FIG. 2, includes ten numerical keys 32, one of which is provided for each of the numerals 0-9, as well as a "." key 33 for a decimal point. TIME and DATE keys 34 and 35 are respectively activated to change stored indications of local time and date, as is necessary if there is an appreciable error in accumulated local time or a change from daylight time to standard time, or vice versa, as well as to insert a new date at the beginning of each month. Activation of TIME key 34 is accompanied by entries of numerical keys 32 to indicate time in hours (00-23) and minutes (00-59) while activation of DATE key 35 is accompanied by entries of keys 32 to indicate day of the week (1-7), day of the month (1-31), month (1-12) and year of the century (00-99). HOURS key 36 is activated to insert the hours during which alcoholic beverages may be legally dispensed from the equipment at units 14 for different days of the week. Key 36 is activated seven times, one for each day of the week. Each activation of HOURS key 36 is accompanied by a one digit numerical key entry (1-7) for the day of the week and two sets of numerical key entries for hours (0-23) and minutes (0-59); these two sets of entries are for beginning and end of legal hours, respectively. The amount of money charged for beverages dispensed from different reservoirs 51-55 at units 14 is controlled by depressing RATE key 37. Depression of key 37 is accompanied by depression of one numeral key 32 (1-5) to indicate the reservoir number, one numeral key for dollar amount of each drink, "." key 33 and two numeral keys for the number of cents. In response to activation of keys 34, 35, 36 and 37, display 23 is activated to indicate the nature of the activated key and the accompanying numerical values.

If an alarm has been sensed causing speaker 27 to be activated, an alarm flag at data processor 24 is reset by activating ALARM RESET key 38. If the operator realizes he has made a mistake, CANCEL KEYBOARD or CLEAR key 39 is activated. To obtain the total charge for a particular room, e.g., at the time of check out, the operator keys ROOM TOTAL key 41, and keys 32 for the room number. In response to activation of keys 41 and 32, the unit in the keyed room and the room number are indicated by display 23. If a tenant is checking out of his room, and it is desired to clear the room total, CLEAR ROOM TOTAL key 42 is depressed, after the charge information is displayed and before any other key, other than a numerical key 32 is activated.

NEXT key 43 is depressed by the operator of console 11 if the room total display indicates a plurality of units are located in a single room or location. Data processor 24 automatically addresses the plural units in reponse to each activation of key 43, whereby display 23 indicates the total for each of the units at a single location in response to each activation of key 43. In addition, key 43 is activated in combination with EMPTIES key 44 if the operator is making an analysis of units 14 to determine which units have empty dispensing reservoirs. Data processor 24 responds to each such activation of key 44 and then key 43 to address units 14 in sequence and receive signals back from the units having an empty reservoir. Data processor 24 responds to the signals from the units having empty reservoirs to activate display 23 to indicate the number of each room having an empty reservoir and the number assigned to the empty reservoir in the room. After the operator has appropriately noted the displayed information, he again activates key 43, whereupon data processor 24 continues to sequence the different units until the next unit having an empty reservoir is reached. The process is continued for each activation of NEXT key 43 until all of the units have been scanned.

To enable and disable, i.e., turn on and turn off, any of units 14 on a selective basis or the entire system, ENABLE key 45 and DISABLE key 46 are activated together with numerical keys for the room number. The entire system, i.e., all of units 14, can be enabled and disabled by activating key 45 or 46, in combination with two activations of the number NINE key 32 to indicate 99th floor, which is a code for the entire system.

Each of the units is provided is provided with a unit number. To assign a particular unit number to a given room, ASSIGNMENT key 47 is activated. Then, the unit number and room number are entered via keys 32. If it is desired to perform a diagnostic routine on a particular one of stations 14, DIAGNOSTIC key 48 is activated, after which the room number where the station is located is entered via keys 32.

The keys of keyboard 22 are connected with ten lines of bus 31 so that CANCEL key 39, ROOM TOTAL key 41, DIAGNOSTIC key 48 and ASSIGNMENT key 47 are individually connected to the four lines provided for the four function keys. The remaining keys of keyboard 22 are connected to six other leads of bus 32 to form a six-bit parallel binary signal. The manner in which data processor 24 responds to the keys of keyboard 22 to activate display 23 and units 14 and the apparatus of these devices is described in greater detail infra.

At unit 14, in room K, five inverted beverage reservoirs 51-55, preferably liquor bottles or the like, are provided. A beverage is dispensed from each of bottles 51-55 in response to selective activation of valves 61-65, respectively, connected in a separate line for each of the different reservoirs. Connected to a neck of each of reservoirs 51-55 is a resistance type liquid sensor 71-75, each of which derives a binary output signal having high and low levels, respectively, indicative of a conducting liquid being in and out of contact with the sensor. Thereby, sensors 71-75 derive binary signals respectively indicative of whether reservoirs 51-55 are or are not empty. Associated with each of reservoirs 51-55 are manually activated push button switches 81-85, which are activated by an occupant of room K when he desires to have a beverage dispensed from reservoirs 51-55, respectively. To provide a visual indication that reservoirs 51-55 are empty, light emitting diodes 91-95 are respectively provided for reservoirs 51-55.

Valves 61-65, sensors 71-75, switches 81-85, and light emitting diodes 91-95 are interconnected via buses 96, 97, 98, and 99, each having 5 signal leads, to data processor 101. Data processor 101 is supplied with DC operating power by power supply 102, which is connected to outlet 16 in room K by plug connector 17. Power supply 102 supplies appropriate power to data processor 101 and to valves 61-65 so that solenoids within these valves can be activated in response to signals from the data processor. Connector plug 17, in addition to supplying AC current to power supply 102, is connected via a pair of lead wires to a pair of signal terminals of data processor 101.

Data processor 101 is also responsive to a unit number select input signal source 103, which derives a parallel, eight-bit binary signal indicative of the unit number; the eight-bit signal is coupled from source 103 to data processor 101 via eight-lead bus 104. Data processor 101 is also responsive to manually activated switches 105 and 106, as well as switch 107 that is responsive to a forced door sensor 108. Forced door sensor 108 is activated whenever a door (not shown) is opened in a cabinet where reservoirs 51-55 are located. Switch 105 is closed by maintenance personnel when it is desired to calibrate the activation time of the solenoids in valves 61-65, thereby to control the amount of beverage dispensed from reservoirs 51-55 in response to each activation of switch buttons 81-85. Enable switch 106 is activated by the room occupant to assure that minors who may be in the room do not illegally activate buttons 81-85. In many instances, therefore, it is desirable for switch 106 to be controlled by a key.

Data processor 101 includes a timing source, microprocessor, controller chip, a programmable read-only memory (PROM), a random access memory (RAM), decoding circuitry, buffer circuitry, and a universal asynchronous receiver-transmitter, as described in detail infra in connection with FIG. 3. These elements of data processor 101 respond to signals from sensors 71-75, switches 81-85, unit number select source 103, switches 105-107 and signals from console 11 to activate valves 61-65, as well as light emitting diodes 91-95. Each of valves 61-65 is respectively activated for a predetermined interval in response to each manual activation of switches 81-85, unless one of the switches is activated before the open valve has been closed, in which case the switch activation is ignored. In response to sensors 71-75 detecting that reservoirs 51-55 are respectively empty, LEDs 19-95 are deactivated so no light is derived from them.

In response to activation of ROOM TOTAL key 41 and the room number from keys 32 of keyboard 23, data processor 101 is addressed by a unit number signal transmitted to it from console 11 to initiate a communication link. The address is recognized by comparing the unit number derived from source 103 with the address unit number derived from console data processor 24. Data are also transmitted from data processor 101 to data processor 24 to indicate that a door of the cabinet has been opened, as detected by sensor 108. Normally, after unit 14 at room K has been addressed, data processor 101 supplies console 11 with signals indicative of the total number of dispensing operations associated with each of reservoirs 51-55 for a particular occupancy of room K. Data processor 101 supplies, to data processor 24, signals indicative of which of reservoirs 51-55 is empty, in response to activation of EMPTIES key 44 and (1) keys 32 for the room number or (2) NEXT key 43.

Unit 14 includes two additional visual, LED indicators 110 and 111 which are supplied with bilevel signals by data processor 101. Data processor 101 responds to time indicating signals derived from data processor 24 so LED 110 is activated to a light emitting condition during hours while the dispensing of beverages from reservoirs 51-54 is legal. LED 111 is activated by data processor 101 in response to signals from data processor 24, when the console data processor derives an indication that only a predetermined time exists prior to the expiration time of the hours when liquid can be legally dispensed from reservoirs 51-55. This warns the room occupant that legal hours are about to expire so he can activate switches 81-85 multiple times during the interval immediately preceding the expiration of legal hours.

Reference is now made to FIG. 3 of the drawing wherein there is illustrated, in block diagram form, a preferred embodiment of data processor 24 at console 11. Data processor 24 includes a microprocessor 111, preferably an INTEL 8080A microprocessor, as described for example, on pages 256-261 of the book "Microprocessors and Small Digital Computer Systems for Engineers and Scientists", written by Granino A. Korn, published by McGraw-Hill Book Co., 1977 edition. Microprocessor 111 is a monolithic NMOS 8-bit central processing unit chip including an 8-bit arithmetic logic unit/accumulator subsystem, an 8-bit instruction register, an 8-bit processor status word register (only 5 bits are used), and six 8-bit scratchpad registers that can be paired to form three 16-bit stack pointer registers. Each input-output word of microprocessor 111 is a sequential two byte instruction derived as address bits. The second byte is a binary value for any one of 256 memory addresses, while the first byte includes four bits that control the derivation of control signals IN00-IN70 and OUT00-OUT70, as described infra.

Microprocessor 111 includes forty input-output pins, numbered on the drawing with lead lines immediately outside of the rectangle designating the microprocessor. The microprocessor is connected in the present configuration so that it includes a 12 parallel bit address bus for address bits A0-A11, and an 8-bit, bidirectional data bus 100 for data bits D0-D7; data bus 100 can be operated to handle an 8-bit byte or a 16-bit byte including two sequential sets of 8 bits. Microprocessor 111 is responsive to appropriate DC voltage levels applied to its DC power supply pins 2, 20, 11 and 28. In addition, hold pin 13 is connected to a zero volt level, to prevent activation of the hold function of microprocessor 111. Microprocessor 111 includes an interrupt pin (INT) 14 which is selectively responsive to signals from an interrupt source. Microprocessor 111 includes output pins 17, 18, 19 and 21 on which are respectively derived signals indicating that: (1) microprocessor 111 has placed data on data bus 100, (2) microprocessor 111 is ready to read data bits D0-D7, (3) a data bus cycle is to start, and (4) microprocessor 111 is ready to write data bits D0-D7. The first clock signal at pin 22 after the occurrence of a sync signal strobes control bits D0-D7 from data bus 100 into the process status register within microprocessor 111. These bits are latched by the status register to determine bus operations during the remainder of a cycle while data bus 100 is activated.

Address bits A0-A11 at output pins 25-35, 1 and 40 of microprocessor 111, effectively form an address bus. The address bits are fed as an addressing signal to memory circuitry (described infra) via buffers 114 and 115, which are preferably standard 74S241, 8-bit binary buffer chips.

Microprocessor 111 is responsive to signals derived from oscillator and frequency divider 112, preferably an INTEL 8224 chip. Oscillator and frequency divider 112 is responsive to an 18 mHz crystal 113, as well as to DC power supply voltages applied to pins 2, 3, 8, 9 and 16. Oscillator and frequency divider 112 includes a pair of 2 mHz output pins 10 and 11, on which are derived signals that are phase displaced from each other by 180.degree., and respectively applied to pins 15 and 22 of microprocessor 111. Oscillator and frequency divider 112 includes output pins 1 and 4 on which are derived positive, binary one levels that are respectively applied to reset pin 12 and ready (RDY) pin 23 of microprocessor 111. Oscillator and frequency divider 112 includes an input pin 5 responsive to the signal at sync terminal 19 of microprocessor 111.

Data bits D0-D7 are selectively coupled in either direction through controller chip 116, preferably an INTEL 8238 chip. Controller chip 116 includes, for data bits D0-D7, pins 6, 7, 8, 10, 12, 15, 19 and 21, connected to exchange signals in either direction with pins 3-10 of microprocessor 111. The data bits are selectively coupled in either direction to other circuitry in data processor 24 from controller 116 via pins 5, 9, 11, 13, 16, 17, 18 and 20. Controller 116 includes control output pins 24-27 on which the controller selectively applies enable signals to: (1) command data to be read from the data processor memory into microprocessor 111, (2) command data to be written from microprocessor 111 into data processor memory, (3) input/output read (I/O R) command, and (4) input/output write (I/O W) command. Controller 116 includes a strobe control input pin (STSTB) 1, connected to pin 7 of oscillator and frequency divider 112 to provide a strobe control for bits transmitted between the controller chip data bus pins to the data bus pins of microprocessor 111. Pins 2, 3 and 4 of controller 116 are responsive to the signals at pins 21, 18 and 17 of microprocessor 111. The signals applied to pins 2-4 of controller 116 enable data signals to be coupled between pins 5, 9, 11 etc. of the controller and pins 3-10 of microprocessor 111. The remaining pins of controller 116 are connected to constant DC voltages, for either power supply purposes or to prevent the functions associated with these pins from being enabled.

Ten address bits A0-A9 derived from microprocessor 111 are fed through buffers 114 and 115 on an address bus to parallel input terminals of programmable read-only memories (PROMs) 117 and 118, preferably of the INTEL 2708 type, and which constitute the non-volatile portion of the memory of data processor 24. In the preferred embodiment, each of PROMs 117 and 118 includes 1024 8 bit bytes. Each of PROMs 117 and 118 includes 8 parallel output bits, supplied to pins 9-17 thereof, as well as address input pins 1-8, 22 and 23. Each of PROMs 117 and 118 includes an input pin 20, which when supplied with a binary zero signal, enables the particular PROM to be read out at the address indicated by the bits A0-A9. PROMs 117 and 118 store, in firmware, the program signals of data processor 24, as well as signals to activate display 23 with certain messages in response to signals from console 11 and units 14.

The memory data processor 24 also includes four random access memory (RAM) chips 121-124, each having address input pins 1-7 and 17-15, respectively driven by address bits A0-A9. Each of RAMs 121-124 is capable of storing 1024 4-bit bytes and therefore includes four output pins 11-14, on which are derived a four bit output signal of each RAM. RAM chips 121-124 also include a chip select (CS) input pin 8 and a write enable (WE) input pin 10. In response to only CS pin 8 being supplied with an enabling signal, the signal stored at the address indicated by address bits A0-A9 of the particular RAM is read out on pins 11-14. In response to pin CS and WE pin 8 and 10 both being enabled by input signals, the signal at pins 11-14 is written into the RAM address designated by address bits A0-A9. RAMs 121-124 are arranged so that RAMs 121 and 122, together, actually comprise a single 8-bit RAM because the CS pins of RAMs 121 and 122 are connected in parallel to each other, while RAMs 123 and 124, together, function as a single 8-bit RAM because the CS pins thereof are also connected in parallel, but to a different source.

Selection of which of PROMs 117 or 118 or RAMs 121-124 is activated to be responsive to address bits A0-A9 and the operating mode of the RAMs is in response to address bits A10 and A11, as well as the read from memory (MEMR) and write into memory (MEMW) signals derived from pins 24 and 26 of controller 116. These signals are combined in address decode circuit 125, including an array of inverters, AND gates, NAND gates, and NOR gates, and having output signal leads 126-130; lead 126 is connected to the CS input pin of PROM 117, lead 127 is connected to the CS input pin of PROM 118, lead 128 is connected to the WE input pin of RAMs 121-124, lead 129 is connected to the CS input pins of RAMs 121 and 122, and lead 130 is connected to the CS input pins of RAMs 123 and 124. Address decoder 125 is also responsive to the voltage derived from power supply 21 so that the contents of RAMs 121-124 cannot be changed if there is a power failure.

A power failure is sensed by determining if the power level of supply 21 drops below a minimum value; e.g., a normal 5.0 volt source is sensed to determine if the voltage thereof drops below 4.7 volts. The power supply voltage is sensed by circuit 132, including an operational amplifier 133, a Zener diode 134 and appropriate components and connections to power supply 21 to enable a bi-level DC voltage to be derived on lead 135 to indicate whether the voltage of power supply 21 is above or below the minimum value.

Address bits A10 and A11 are respectively combined with the read from memory and write into memory signals MEMR and MEMW and with the signal on lead 135 to control activation of PROMs 117, 118 and 121-124 in accordance with the following criteria:

These signals are combined by decoder 125 to supply an enabling signal to the CS input pin of PROM 117, to enable the data stored at the address indicated by bits A0-A9 to be read out as a parallel 8-bit byte at pins 9-17. The operations associated with lines 3-6 of Table I are inhibited if the sensed voltage of power supply 21 is less than a predetermined value, in response to the binary zero level on lead 135.

If the voltage of power supply 21 should drop below the predetermined level, a keep alive voltage level is supplied to RAMs 121-124 by re-chargeable battery 136. During normal operation, battery 136 is charged by the output voltage of power supply 21 through PNP transistor 137. In the event of the power supply voltage dropping below the predetermined level in response to a power line failure, battery 136 is isolated from power supply 21 and a keep alive voltage is supplied by the battery to DC power input pins 18 of RAMs 121. Normally, power supply pins 18 of RAMs 121 are supplied with a DC positive voltage that is fed to them through the collector of PNP transistor 137.

PROMs 117 and 118 are pre-loaded with firmware program information necessary to execute the various operations which the apparatus of the present invention performs. RAMs 121-124 are supplied with and store data, such as read/write information, time, the total number of drinks which have been dispensed from all of the reservoirs 51-55 of the various units 14, the price of each drink from each reservoir, which of the reservoirs are empty, etc.

Corresponding output pins of PROMs 117 and 118, as well as corresponding output pins of paired RAMs 121, 122 and 123, 124 are connected in parallel to data bus 100; the common connections of PROMs 117, 118 and RAMs 121-124 to bus 100 are via a buffer 141, including three state, 4 bit buffer chips 142 and 143 that are controlled in parallel to pass signals in either direction or to block signals. Each of buffer chips 142 and 143 includes a pair of input pins 1 and 15, respectively connected to be responsive to the output of address decoder 125 and the read from memory signal MEMR. Chips 142 and 143 respond to the signals applied in parallel to pins 1 thereof by address decoder 125 so that the buffers are normally disabled. With an enabling signal being applied to pins 1 of chips 142 and 143, signals can be read from PROMs 117 or 118 or RAMs 121, 122 or 123, 124 through buffer 141 to data bus 100. If enabling signals are simultaneously supplied to pins 1 and 15 of buffer chips 142 and 143 and to pins 1 of chips 142 and 143, signals can be read in the other direction from data bus 100 through buffer 141 into RAMs 121, 122 or 123, 124.

A further control for coupling signals to various elements of data processor 24 is attained by selectively enabled, three input to eight output decoders 145 and 146, driven in parallel by address bits A4-A7 derived from microprocessor 111. Bits A4-A7 have different combinations of values during different intervals of each one microsecond operating cycle of the program executed by data processor 24. Each of decoders 145,146 includes an enable input pin 5, responsive to address bit A7, as well as three decoding input pins 1, 2 and 3, respectively responsive to address bits A4, A5 and A6. Input pins 4 of decoders 145 and 146 are respectively responsive to I/OR and I/OW signals derived from pins 25 and 27 of controller 116. Thereby, decoder 145 is activated to be responsive to address bits A4-A6 only while it is enabled by address bit A7 and the I/OR signal, while decoder A6 is enabled by address bit A7 and the I/OW signal. Each of decoders 145 and 146 includes eight output pins 7-15, only one of which has a binary one signal at a time; the output pin having the binary one level is dependent upon the values of address bits A4-A6. The output signals of decoders 145 and 146 are respectively denominated IN00-IN70 and OUT00-OUT70. As described in detail infra, signals IN00-IN40 and OUT00-OUT50 respectively cause data processor 24 to perform certain functions during different times within each 1 .mu.s (microsecond) operating cycle associated with (1) signals being supplied to the data processor, and (2) signals derived from the data processor. Two .mu.s operating cycles form a complete microprocessor cycle time, so that 2-8 bit data outputs of the microprocessor can be multiplied to buffers of the 16 bit display deriving two consecutive cycle times.

Data bus 100 is responsive to the signals on 11-lead keyboard bus 31. Data bits D0-D5 of bus 100 are selectively responsive to the 6 coded bits B1-B6 which carry information from 21 "data" keys of keyboard 22. Data bits D0-D3 of data bus 100 are selectively responsive to the four function bits F1-F4 derived from function keys 39, 41, 47 and 48 of keyboard 22; all of the other keys are the data keys. Data bits D6 and D7 are selectively and respectively responsive to closure of key switch 28 and the strobe signal supplied by keyboard 22 to keyboard bus 31.

Bits B1-B6 and the strobe signal of keyboard bus 31 and a signal from switch 28 are selectively gated to data bus 100 via tri-state buffer 644 and buffer 645, responsive to keyboard function bits F1-F4. Buffers 644 and 645 are controlled by the signals at pins IN20, IN30 and OUT50 so that signals at the input pins of each buffer are gated into the buffer and then read out from the buffer. The strobe signal is coupled to buffer 644 under the control of signal OUT50 that is supplied as an enabling signal to a reset input of D flip-flop 646, having a C input terminal responsive to the signal on the strobe lead of keyboard bus 31. Flip-flop 646 has a Q output terminal on which is derived a signal that is supplied to pin 13 of buffer 644 and is selectively supplied to the buffer output pin 7 and thence to data bit line D7 of bus 100. Each time a key of keyboard 22 is struck, a signal is supplied to the C input terminal of flip-flop 646, causing an enabling level to be supplied by the Q output terminal of flip-flop 646 to input pin 13 of buffer 644. Flip-flop 646 is reset slightly after the leading edge of the strobe signal supplied to the C input terminal of the flip-flop, in response to signal OUT50. Thereby, flip-flop 646 derives a signal having a predetermined duration each time a key of keyboard 22 is activated. Buffers 644 and 645 are respectively enabled by signals IN20 and IN30 to couple the signals at the data input pins thereof to the output pins thereof once, at different times, during each one ms. program cycle of data processor 24. In response to the leading edge of enabling signal IN20, buffer 644 is activated so the six keyboard bits B1-B6 are supplied from buffer input pins 2, 4, 6, 8, 11 and 17 to storage elements in the buffer. In response to the trailing edge of signal IN20, the signals stored in the buffer elements are read out to buffer output pins 3, 9, 12, 14, 16 and 18. Buffer 645 responds similarly to the leading and trailing edges of signal IN30 to gate the signals at pins 2, 4, 6 and 17 to pins 3, 14, 16 and 18.

Signals supplied to data bus 100 are selectively supplied to 16 character, 16 segment LED display 23 under the control of signals OUT20, OUT30, and OUT40 via 8-bit latch chips 151, 152, 4 to 16-bit latch decoder 153, LED driver chips 154, 155, and common cathode driver chips 156, 157. In the preferred embodiment, chips 151 and 152 are 74LS273s, chip 153 is an MC14514B, chips 154 and 155 are 8816s, and chips 156 and 157 are 8863s. Latches 151, 152 and drivers 154, 155 respond to data bits D0-D7 to selectively activate the 16 segments of a single alphanumeric character of display 23, while decoder 153 and drivers 156, 157 control which of the sixteen characters of the display are to be activated with the character supplied to latches 151 and 152, during each 2 .mu.s cycle time of the microprocessor.

Pins 3, 4, 7, 8, 13, 14, 17 and 18 of chips 151 and 152 are respectively driven by D0-D7 bits of data bus 100. Eight bit latch 151 is loaded in response to an enable signal OUT20, during one .mu.s cycle time of data processor 24, while latch 152 is loaded during a subsequent 1 .mu.s operating cycle of the microprocessor, in response to an enable signal OUT30. The signals stored in latches 151 and 152 are fed through LED driver chips 154 and 155 to control illumination of the 16 segments of LED display 23.

Input pins 2, 3, 21 and 22 of latched decoder 153 are responsive to data bits D0-D3 of data bus 100, while load input pin 1 of the decoder is responsive to enable signal OUT40. Decoder 153 responds to data bits D0-D3 to translate these data bits into the 16 possible places where characters can be displayed on display 23. The timing of signals IN20, IN30, OUT20, OUT30, OUT40 and OUT50, as well as the connection of chips 154-157 to data bus 100 in such that alphanumeric controlling bits B1-B7 derived from keyboard 22 are supplied to drivers 154-157 at appropriate times to form displayed messages. The derivation times of these control signals are also such that enabling signals derived from pins 5 and 7 of buffer 144, as well as from pins 3, 14, 16 and 18 of buffer 145 are supplied to pins 7, 9, 11, 13, 16 and 20 of controller 116, to enable certain operations to be performed by microprocessor 111, which then derives signals to control memory chips 117, 118 and 121-124.

Data bits D0-D7 on data bus 100 are selectively supplied to and derived from universal asynchronous receiver transmitter (UART) 161, preferably a National Semi-conductor 5303 chip. UART 161 is selectively a serial to parallel or parallel to serial converter which supplies signals between data bus 100 and lines 26 which are connected to connector 17 at console 11. Eight serial bits, forming a byte, coupled through connector 17 to lines 22, are supplied to serial input (SI) terminal 20 of UART 161 via line receiver 162. When properly enabled, UART 161 responds to the 8 serial bits at pin 20 to form an 8-bit parallel output signal RR1-RR8, that is coupled to the UART output pins 5-12 respectively. The signal at pins 5-12 is selectively fed through buffer 163 to data bits D0-D7 of data bus 100. In contrast, parallel data bits D0-D7 on data bus 100 are supplied to pins 26-33 of UART 161 and are converted by the UART into eight serial bits that form a serial data byte. The 8-bit serial byte (SO) is derived from output pin 25 of UART 161 and applied to line driver 164. In response to each binary one signal at pin 25 of UART 161, one shot 164 derives a binary signal having a predetermined amplitude and duration, which binary signal is fed to leads 20 and connector 17 at console 11.

Clocking of signals between pin 20 and pins 5-12, as well as between pins 26-33 and pin 25 of UART 161, is in response to a 5 kHz signal derived from cascaded frequency dividers 165 and 166. Frequency divider 165 is responsive to a 2 mHz clock signal derived from pin 6 of oscillator and frequency divider 112; the 2 mHz signal at pin 6 of oscillator and frequency divider 112 has the same phase as the phase of the signal derived from pin 10 of the oscillator and frequency divider. The signal derived from pin 6 of oscillator and frequency divider 112 is supplied to a C input terminal of D flip-flop 167, which derives a one mHz output signal that is applied to an input pin of frequency divider 165. An output pin of frequency divider 165 derives a 10 kHz signal that is applied to an input of frequency divider 166, which in turn derives a 5 kHz clock input signal applied to UART 161.

Control of signals coupled between the inputs and outputs of UART 161 is in response to enabling signals IN00, IN10, OUT00 and OUT10. Parallel bits D0-D7 on bus 100 are gated from pins 26-33 into the parallel to serial converter of UART 161 in response to enabling signal OUT00 being derived during each microsecond operating cycle of data processor 24. These eight binary signals are then converter into a signal that can be derived as eight serial bits from pin 25 in response to the OUT10 signal, as coupled through inverter 167 to input pin 21 of UART 161. After signal OUT10 has been supplied to pin 21 of UART 161, the eight parallel bits are read out in sequence in response to the next eight clock pulses supplied by frequency divider 166 to UART 161. Serial data bits coupled to pin 21 are read out as a parallel 8-bit byte from pins 5-12 in response to enabling signal IN00 that is applied to pins 4 and 18 of UART 161. Signal IN00 is also applied through NOR gate 168 to input pin 1 of tri-state buffer 163 (preferably a LS241), and through inverter 169 to input pin 19 of the buffer. Buffer 163 is activated so that the signal at its input pins 2, 4, 6, 8, 11, 13, 15 and 17 is coupled to the buffer storage elements in response to the leading edge of the output NOR gate 168, and the buffer storage and elements are read out in response to the trailing edge of the output of NOR gate 168.

UART 161 includes 4 status bit pins 13, 14, 19 and 22 on which are respectively derived: (1) data available (DA) signal, (2) TBMT signal which indicates that a transmit buffer of UART 161 responsive to data bits D0-D7 is empty so that a new byte can be loaded into the UART input pins 26-33, (3) parity error (PE) error signal which indicates that the serial byte received at UART pin 20 has an incorrect parity, and (4) a framing error (FE) signal which indicates that a stop bit in the received serial signal is incorrectly located. The status bit signals derived at pins 13, 14, 19 and 22 are read out of UART 161 in response to enabling signal IN10 being supplied to input pin 16 of the UART. Signal IN10 is also applied through NOR gate 168 and inverter 169 to input pins 1 and 19 of buffer 163 to enable the four status bits to be coupled to the buffer output pins 3, 5, 7 and 18 of thence to data bits D0, D1, D6 and D7 of data bus line 100.

To activate audio alarm speaker 27, decoder 146 responds to a flag stored at address bits A4-A7 in RAMS 121-124. In response to the flag being set while address bits A5-A7 have a predetermined combination of values, decoder 146 derives output signal OUT70. The OUT70 signal is a short duration pulse that is coupled to an input pin of timer 171, having capacitors 172 connected thereto. Timer 171 derives a one second duration rectangular wave in response to enable signal IN70. The one second rectangular wave output of timer 171 is applied by inverter 173, which is cascaded with amplifier 174, to speaker 27 so an audio alarm is sounded.

The normal 1 .mu.s operating cycle of microprocessor 111 is interrupted when signals are (1) derived from keyboard 22, (2) are to be sent between console 1 and units 14, and (3) are to be supplied to display 23. In response to an interrupt, the normal sequencing of PROMS 117, 118 is terminated at different times depending on the interrupt. After the interrupt, microprocessor 111 includes a pointer to control PROMS 117, 118 so the program is restarted from the interrupted point. Microprocessor 111 is interrupted in response to a signal being derived from keyboard 23 so a binary one signal is fed to data bit D7 while buffer 44 is enabled by IN20 or in response to a signal from unit 14 being received so a binary one signal is fed to data bit D7 while the status word of UART 161 is enabled by IN10. The interrupt flag sets bit A7 while bits A4-A6 have values that enable decoder 146 to derive signal OUT60, i.e., the OUT60 signal is enabled if the interrupt bit flag is set while bits A4-A6 have one set of values during the 1 .mu.s cycle time. Signal OUT60 is coupled to a reset input of D flip-flop 175, having a C input terminal responsive to a 1 kHz output of frequency divider 166, as coupled through inverter 176. Flip-flop 175 has a Q output connected to the interrupt (INT) input pin 14 of microprocessor 111. In response to the interrupt flag being set, signal OUT60 causes flip-flop 175 to interrupt the operation of microprocessor 111 by supplying an enabling signal to terminal 114 of the microprocessor, whereby the microprocessor normal operation is interrupted and an interrupt subroutine, which usually takes about 150 microseconds, is executed. The executed interrupt depends on the nature of the signal from keyboard 23 or unit 14 that caused the interrupt. The leading edge of a 1 kHz output of frequency divider 166, as coupled through inverter 176, causes flip-flop 175 to be set so that the interrupt input to pin 14 of microprocessor 111 is removed and the microprocessor again is operated from the same point as it had when the interrupt occurred.

In summary, control signal: OUT00 indicates the data is to be loaded into UART 161; OUT10 indicates that the UART is cleared; OUT20 indicates that display segments A-H are to be latched; OUT30 indicates that display segments I-P are to be latched; OUT40 indicates that the displayed character position is to be derived; OUT50 indicates that a clear keyboard flat has been set; OUT60 indicates clear interrupt flag from the 1 kHz cycle; OUT70 activates the alarm. IN00 enables readout of UART 161 to data bus 100, IN10 enables the UART status word, IN20 resets flip flop 646, IN30 enables buffer 644 and IN40 enables buffer 645.

Reference is now made to FIG. 4 of the drawing wherein there is illustrated a circuit diagram of the electronic equipment included at unit 14 of room K. Data processor 101 includes microprocessor 181, oscillator and frequency divider 182, and controller chip 183, which are preferably interconnected and operated in the same manner as the corresponding elements of data processor 24. Thereby microprocessor 181 is clocked at a two megahertz rate by oscillator and frequency divider 182 to derive 12 binary bits A0-A11 and is selectively connected to data bits D0-D7 of data bus 184 via controller chip 183. Address bits A0-A9 are coupled in parallel to input pins of PROMS 185 and 186 which store a program to activate unit 14. Address bits A0-A7 of microprocessor 187 are also fed in parallel to address input pins of a static RAM 187. In the preferred embodiment, RAM 187 in a Fairchild 3539 chip and PROMS 185 and 186 are of the same type as PROMS 117 and 118 of data processor 24.

Each of the PROMS 185 and 186, as well as RAM 187, includes eight output bits which are selectively coupled to data bits D0-D7 of data bus 184. Selective activation of PROMS 185, 186 and RAM 187 is in response to address bits A10 and A11 of microprocessor 181, as wall as MEMR, MEMW and I-OR signals derived by a controller chip 183 on leads 24-26. One of PROMS 185 and 186 is selectively enabled in response to chip select (CS) signals respectively supplied by decoder 188 to pins 20 thereof. RAM 187 is selectively enabled in response to chip select signals CS1 and CS2 being respectively applied to terminals 10 and 14 thereof. Data are read out of RAM 187 in response to an enable signal being applied to R/W pin 12 of RAM 187.

Selection of PROMS 185 and 186 is performed with PROM chip select decoder 188 while RAM 187 is enabled to its various states in response to signals from logic networks 189 and 190 and in response to signals derived directly from address bit A11 of microprocessor 181 and the MEMW signal derived at pin 26 of controller chip 183. PROM chip select decoder 188 selects one of PROMS 185 and 186 in response to address bits A10 and A11, as well as signal MEMR. PROMS 185 and 186 can be read out only in response to signal MEMR being enabled, while PROM read out selection is determined by whether address bit A10 or address bit A11 is enabled. To activate RAM 187, either into the read or write state, the MEMR and MEMW output signals of controller chip 183 are combined in logic network 190, including NOR gate 191, having an output which is fed through inverter 192 to CS1 input terminal 10 of the RAM. Thereafter, address bit A11 is applied by microprocessor 181 to CS2 input terminal 14 of RAM 187. To write information into RAM 187 in response to data bits D0-D7 on line 184, the MEMW signal on output pin 26 of controller 183 is enabled, after the CS1 and CS2 terminals have responded to enabling signals. To read signals from RAM 187 to data bits D0-D7 of data line 184, the MEMR signal at pin 24 of chip 183 is enabled simultaneously with enabling of address bit A11, as detected in logic network 189 that includes inverter 193 and NAND gate 194 that derives pin 13 of RAM 187.

Certain functions associated with reading information into and writing information out of RAM 187 are performed by two input to four output decoders 195 and 196, as well as by logic network 197, in response to the status of address bits A0-A3, as well as in response to signals I/OR and I/OW, as derived from pins 25 and 26 of controller chip 183. Decoders 195 and 196 are enabled in response to enabling signals being applied to G input pins 1 and 15, respectively, thereof. Pin 15 of decoder 196 is directly responsive to the I/OW output signal of controller 183, on pin 27, while pin 1 of decoder 195 is responsive to the I/OR output signal at pin 25 of controller 183 and address bit A2, as derived from microprocessor 181; the I/OR signal and bit A2 are combined in NAND gate 198, having an output that drives the G input pin 1 of decoder 195. Both of decoders 195 and 196 include A and B input pins, respectively driven in parallel by bits A0 and A1 of microprocessor 181. Each of decoders 195 and 196 responds to a two-bit parallel input signal to activate one of four output pins having a decoded value of 0-3. The 0-3 output signals of decoder 195, at decoder output pins 4-7, are respectively referred to as signals IN00-IN03, while the 0-3 output signals of decoder 196, at the decoder output pins 2-9 are respectively referred to as signals OUT00-OUT03. Logic network 196 responds to address bit A2 and the I/OR signal at pin 25 of controller 183 to derive signal IN04.

Data bits D0-D7 on data bus 184 are coupled to transmit pins (TR1-TR8) and to receive pins (RR1-RR8) 5-12 of universal asnynchronous receiver transmitter (UART) 201, which is identical to UART 161 at data processor 24 of console 11. Signals coupled into pins TR1-TR8 by data bus 184 are converted into an 8-bit serial signal SO is coupled from pin 25 of the UART to line driver 202, having output pins that are connected to connector plug 17. Serial binary signals received by connector 17 from console 11 are supplied to input pins of line receiver 203, and thence as SI input signals to pin 20 of UART 201. UART 201 is activated to be responsive to the 8-bit serial bytes at pin 21 to derive an 8-bit parallel output signal that is coupled by pins 5-12 to data bus 184, as data bits D0-D7.

The signals on data bus 184 are coupled to (SO) pin 25 of UART 201 and the signal at SI pin 20 of the UART is connected to data bus 184 in a two-step operation. Signals at pins 26-33 are loaded into a buffer register of UART 201 in response to an enable signal being derived at terminal OUT00 by decoder 196, as coupled to DS input pin 23 of the UART. The parallel signals loaded into the buffer and read out in response to clock signals supplied to TRC and RRC pins 17 and 40 of UART 201, at the 5 kHz rate, while an enable signal is being derived by decoder 196 on lead OUT01, and supplied to XR pin 21 of the UART via inverter 204. Data are used into a buffer of UART 201 from SI pin 20 at the 5 kHz rate in response to decoder 195 deriving an IN00 enable signal that is coupled in parallel to RDE and RDA input pins 4 and 18 of UART 201. After the 8 binary bits in the signal at SI pins of UART 201 have been loaded into the UART, the eight bits are read out to data bus 104 in response to signal IN00 enabling the UART via RDA and RDE pins 18 and 4.

Five kHz clock signals are supplied to TRC and RRC pins 17 and 40 of UART 201 via a cascaded arrangement of D flip-flop 205, frequency divider 206, and frequency divider 207. Flip-flop 205 in responsive to clock signals derived from oscillator and frequency divider 182, in the same manner as D flip-flop 167 in responsive to the output of oscillator and frequency divider 112.

UART 201, like UART 161, includes status bits DA, TBMT, PE, and FE, respectively derived on pins 19, 22, 13 and 14, once each 1 .mu.s operating cycle of the unit microprocessor in response to signal IN01 being derived from decoder 195. The FE, PE, TBMT and DA signals derived from UART 201 are respectively applied to data bit lines D0, D1, D6 and D7 of data bus 184. Signal D4, when enabled, is coupled to microprocessor 181 via controller 183, to active the microprocessor to indicate that data to be processed is available at the input of the UART. Microprocessor 181 responds to the DA signal and its next address to activate decoder 195 to enable signal IN00 which is coupled to pins 4 and 18 of UART 201, causing 8 parallel bits to be read out from the UART to data line 184. Enabling of signal TBMT indicates that the transmit buffer of UART 201 is empty and that a new byte can be loaded into the UART for coupling to SO pin 25 and thence to console 11. The enabled TBMT signal is coupled through controller chip 183 to microprocessor 181, to cause the next address output of the microprocessor to activate decoder 196 so that signal OUT00 is derived by the decoder. Signal OUT00 is coupled to DS pin 23 of UART 201, enabling the UART to be laoded with a parallel 8 bit byte from data bus 184. An enabled PE signal on pin 13 indicates that there is a parity error in the signal received by UART 201, which parity error is fed into microprocessor 181 via data bit D1 and controller 183. The parity error signal activates microprocessor 181 to prevent loading of RAM 187 with the byte containing the parity error. An enabled signal FE at pin 14 is coupled via data bit D0 through controller 183 to microprocessor 181 to indicate that a stop bit in the frame is in the incorrect place, and advises the microprocessor to ignore the byte including the framing error.

Data bus 184 is responsive to signals generated by unit 14 in response to activation of push buttons 61-65, resistance sensor 71-75, unit select source 103, calibrate switch 105, enable switch 106, and tamper switch 107.

The selective closure of switches 61-65 is coupled, once each 1 .mu.s operating cycle, to data bits D0-D4 via buffer 208 that is activated in response to an enable signal being coupled to IN04 lead by logic circuit 197. Buffer 208 includes five input pins 4, 8, 11, 15 and 13, respectively connected to contacts 61-65, and five output pins 16, 12, 9, 5 and 7 respectively coupled to data lines D0-D4 of data bus 184. In response to the leading edge of signal IN04, the input pin of buffer 208 are responsive to binary signals indicating closure of contacts 61-65. In response to the trailing edge of signal IN04, the signal stored in buffer 208 is read out from pins 16, 12, 9, 5 and 7 to data lines D0-D4 of data bus 184.

Buffer 209 has eight input pins responsive to an 8-bit binary signal indicative of the number of the unit installed in room K. The 8-bit signal is derived from a source 103 having eight individual switches responsive to three decimal keys for the 128 different units and a further key which sets the most significant bit to a binary one if multiple units are installed at the same location. The 8-bit binary signal coupled to the eight input pins of buffer 209 are fed into the buffer in response to the leading edge of signal IN03 derived from decoder 195 during a particular address of microprocessor 181. The trailing edge of signal IN03 activates buffer 209 to derive the 8-bit parallel signal as an output to bits D0-D7 of data bus 184.

In response to an empty bottle condition being sensed by liquid detectors 71-75, enable signals are supplied to data lines D3-D7 of data bus 184. To this end, liquid detectors 71-75 are respectively connected to input pins of resistance detector circuits 211-215, each of which is enabled in response to the resistance supplied to its input pin being above a predetermined value, associated with no liquid being in contact with electrodes of the particular liquid detector. Enabling signals derived from resistance detectors 211-215 are applied to input pins of buffer 216, having three additional input pins responsive to the condition of switches 105-107. In response to any one of switches 105-107 being closed, an enabling signal is supplied to the input pins of buffer 216 which are connected to these switches. Buffer 216 includes an 8-bit output, whereby enabling signals resulting from the outputs of resistance detectors 211-215 are respectively applied to data bits D0-D4, while the signals resulting from activation of switches 105, 107 and 106 are respectively applied to data bits D5, D6 and D7 of data bus 184. Signals are supplied from input pins of buffer 216 to storage circuits of buffer 216 in response to the leading edge of signal IN02 and are read out of the buffer to data bus 184 in response to the trailing edge of signal IN02.

Signals from data bus 184 are also used to activate: (1) solenoid valves 61-65, (2) empty bottle indicating LEDs 91-95, (3) legal hours LED 110, and (4) last call LED 111.

Valves 61-65 are respectively activated in response to data bits D0-D4 being enabled during the interval while signal OUT03 is derived by decoder 196. Data bits D0-D4 are respectively applied to channels 221-225, each of which is identical, whereby a description of channel 221 suffices for the remaining channels. Channel 221 includes NAND gate 226 responsive to data bit D0 and the signal on lead OUT03, as coupled through inverter 227. The signal coupled through inverter 227 is applied in parallel to all of channels 221-225. NAND gate 226 has an output that is applied to a timer 228 including external circuitry which controls the length of time that a binary one signal is derived from the timer, thereby to vary the length of time valve 61 is opened, and to vary the number of ounces in each drink dispensed by reservoir 51 to a glass beneath the reservoir. Timer 228 includes an output pin that activates LED driver 229, having an output that is connected to light emitting diode 230 of electro-optical isolating element 231. Element 231 includes a light responsive silicon controlled rectifier 233 having an anode and cathode which are connected across diagonal pins of bridge 234. Bridge 234 includes another pair of diagonal pins which selectively connect pins 235 of a 120 volt AC source in series with coil 236 that actuates valve 61 in response to bridge 234 being energized into a conducting state by SCR 233 being responsive to light from LED 230.

During the interval while signal OUT01 is derived by decoder 196, LEDs 91-95, 110 and 111 can be selectively activated into a latched-on condition. To this end, signal OUT01 is applied to a latch input of latch chip 237, having eight input signal pins responsive to data bits D0-D7. Latch chip 237, when activated by signal OUT02, supplies an enabling signal to an output pin corresponding with an input pin having an enabling pulse input supplied to it. The enabling level derived from the eight output pins of latch chip 237 are supplied to LED drivers 238, one of which is provided for each of LEDs 91-95, 110 and 111. The signals supplied to latch 237 cause LEDs 91-95 to be respectively activated in response to enabling signals being derived from resistance detectors 211-215. LED 110 is normally maintained in an energized condition, during legal hours, when alcoholic beverages can be dispensed from reservoirs 51-55, while LED 111 is activated for an interval immediately preceding the termination of legal hours, which interval is typically on the order of 15 minutes.

The timing and arrangement of microprocessor 201 are such that enabling signals derived from buffer 216 are not applied directly to LEDs 91-95, but are coupled from the buffer to RAM 187 and thence are coupled back to the LEDs. Similarly, coils 236 of channels 221-225 are not directly responsive to energization of push buttons 61-65, but are activated in response to signals written into RAM 187, and thence read out of the RAM to channels 221-225.

To summarize, control signal: IN00 indicates that data is to be supplied to UART 201; IN01 indicates that the status of UART 201 is to be determined; IN02 enables the empty status of dispensing reservoirs 61-65 is to be determined; IN-03 enables the addressed unit number to be determined; IN04 enables a determination to be made that a dispensing action has been executed at the addressed unit; OUT00 indicates that the UART is ready to transmit; OUT01 indicates that the UART is cleared; OUT02 enables the indicator lights to be activated; OUT03 indicates that a dispensing action has occurred.

Before considering the detailed operations performed at console 11 and unit 14, consideration will be given to the format of data bytes transmitted in both directions between the console and stations. The signals transmitted from console 11 to units 14 are referred to as polls, each of which include five sequential bytes, each including eight parallel bits. Bytes 1 and 2 of each poll are identical, and are utilized for synchronizing purposes. Byte 3 of each poll is an address byte for the unit 14 being polled by console 11, and thus corresponds with the 8-bit binary signal supplied by unit select source 103 to each unit. The fourth byte in each poll is one of seven different commands which are transmitted from each console to an addressed station. The fifth byte in each poll is basically a parity byte, formed by an exclusive OR combination of all the bytes in the poll, whereby;

Because synchronizing bytes 1 and 2 are identical in each poll, preferably having the value 00010110, the value of byte 5, bit i can be determined exclusively from:

The eight bits in command byte 4 have values indicative of the functions listed in TABLE II.

All of units 14 are simultaneously connected to be responsive to the poll transmitted from console 11. However, only the addressed unit 14 responds to a poll, and such a response occurs only if: the poll contains a valid command byte 4 following address byte 3, and LRC or parity byte 5 is correct. The addressed unit responds to the poll approximately 10 milliseconds after receipt of byte 5 of the poll transmitted from console 11 to the units. However, no response is derived from the addressed unit if command byte 4 indicates that a line test is to be conducted or if data are to be transmitted from the console to the addressed unit.

An addressed unit 14, when responding to a poll signal from console 11, except for the test line and send data polls, initially acknowledges receipt of the poll transmitted from the console by sending back to the console all of the five bytes of the original poll signal. The addressed unit 14 then transmits ten bytes, each including eight bits, back to console 11. Bytes 1 and 2 are identical synch bytes, each having a format of 0010111. Synch bytes 1 and 2 are followed by addresss byte 3, which indicates the address of the polled unit 14. Byte 4 is a status byte, having eight bits respectively representing eight different monitored parameters at the addressed station. The five least significant bits of status byte 4 respectively indicate whether or not reservoirs 51-55 are empty or not empty. The next three most significant bits of status byte 4 indicate the condition of switches 105-107, whereby the sixth least significant bit indicates whether or not calibrate switch 105 is opened or closed, the seventh least significant bit indicates whether enable switch 106 is opened or closed, while the most significant bit of byte 4 indicates whether tamper switch 107 is open or closed. Bytes 5-9 respectively indicate, in binary code, the number of times beverages were dispensed from each of reservoirs 61-65. Byte 10 is a parity byte, whereby each bit of byte 10 is formed by performing an exclusive OR function on the correspondingly numbered bits of the previous nine bytes forming the data poll signal transmitted from addressed unit 14 to console 11.

In order for console 11 to test the line between it and any one of units 14, a 13-byte test signal is transmitted from the console to the addressed unit. Bytes 1 and 2 of a line test command are identical with the sync bytes normally transmitted from console 11 to units 14, while byte 3 indicates the address of the unit 14 over which the line is being tested. Byte 4 signals a line test command, as indicated by line 1 of Table II. Bytes 5-12 of the line test command are selected in accordance with statistical criteria to enable line testing to be performed. In a preferred embodiment, the sequence of bits for bytes 5-12 is indicated by:

After byte 12 has been transmitted from console 11 to the addressed station 14, a parity or LRC byte is supplied by the console to the line, with each bit of the LRC byte being formed as an exclusive OR of the correspondingly numbered bits of the other 12 bytes of the line test. The addressed station responds to the line test command by sending back an identical signal, except that the sync bytes 1 and 2 are 00010111, i.e., the same as the sync normally supplied from the addressed station to the console.

Reference is now made to FIG. 5 of the drawing wherein there is illustrated a functional flow diagram of the operations performed by the appratus of FIG. 4, at unit 14. In general, each of the program operations illustrated in FIG. 5 is performed once during each millisecond program cycle time of data processor 101. However, certain initilization functions 241 are performed only after power is initially applied to unit 14. The initialization functions involve clearing certain portions of RAM 187 wherein there are: (1) counters which store the number of drinks dispensed from each of reservoirs 61-65; (2) flags which indicate the status of: (a) calibrate, (b) enable and (c) tamper switches 105-108, (d) the active state of unit 14, and (e) resistance detectors 211-215. In addition, each of buffers 208, 209, 216 and latch 237 is cleared so binary zeros are derived from the outputs thereof.

To carry out the program at unit 14, certain one bit flags are selectively derived during 1 ms cycle time of data processor 101. These flags, stored at different predetermined bit positions in one byte of RAM 187, indicate if: (1) a message is pending for transmission from or reception at unit 14 (button pending), (2) any of buttons 61-65 is depressed (button pending), (3) unit 14 is active to be responsive to an address byte from console 11 (active), (4) unit 14 is the unit addressed by console 11 (local). The manner in which these flags are set is discussed in connection with FIG. 5.

During execution of the program for unit 14, as well as console 11, many comparison operations are performed. The comparison operations are performed in the usual manner, by supplying two bytes from a portion of memory (either one byte from a designated RAM address and one byte from a designated PROM address, or two bytes from different designed RAM addresses) to exclusive or, comparison circuitry in the arithmetic register of the microprocessor. The arithmetic register responds to its inputs to derive an enable signal that sets a flag in the RAM or directs the stack pointer register of the microprocessor to an address in the PROM of the data processor.

Certain addresses in RAM 187 can be considered as counters for indicating the number of drinks served from each of reservoirs 51-55. These counters of RAM 187 are arranged so that there are actually two redundant sets. One set of counters can be considered as active and directly responsive to signals indicative of the total number of dispensing operations performed for each of reservoirs 61-65. The other set of counters is responsive to output signals from the first set of counters. Counts stored in the second set of counters are added to the count on the first set when the console commands a counter interrogation. The first set of counters is cleared when each of the counters dumps its counters into the second set of counters during interrogation. The second set of counters is cleared only when console 11 acknowledges receipt of the number of drinks stored in each of the counters. This feature assures that the second set of counters stores the correct number of drinks dispensed from each of the reservoirs, regardless of whether a polling operation is performed on unit 14 by console 11 while one of buttons 51-55 is or is not activated.

The first operation 242, except when a start sequence and initialization function 241 are required, involves determining the message pending flag. If operation 242 indicates that a message is not pending, the program stored in PROMS 185 and 186 is advanced to operation 243.

During operation 243, a determination is made by examining the button pending flag to determine whether the status of one of buttons 61-65 is pending, i.e., was one of buttons 61-65 pressed since operation 243 was last performed or if a button is now being pressed. If the button pending flag is not set, operations 244-248 are executed in sequence. Operations 244-248 respectively involve interrogating the addresses of RAM 256 where the status of buttons 61-65 is stored; the status of buttons 61-65 is fed to the RAM under the control of signal IN04. If operations 244-248 indicate that none of buttons 61-65 is set, the program executes a DO loop and operation 243 is again performed to determine if a button is pending.

In response to one of buttons 61-65 being set, RAM 187 supplies an enable signal to data bits DO-D4 during operations 244-248, respectively, whereby coil 236 of the appropriate channel 221-225 is activated during one of operations 251-254, whichever one of these operations is reached during the operating cycle being considered. The sequential performance of operations 244-248, with a possible program branch after each prevents activation of more than one of coils 236 at a time. After one of operations 251-254 has been executed, a count of one is added to one of five counters in RAM 187 that stores the number of dispensing operations associated with reservoirs 51-55 respectively. After any one of operations 255-259 has been executed, the button pending flag is set during operation 261. The flag set during operation 261 is examined during interrogation operation 243.

If operation 243 indicates that the button pending flag is set, interrogation operation 262 is executed. Operation 262 involves determining if the pending button was released within the last 1 ms program cycle time of data processor 101. The operation is performed by feeding the set pending flag (set during operation 261) and the pending button flag status of the immediately preceding cycle from predetermined addresses in RAM 187 to exclusive or (comparison) circuitry in the arithmetic unit of microprocessor 181. In response to operation 262 indicating that the button has been released, the button pending flag is reset during operation 263 so that when operation 243 is next performed there is a no answer. If button released interrogation operation 262 indicates that the button was not released, the program returns to interrogation operation 242, enabling a determination to be made as to whether a message is or is not pending.

In response to interrogation operation 242 indicating that a message is pending, operation 264 is executed. During operation 264 message bytes received by unit 14 from console 11 are read. The first step involved in reading a message byte from console 11 into unit 14 involves determining if the active flag has been set at the unit, interrogation 265. In response to interrogation operation 265 indicating that the active flag has not been set at unit 14, operation 266 determines if the 8-bit byte supplied by UART201 to data line 184 is a synchronization byte. In response to operation 266 indicating that the eight bits received by UART201 do not form a synchronization byte, the program is returned to message pending operation 242. If, however, it is determined that a sync byte is applied to UART201, the active flag of unit 14 is set during operation 267. Following operation 267, a counter in RAM 187, that indicates the number of received bytes, is incremented from zero to a count of 1, during operation 268. Hence, the count of the counter is one less than the number of received bytes. After operation 268, microprocessor 181 activates PROMS 181 and 186 so that the program returns to operation 242.

If operation 265 reveals that the active flag was set during operation 267, the program is advanced to interrogation operation 269, during which the count of the byte counter is examined to determine if it is a one or some other number. If operation 269 determines that the byte count is one, indicating the second received byte, the program proceeds to interrogation operation 270, at which time a determination is made as to whether the second received byte is, in fact, a sync byte. It is to be recalled that the second byte is normally a sync byte, but in certain instances, there may be errors on the line or the byte counter may erroneously be set to a count of one, whereby operation 270 results in a no. A no result from operation 270 causes the active flag for station 14 to be reset during operation 271. After operation 271, the program returns to operation 242.

If interrogation operation 270 determines that the second byte was, in fact, a sync byte, the program is advanced so the byte counter is incremented by a count of 1, during operation 272. After the byte counter has been incremented by a count of one by operation 272, the program returns to message pending interrogation operation 242.

If interrogation operation 269 indicates that the byte counter count is not one, the program is advanced to interrogation operation 273, during which the byte counter is examined to determine whether the count stored therein is two, as occurs in response to the third (address) byte being transmitted from console 11. In response to the byte counter storing a value of two, the program is advanced to interrogation operation 274 during which a determination is made as to whether the address byte now being received at unit 14 is the same as the address of the local or particular unit 14. Hence, all of the foregoing operations are carried out by each of stations 214 in response to bytes 0, 1 and 2 being transmitted from console 11 to all of the units.

In response to operation 274 indicating that the address at the particular unit 14 differs from the address tranmsitted from console 11, the active flag at the particular unit is reset during operation 271 so the particular unit is decoupled during the remainder of the poll being transmitted from console 11. If, however, the address of unit 14 is the same as the address transmitted from console 11 during the third byte, the local flag at the particular station 14 is set during operation 275. During operation 275 the bits in byte 2 are supplied to the exclusive or circuitry in the arithmetic register of microprocessor 181, to initiate accumulation of the LRC signal, which is utilized for parity check purposes.

If interrogation operation 273 indicates that the byte count is not two, the program is advanced to operation 276, during which a determination is made as to whether the local flag is set; the local flag is set only if the first, second and third bytes have been correctly received and the address of the particular station coincides with the address transmitted from the console 11. In response to operation 276 indicating that the local flag is not set, the program advances to interrogation operation 277, during which the byte counter is examined to determine if it has a count of 5, which indicates that the poll from console 11 to the addressed unit 14 has been completed. In response to the byte counter having a count of 5, the program advances to operation 271, during which the active and local flags are reset.

In response to interrogation operation 277 indicating that the byte count is not 5, the program advances to operation 277, during which the byte counter is incremented by a count of 1. Operation 272 is thereby performed in all of units 14, except the addressed unit which responds to the fourth (command) byte and the fifth (LRC) byte in the poll from console 11 to units 14.

In response to interrogation operation 276 indicating that the local flat is set, operation 278 is performed. During operation 278, the received third, fourth or fifth byte from console 11 is fed to a designated address of RAM 187. In addition, the received byte is applied to the exclusive or circuitry in microprocessor 101, and accumulated in a register of the microprocessor arithmetic unit. Of course, operation 278 is performed only at the station 14 having an address that is the same as the address transmitted from console 11.

After operation 278 has been performed, the program is advanced to interrogation operation 279, during which the byte counter is examined to determine if it has a count of five, i.e., all of the five bits of the poll from console 11 have been received. Operation 279 is also reached after operation 275 has been performed. If operation 279 indicates that the byte count is not 5, the program is advanced to operation 272, during which the byte counter is incremented by a count of 1.

If, however, operation 279 indicates that the byte count is 5, operations are performed that are related to determining if the poll signal transmitted to the particular station 14 is correct and certain commands associated with byte 3 are possibly executed. If operation 279 determines that the byte count equals 5, operation 281 is performed. During operation 281, all of the accumulated bits which have been exclusive ored together are examined to determine if each of them has a binary zero value. If each of the accumulated bits does not have a binary zero value, in indication is provided that there has been an incorrect transmission to or reception at unit 14, and the program proceeds to operation 271, whereby the active and local flags at the particular unit 14 are reset.

If, however, operation 281 indicates that the accumulated, exclusive ored bits all have a binary zero value, a correct transmission between console 11 and the addressed unit 14 is assumed, whereby program is advanced to operation 282. During operation 282, a stored indication (01000001) of command byte 3 is compared with the received byte 3 to determine if the addressed unit 14 is to send data back to console 11. If operation 282 indicates that the particular station 14 has been commanded to send data back to console 11, a data message is sent back to the console during operation 283. The data message has the format described supra, including ten bytes, numbered 0-9; bytes 0 and 1 are sync bytes, byte 2 is the address of the addressed unit, byte 3 is a status byte for the addressed unit, bytes 4-8 indicate the number of servings respectively associated with reservoirs 51-55, and byte 9 is the LRC or parity byte. After the data message has been sent from UART 201 at the addressed unit 14 to console 11, the program at unit 14 is advanced to operation 271, during which the active and local flags are reset.

If operation 282 indicates that the command byte transmitted from console 11 to the addressed unit 14 was other than a command to send data back to the console, the program is activated to operation 284. In operation 284, the original five byte poll is transmitted from the addressed unit 14 back to console 11 as an acknowledge message. As previously indicated, however, the sync bytes of the acknowledge messages that are transmitted from the addressed unit 14 back to console 11 are modified to be 00010111.

After the acknowledge signal has been transmitted from unit 14, the program is advanced to operation 285, during which the function commanded during the fourth byte of the poll transmitted from the console 11 to the addressed unit is executed. In other words, during operation 285, one of the following functions is performed at the addressed unit 14: (1) the total of the number of dispensed drinks stored in RAM 256 is cleared or erased (2) the operation of the addressed unit 14 is enabled, (3) the operation of the addressed unit 14 is disabled, (4) last call indicating LED 111 is activated, and (5) a bit in RAM 187 which indicates that tamper switch 107 has been activated, is reset.

After operation 285 has been performed, the program is advanced to operation 271, during which the active and local flags are reset.

A complete operating cycle of station 14 has thus been described for all possible situations at the station, whether it be an addressed or unaddressed station. A detailed program listing of the program stored in PROMS 185 and 186, in the INTEL 1080A assemblers language is enclosed as a part of Appendix I.

Consideration is now given to the program of data processor 24 at console 11, by referring to the flow diagram of FIG. 6.

Before describing the detailed flow diagram of data processor 24, consideration will be given to certain registers of microprocessor 111 and the function of certain addresses in RAMs 121-124 and PROMS 117, 118. Certain of the registers in microprocessor 111 indicate the status of program pointers. In addition, microprocessor 111 includes a millisecond tikker register that is responsive to two MHz clock pulses derived from oscillator and frequency divider 112, and is utilized in connection with interrupt operations. When the tikker register indicates that one millisecond has elapsed, the program of data processor 111 is restarted, to establish a one millisecond program cycle including many of the 1 microsecond microprocessor cycles. The arithmetic register of microprocessor 111 includes exclusive or, comparison circuitry that determines the result of many interrogation operations in the same manner as discussed supra for microprocessor 161. Certain addresses in RAMs 121-124 store information that has been supplied to data processor 124 by keyboard 22; other addresses in the RAMs store information or data from an addressed unit 14; other addresses are utilized as station tables to keep track of: (1) the units 14 connected in the system, (2) the rates associated with the dispensing operations at the units, and (3) the status of each unit; other addresses store the sum of all drinks that have been served at all of units 14 since power has been switched on the system; other addresses store information regarding time in milliseconds, quarter seconds, minutes, hours, days of the week, days of the month, and month; other addresses are utilized in connection with keyboard queuing to keep track of the number of keys that have been activated at keyboard 23, but which have not been processed through the display, the size of a mask, the next memory cell where characters to be displayed can be stored in the queue, the oldest cell in the keyboard queue, and cells for storing the unprocessed keyboard data; other addresses store the beginning and end of legal hours (in minutes and hours) for all seven days of the week. In addition, RAMs 121-124 store signals associated with communicating between console 11 and units 14; these signals are: a state flag, a transmit count, an address for the unit 14 in communication with console 11, a command byte, a parity byte, and a count of the byte numbers in the transmission between console 11 and unit 14. RAMs 121-124 also store other signals relating to alphanumeric displays on dynamic, LED display 23; these signals indicate whether there is a display being generated, and the current character being displayed at each of the 16 display positions. PROMs 117, 118 store the firmware program, as well as signals to activate display 23 in response to certain direct keyboard entries, as well as in response to keyboard entries that are determined by the program to be incorrect. The displayed characters are stored as 16 bit entries, formed as two 8-bit bytes that are sequentially fed to data bus 100.

The main program executed by data processor 24 in response to a program sequence read out of PROM 118 in response to pointers from microprocessor 111 is broadly indicated in the flow diagram of FIG. 6A. After the system has been turned on, operation 301, addresses in RAMs 121-124 for queing keyboard 22 are cleared during operation 302. Immediately thereafter, the program is advanced to operation 303 which involves clearing the registers in UART161 and buffers 644 and 645. Immediately thereafter, the one millisecond tikker is cleared during operation 304.

After all clearing operations 302, 303 and 304 have been performed, the interrupt service is enabled during operation 305, as described in detail in connection with FIG. 6B. Then buffer 163 and the communication buffers in UART 161 are cleared during operation 306.

A test is then made, during operation 307, to determine if there has been a system shut down. Such a test is made by determining if the voltage at lead 135, as supplied to address decoder 125, is above or below a threshold value associated with a binary one value. If the voltage is below the threshold, a power failure is presumed and a test is made to determine whether the contents of RAMs 121-124 can be considered as being reliable. The test involves performing an exclusive or function of the signals stored in RAMs 121-124 which is indicative of the sum of all dispensed drinks with a multi-bit parity byte that is accumulated as the sum of the drinks is stored. If this exclusive or function results in a sum of zero, it is assumed that the power loss caused a change in the memory, whereby it is necessary to clear the scratch pad and station table addresses in RAMs 121-124; such clearing is performed during operation 308. If, however, operation 307 indicates that the power shutdown did not alter the signals stored in RAMs 121-124, the program proceeds to operation 309, during which clock pulses are supplied once every millisecond to designated addresses in RAMs 121-124, which addresses are considered to form a soft clock. The soft clock stores time in milliseconds, quarterseconds, seconds, minutes and hours and initially has all zeroes in it; and is thereafter incremented as described in connection with FIG. 6B.

After the soft clock has been started, polling of units 14 is initiated during operation 310. Then, timing functions, as illustrated by FIG. 6D, are performed during operation 311. The program is then advanced to operation 316, during which the stored keyboard queue, indicated by FIG. 6E, is unloaded. Then, during interrogation operation 317, a determination is made as to whether the keyboard queue is empty. If the keyboard queue is not empty, the keyboard instructions in the keyboard queue are performed during operation 318, and, as illustrated in FIG. 6E. During operation 318, the various command functions which have been entered into the keyboard are performed in accordance with the flow diagrams on FIGS. 6F-6N. If, however, operation 317 indicates that the keyboard queue is empty, the station polling operations indicated by FIG. 6P are performed during operation 319. Upon completion of operation 319, the main program is recycled back to operation 311. Thus, during the normal operation of data processor 24, (when there is no interrupt) operations 311, 316, 317, possibly operation 318, and operation 319, are sequentially performed, with return from operation 319 to operation 311, without performance of operations 302-310. Interrupt operation 305, however, is performed on demand in response to activation of keys from keyboard 22, in response to the elapse of certain time intervals, and when signals are being transmitted between console 11 and unit 14 in both directions.

The interrupt operations are illustrated in detail in the flow diagram of FIG. 6B. When the interrupt service is initially entered, operation 321 is performed; operation 321 involves saving the state of the program of data processor 24 when the interrupt instruction occurred. This operation involves shifting the signals stored in the various registers of microprocessor 111 into designated memory locations of RAMs 121-124. In particular, the signals stored in each of the registers of microprocessor 111 are fed to designated locations in RAMs 121-124. These registers are: (1) the program status word register, (2) the stack pointer register, (3) the 16-bits stored in the microprocessor BC registers, (4) the 16-bits stored in the microprocessor DE registers; and (5) the 16-bits stored in the microprocessor HL registers. Then the 1 millisecond tikker register in microprocessor 111 is cleared, during operation 322.

If the interrupt is to service the time of the day counter or clock, which occurs once every millisecond, such servicing is performed during operation 323. During operation 323, five bytes of RAMs 121-124 are selectively activated. The five bytes indicate milliseconds, between 0 and 249, quarter seconds between 0 and 3, seconds between 0 and 59, minutes between 9 and 59, and hours within the day, between 0 and 23. The millisecond byte is incremented once every millisecond. In response to the millisecond counter in RAMs 121-124 exceeding a count of 249, the quarter second counter in RAMs 121-124 is incremented by a count of one. Similarly, the second counter in RAMs 121-124 is activated in response to a count of three being exceeded by the quarter second counter, while the minute and hour counters are activated in response to the second and minute counters respectively exceeding counts of 59.

The quarter second, second, minute and hour counters are advanced in response to comparison operations performed in microprocessor 111. To increment the quarter second counter, a signal indicative of 249 milliseconds is supplied from a designated address in PROM 118 to one input of the exclusive OR, comparator circuit of microprocessor 111 immediately before the millisecond counter is incremented. After the millisecond counter has been incremented, the millisecond counter address in RAMs 121-124 is read out to the other input of microprocessor comparator. If the comparison operation indicates that the maximum 249 count of the millisecond counter has been reached, an increment pulse is supplied to the quarter second counter in RAMs 121-124. Similarly, the second, minute and hour counters in the RAMs are advanced.

After the clock counters in RAMs 121-124 have been serviced, operation 324 determines if any new keys of keyboard 22 have been struck during the one millisecond operating cycle under consideration. This determination is made by examining data bit 7 of data bus 100, which has a binary one level in response to an enable signal being supplied to lead IN20 by decoder 145. If operation 324 indicates that a new key has been struck, the new key or keys are queued during operation 325. The keyboard queue includes twelve 8-bit bytes of RAMs 121-124. The first, second, third and fourth bytes respectively indicate: (1) the number of keys that have not been processed, (2) the size of a 7-byte mask indicating the number of key signals that can be stored, (3) the memory cell number where the next character can be stored in the queue, and (4) the cell number of the oldest keyed character, i.e., the key which is next in line to be processed. The remaining 8-byte locations in the keyboard queue indicate the values of the characters that are awaiting processing. The queuing technique is a standard technique, such as described in the book "Queuing Systems," written by Leonard Kleinrock.

After operation 325 has been performed, or if there are no new keys as determined by operation 324, display 23 is refreshed during operation 326. The display refresh operation is well known to those skilled in the art and involves standard light emitting diode display multiplexing techniques. Display refreshing is performed with a modulo 16 position counter in RAMs 121-124 that controls where a particular character is to be displayed. In addition, a display table containing 16-bit entries selects the segments of display 23 which are to be illuminated in response to the code for the character. This table is stored in PROMs 117 and 118 and fed to latches 151 and 152 under the control of an enable signal on lead OUT30, as derived from decoder 146. The position counter of RAMs 121-124 supplies signals to latch decoder 153 in response to an enable signal being supplied to lead OUT40 by decoder 146.

After operation 326 has been performed, operation 327 determines whether the communication flag is set to zero. If the flag is set to zero, there is to be no communication between UART 161 and units 14 in either way; if the flag is not set to zero, there is to be communication to and/or from the UART. The communication flag is set to zero if a parity error (PE) or framing error (FE) is indicated by UART 161 in response to an enabling signal being supplied to lead IN10 by decoder 145. If the data available (DA) signal at terminal 19, or the transmit buffer of UART 161 is enabled, the communication flag is not set to zero and the communication service program 328, illustrated in detail in FIG. 6C, is executed.

After operation 328 has been performed or interrogation operation 327 indicates that the communication flag is set to zero, operation 339 is executed, during which the signals which were transferred from microprocessor 111 to RAMs 121-124 during operation 321, are transferred back to the microprocessor. After operation 329, enable interrupt operation 330 is performed in response to flip-flop 175 supplying a signal to the INT lead which is coupled to INT input terminal 14 of microprocessor 111. Microprocessor 111 and PROMs 117, 118, then continue their 1 ms operating cycle at the same place as when the interrupt occurred. The maximum time required to execute the interrupt cycle is 150 microseconds, a relatively small percentage of the one millisecond total operating cycle time of data processor 24.

Reference is now made to FIG. 6C of the drawing wherein there is illustrated a flow diagram for the operations involved in servicing the communication cycle, indicated by operation 328, FIG. 6B. Associated with the communications service procedure are addresses in RAMs 121-124 which indicate: (1) the state of the communications flag, (2) a counter for the byte number of the message being transmitted from console 11 to unit 14, (3) the address of unit 14 to which the next message is to be transmitted, (4) a byte 3 command signal for the unit, and (5) an accumulated indication of the parity or LRC bit. In addition, PROMs 117 and 118 store the synchronizating bytes which are always transmitted with a poll from console 11 to units 14. RAMs 121-124 also include storage locations to indicate the byte number of the message being received from unit 14 at console 11, the two sync bytes in the received poll, the address of the unit 14 communicating with console 11, the command to which unit 14 is responsive, nine locations for a variable length message, a cell for indicating when the message was received, and a cell for storing the parity bit transmitted from the station to console 11. Twenty-three, 8-bit bytes addresses are provided in RAMs 121-124 for the communication.

The state flag in RAMs 121-124 for the communication service includes one byte having individual bit locations that indicate: (1) the state (active or idle) of the communication flag, (2) whether the communication service is in a receive state, (3) whether the communication service is in a sync search condition (the normal, idle position of console 11), (4) whether UART 161 is ready, and (5) whether the communication service is in an idle state.

The first step, operation 332, in the service communications subroutine 328 involves determining whether the state flag is set to receive. Normally, the state flag is not set to receive, and the program is advanced to interrogation operation 333, during which the state flag is again examined to determine if it is set to a sync search condition. If no transmission or reception is occurring, the state flag has previously been set to a sync search position, and the program is advanced to interrogation operation 333, which determines whether or not UART 161 is ready, as determined, in response to the TBMT signal at terminal 22 of the UART.

If the UART 161 is ready, the program advances to operation 335, during which the character to be transmitted is read from an address in RAMs 121-124 to data bus 100 and thence to input terminals 26-33 of UART 161. Virtually simultaneously, the present time-out counter is reset to zero. After operation 335 has been performed, operation 336 determines from the state flag if synchronization has been achieved. If operation 336 indicates that synchronization has not been achieved, the program advances to operation 337 and the state flag is set to a sync search condition. Following operation 337, the number of received bytes counter in RAMs 121-124 is cleared to zero. After operation 338, the communications service subroutine is exited.

If, however, operation 336 indicates that the state flag is set to sync, the program proceeds to operation 339, during which the received byte counter is bumped, i.e., incremented, by a count of one. After incrementing operation 339 has been performed, the received byte counter in RAMs 121-124 is examined during operation 341 to determine if the counter has a count of one; a count of one indicates that the second sync byte is being processed. If operation 341 indicates that the second sync byte is not being processed, the communication subroutine is exited. If, however, operation 341 indicates that the second sync byte is being processed, the state flag is set to receive during operation 342 which is followed by an exit of the communication service subroutine.

If interrogation operation 334 indicates that UART 161 is not ready to transmit information, the program proceeds to operation 343, during which a 150 millisecond time-out counter in RAMs 12-124 is decremented by a count of one. Operation 343 is followed by operation 344, during which the time-out counter is examined to determine if it has a zero value. If the time-out counter does not have a zero value, the communications service subroutine is exited. If, however, the time-out counter count is zero, the communications service subroutine returns to operation 327, when the communication flag is again sensed to determine if it is set. If the communication flag is set, i.e., is not zero, the communications service subroutine is again performed, starting again with an examination of the state flag to determine if it is set to receive, as indicated by operation 332.

If operation 332 indicates that the state flag is set to receive, the program proceeds to operation 345, during which the DA signal on terminal 19 of UART 161 is sensed to determine if UART 161 is ready to receive a byte from data bus 100. If operation 345 indicates that UART 161 is not ready, the program advances to operation 343 whereby the time-out counter is decremented and the program then continues as described above. If, however, operation 345 indicates that UART 161 is ready, the program advances to operation 346, during which an 8-bit, received byte is read out from UART 161 terminals 3-12 through buffer 163 to data bus 100 and is appropriately stored in RAMs 121-124. As a character is being read out from UART 161 to RAMS 121-124, the time-out counter is reset to zero.

Upon the completion of operation 346, the number of received byte counter in RAMs 121-124 is incremented by a count of one during operation 347. Then, during operation 348, the count stored in the received byte counter is compared with the number of bytes in a poll from units 14 to console 11. If operation 348 indicates that further bytes are to be received during the poll, the communications subroutine is exited. If, however, operation 348 indicates that the last byte has been received, i.e., the parity of LRC byte has been received, the accumulated exclusive ORed bits of the received poll are calculated during operation 349. The accumulated exclusive ORed signals are sensed during operation 350 to determine if each of the exclusive ORed bits has a correct value. If operation 350 indicates that the exclusive ORed bits do not have a correct value, the communication flag subroutine is again re-entered, as indicated by operation 327. If, however, operation 350 indicates that the exclusive ORed bits have the correct value, the state flag is set to idle, during operation 351.

Previously, consideration has been given to the operations performed if interrogation operations 332 and 333 indicate that the state flag is in a receive condition and the state flag is in a sync search condition. If, however, operation 333 is reached while the state flag is not in a sync search condition, the program advances to operation 352, which involves determining whether UART 161 is ready. If UART 161 is not ready, the communication subroutine is immediately exited. If, however, operation 352 indicates that UART 161 is ready, there is an implication that a byte is to be transmitted from console 11 to the addressed unit 14.

The next character is transmitted during operation 353, which involves feeding a byte from addresses in RAMs 121-124 to data line 100 and UART 161 terminals 26-33. After the byte has been loaded into terminals 26-33, the byte is read out in series from UART 161 SO terminal 25 and transmitted to the addressed unit 14. After operation 353 has been performed, the transmit byte counter in RAMs 121-124 is incremented by a count of one, during operation 354. After the transmit byte counter has been incremented, the transmit byte counter is examined during operation 355 to determine if the last transmitted byte count of 4 has been reached. If the highest transmitted byte count has not been reached, the communications subroutine is exited. If, however, the last transmitted byte count has been reached, the program advances to operation 337 so that the communications service subroutine can again search for sync bytes. The transmit byte counter is then cleared, during operation 338 and the communications service subroutine is exited.

Consideration is now given to the operations involved in timers subroutine 311, as illustrated by the flow diagram of FIG. 6D. The initial operation 411 of subroutine 311 involves reading the previous second of time from a designated memory location of RAMs 121-124. During operation 412, a test is then made to determine if the previous seconds stored in RAMs 121-124 is the same as the presently read second. If the present and previous seconds are the same, the timing subroutine is immediately exited.

If, however, the previous second differs from the present second, the new second is transferred to the location in RAMs 121-124 previously occupied by the previous second, operation 413. After operation 413 has been performed, the program is advanced to operation 414, at which time a flag in the i-bit flag byte of RAMs 121-124 is interrogated to determine if an audio alarm is being sounded by speaker 27; this flag is termed system bleep. If the flag interrogated during operation 414 indicates that the system bleep is on, the program is advanced to operation 415, at which time the bleep flag is again maintained and a display recycle delay counter in RAMs 121-124 is incremented. The display recycle counter indicates a delay time, in seconds, between the last time a key of keyboard 22 was activated and the present time. If 30 seconds are counted by the recycle delay counter, it is assumed that the keyboard is unattended and the program is exited, as described infra.

After operation 415 has been performed, or if operation 414 indicates that the system bleep is not on, a determination is made during operation 416 as to whether a new minute has been reached. The new minute determination is made by examining the second counter and determining if it last had a value of 59. If interrogation operation 416 indicates that a new minute has been reached, the minute counter is incremented. Then, during operation 317, the hour counter is examined to determine if it last had a value of 59; if so, the hour counter is incremented.

If operation 417 indicates the hour counter is incremented, a midnight determination is made during operation 418 by sensing the hours clock to see if it last had a value of 23. Because operation 418 can only be reached if there is a new second, a new minute and a new hour, a prevous hour value of 23 indicates that midnight has been reached. When it is determined that midnight has been reached, the date counter of RAMs 121-124 is incremented during operation 419. It is noted that there is no incrementing between months; instead, the operator is required, at the beginning of each month, to reset the first of the month via a keyboard entry, including pressing date key 18. After operation 419, or if either of operations 417 or 418 determines that midnight has not been reached, the program is advanced to operation 421.

During operation 421, the delay time counter in RAMs 121-124, indicative of how long before display 23 is to be recycled, is decremented. As discussed infra, in connection with FIG. 6E, the delay time counter is set to 30 each time a key of keyboard 22 is struck and indicates if keyboard 22 is being used. The delay time counter is interrogated during operation 422 to determine if it has a zero value. If the delay time counter has a zero value, the timer subroutine is exited because 30 seconds have elapsed since the last time a key was struck. If the delay time counter does not have a zero value, the program is advanced to operation 423, during which a key activity flag is reset to zero in response to the strobe signal from keyboard 22. Because 30 seconds are required to reach operation 423 after the last time a key at keyboard 22 was struck, the key activity flag remains set for 30 seconds.

After operation 423 has been performed, the program is advanced to operation 424, at which time the display recycle delay counter is reset to a count of five, commensurate with an interval of 5 seconds. After operation 424 has been performed, the program is advanced to operation 424, at which time a modulo three-message flag counter is RAMs 121-124 is decremented. The modulo three-message flag counter indicates which of three messages are to be supplied to display 23. One of the messages is an advertisement, for example, for the brand name of the present equipment, the second message indicates the time, in hours, and minutes, while the third message indicates the date during the month. In response to the message flag display counter having counts of zero, one and two, display 23 is respectively supplied with the advertisement, the time during the day, and the date; the display is performed during operation 426.

After timing subroutine 311 has been executed, the keyboard queue subroutine 316 is performed, which is followed by a determination 317 as to whether the queue is empty, which may be followed by operation 318 performance of the keyboard work; details of these operations are in the flow diagram of FIG. 6E. The first operation 431 involved in handling the keyboard is to supply all of the bits of the keyed character to a designated memory space, as described in operation 325, FIG. 6B. Then, during operation 432, a determination is made as to whether the key signal which was just entered into memory represents a numeral or a function. If the key signal represents a function, certain bits in the stored byte have predetermined values which are compared in microprocessor 111 with predetermined values for these bits, as stored in a designated location of PROMs 117 and 118.

In response to operation 432 indicating that the key represents a numerical signal, the program is advanced to operation 433, at which time the counter which stores the number of active entries in the keyboard queue is examined to determine if it has a zero count. If there are zero active entries in the keyboard queue counter, the program is advanced to operation 434, which orders display 23 to be cleared by deactivating each of latches 151, 152 and 153. If, however, operation 433 indicates that there are active entries pending in the keyboard queue counter, the program is advanced to operation 435 during which the active keyboard queue counter is again examined to determine if it has a count of 17, one more than the highest number of characters that can be displayed at one time on display 23. If operation 435 indicates that the character count is 17, the program is advanced to operation 436, during which the character counter is cleared to zero, the desired result because there has been an error in the character counter. After operation 436, the program advances to the clear image operation 434.

If the character counter count is not equal to 17, or after clear operation 434 has been performed, the character counter is incremented by a count of one during operation 437. Thereafter, the signal representing the new key is supplied from the keyboard queue, discussed in connection with FIG. 6B, into a portion of RAMs 121-124 where the next character to be supplied to display 23 is stored; this operation is indicated by rotate new key into image operation 438. After operation 438 has been completed, the delay time counter is set to a count of 30, during operation 439. The delay time counter is utilized in connection with the timer subroutine described in connection with FIG. 6D.

If, however, operation 432 indicates that the struck key is not a numeral, but a function, the program advances to operation 441 and a signal for the function key is compared with stored signals in PROMs 117, 118 for the different functions. Depending upon the particular function, one of 14 different subroutines, described in connection with FIGS. 6F-6P, is executed; (no FIG. 6O exists because of possible confusion). The functions are: (1) set time, (2) set date, (3) set legal hours, (4) set rates, (5) cancel, (6) diagnostics, (7) room total, (8) assigned unit to a room, (9) determined empties, (10) reset tamper, (11) next, (12) clear totals, (13) enable, and (14) disable.

The set time and set date function subroutines are described in connection with the flow diagrams of FIGS. 6F and 6G. After the operator activates key 34 to indicate that time is to be changed, he enters one or two digits to indicate the current hour (between 0 and 23), which is followed by activation of dot key 33 and then by two digit entries to indicate the current minute (between 0 and 59). After the hour has been entered, the operator activates date key 35, that is followed by a one digit entry to indicate the day of the week (between 1 and 7). After the day of the week has been displayed, the operator enters the day of the month as digits from 1 to 31, the month as digits 01-12, and the year of the century as digits from 00-99.

In response to the set time function key 34 being activated, data processor 24 is activated to perform the functions illustrated by the flow chart of FIG. 6F. Initially, data processor 24 determines, during operation 441, if less than 3 numerical keys have been struck within a 30 second interval of the delay time counter. If less than three numeral keys are struck, the operator entered an incorrect time of day into the keyboard, and the program is advanced to prompt operation 442, during which PROMs 117 and 118 are activated to supply display 23 with prompting characters advising the operator that he has made a mistake in entering the new time. After the prompting characters have been displayed, data change and numerical key signals are erased from RAMs 121-124 and the set time function subroutine is exited.

If, however, three or four digits were entered, the program is advanced to operation 443, during which a determination is made as to whether the number of entered hours is less than 24, i.e., the value of the digits entered prior to the dot are examined to determine if they have a value of less than 24. If the number of entered hours is less than 24, the program advances to operation 444, during which the numerical entries subsequent to the dot are examined to determine if the number of minutes is less than 60. If either of operations 443 or 444 indicates that there was an incorrect entry because the number of entered hours was greater than 23 or the number of entered minutes was greater than 59, the program is advanced to prompting operation 442 during which display 23 provides the operator with a visual message that the time was incorrectly entered.

If operation 444 indicates that there was a minute entry less than 60, the program advances to operation 445, during which the numerical minute and hour entries are converted to complementary binary code by microprocessor 111 which responds to converting signals from PROMs 117, 118. The code is supplied to decoders 151 and 152, to drive display 23. Upon completion of operation 445, the clock, minute and hour counters in RAMs 121-124 are set; the values in these memories are displayed during operation 446. After operation 446, the set time function subroutine is exited.

If set date function key 35 is activated, the subroutine indicated by the flowchart of FIG. 6G is performed. The first operation 451 in the set date subroutine involves determining whether only one digit, coded from 1 to 7 for the days Sunday through Saturday, has been entered by numerical keys 32 after date key 35 was activated. If operation 451 indicates that only one digit has been keyed, the program advances to operation 452, during which a determination is made as to whether the keyed single digit can represent a day of the week, i.e., has a value from 1 to 7. In response to operation 452 indicating that the initially keyed digit is 0, 8 or 9, the program is advanced to prompting display operation 453, during which signals are read from PROMs 117 and 118 to display 23, to inform the operator that he incorrectly entered the day of the week. The initially entered digit is then removed from RAMs 121-124 and the set date subroutine is exited. If, however, operation 452 indicates that one of the digits 1 to 7 has been entered, the entered value is translated into character representing signals for the day of the week, which signals are supplied, during operation 454, to designated addresses in RAMs 121-124. Operation 454 is followed by operation 349 during which the day of the week is displayed. After operation 349, the program is exited.

After the first digit key for the day of the week has been activated, the program advances from operation 451 to operation 455, during which a determination is made as to whether or not the operator correctly keyed 5 or 6 digits, to represent the day of the month, month, and year of the century. If the number of keyed digits has been other than 5 or 6, the operator has made a mistake, and the program advances to prompting operation 457, during which the display is activated to inform the operator that he incorrectly entered the new date; after operation 457, the set date subroutine is exited. If it has been determined that 5 or 6 digits have been correctly keyed by the operator, the program advances to operation 458, during which the entered date is entered into designated addresses of RAMs 121 and 124. After operation 458, the day of the month, month and year are fed to appropriate character locations in display 23 during operation 459. The display includes, from left to right, a three character indication of the day of the week, a two digit indication of the number of the month, a two digit indication of the day of the month, and a two digit indication of the year of the century; the numerical indications are spaced by dashes inserted by PROMs 117, 118.

To set legal hours during which beverages may be dispensed from units 14, the operator initially activates hours key 36 and then keys the day of the week as one of numeral keys 1-7. The operator then keys the legal starting time in hours (0-23) and minutes (00-59) for the day of the week. These operations are followed by the operator keying in the end of legal serving time in hours (0-23) and minutes (00-59), for the particular day of the week. These operations are performed for each of the seven days of the week, as required.

The legal hours subroutine, illustrated by the flow diagram of FIG. 6H, initially involves determining, during operation 451, whether only one digit, to represent the day of the week, has been keyed. If only one digit has been keyed, a flag is set in RAMs 121-124 and the numerical value associated with the day is stored in the RAMs, as indicated by operation 462. After operation 462 has been performed, the program is advanced to operation during which PROMs 117 and 118 feed signals to latches 151-153 to clear display 23. Then, during operation 464, the keyed day of the week is fed from the location in RAMs 121-124 to latches 151 and 152 and these characters are supplied to display 23 under the control of latched decoder 153. By the time operation 464 has been completed, numerous operating cycle times of data processor 22 have been completed, several legal hour keys have been activated, and the program has been executed several times so that it proceeds from operation 461 to operation 465.

During operation 465, a determination is made as to whether eight digits have been keyed within a 30 second time interval since the first digit was keyed for legal hours. Operation 465 involves determining whether 8 digits have been entered on keys 32 before the count in the recycle delay counter of RAMs 121-124 has returned to zero from its initially set value of 30. The recycle delay counter is decremented by a count of one each second. If the eight digit keys 32 are not activated within the 30 second interval, the legal hours subroutine is exited. If, however, eight digits were keyed within the 30 second interval, the program advances to operation 466, during which the address of RAMs 121-124 which was loaded during operation 462 is read to determine if the day for legal hours was entered. If the day was not entered, display 23 is supplied during operation 467 with prompting characters for the operator and the subroutine is exited after the legal hours entries have been removed from RAMs 121-124.

If the day is correctly entered, the program advances to operation 468, which involves determining whether or not the entered starting hour equals 99. An entered starting hour of 99 is a code indicating that the start and end of legal hours for the particular day are to be manually entered by activation of enable key 45 and an entry on keys 32 of the ending time; such manual entries are desirable for special days, e.g., election days. If the entered starting hour is 99, the program advances immediately to operation 469, during which 99 is entered into the station table addresses of RAMs 121-124 as the starting time and the keyed end time is stored in the station table. Of course, units 14 are not enabled in response to the starting hour of 99 because the hour counter never reaches such a value. Units 14 are disabled in response to the hour and minute counters reaching the end time set into the station table during operation 469.

If the starting hour is not 99, the program advances to operations 471-474 during which determinations are made as to correct entries of the legal hours, starting and ending hours and minutes. Operations 471-474 basically involve determining if the starting and ending hours are in the range from zero to 23 and if the starting minutes are in the range from zero to 59. Operations 471-474 are normally sequentially performed and involve the following interrogations: (1) are starting hours between zero and 23?; (2) are starting minutes between zero and 59?; (3) are ending hours between zero and 23?; and (4) are ending minutes between zero and 59?. If any of operations 471-474 indicates an incorrect keyboard entry, the program is advanced so prompt operations 475-478 are respectively performed to advise the operation of an incorrect keyboard entry; each of operations 475-478 is followed by erasing of the entries following activation of the day key and then exiting of the legal hours subroutine.

If all of the starting and ending entries of the legal hours subroutine are correctly made, the program proceeds from operation 474 to operation 469 during which the starting and ending hours and minutes are stored in the station table portion of RAMs 121-124. The values stored in the station table during operation 469 are compared once a minute with the values in the clock counters of RAMs 121-124 for the day of the week, hour and minute to determine if signals are to be sent from console 11 to units 14, to cause activation and deactivation of the units. In addition, the entered end of legal hours signal for each day is decremented by 15 minutes by the arithmetic unit of microprocessor 111 and the decremented value is stored in the station table. The decremented end of legal hours value is compared once a minute with the clock counters for the day of the week, hour and minute to determine if a signal is to be transmitted from console 11 to units 14 to activate last call visual indicator 111. After operation 469 has been completed, the program is advanced to operation 481, during which the keyboard counter in RAMs 121-124 is cleared. Thereafter, during operation 482, the recycle delay counter is set to 30; it is to be recalled that this counter is decremented once every second and is used to determine if eight digits have been entered within 30 seconds, as determined during operation 465. Upon completion of operation 482, the legal hour subroutine is exited.

Display of the entered legal starting and ending hours requires several one ms. program cycles and therefore is much slower than the determinations of whether the correct keys are activated, during operations 466 and 471-474. Therefore, the start and end times for legal hours are stored in the station table of RAMs 121-124, during operation 469, considerably before the day of the week is displayed during operation 464. By the time of the day of the week has been completely displayed during operation 464, the program has advanced to operation 483 during which the legal hours starting time is displayed by reading out the starting hour and minute stored in RAMs 121-124 during operation 469. After the start time has been displayed, the program advances to operation 484, during which the end time is displayed in hours and minutes. In response to activation of key 36 and the numeral keys for each day of the week and the start and end hours and minutes, display 23 is activated to display, from left to right, the day of the week as three characters, the starting time as two digit hour and two digit minute indications and the ending time as two digit hour and two digit minute indications; the starting and ending times are separated by the characters "TO", as read to the display from designated addresses of PROMs 117, 118 under the control of start time display operation 483.

Upon the completion of display and time operations 484, the program is advanced to clear keyboard count operation 485, during which the keyboard display counter is reset to zero. Then, during operation 486, the display recycle delay counter is set to 30, after which the set legal hours subroutine is exited.

The diagnostic procedure involves determining whether all character segments on display 23 are illuminated. Therefore, in response to the operator activating diagnostic key 48, addresses in PROMs 117 and 118 are read out during operation 487 to enable all segments of display 23 to be illuminated. After all of the segments have been illuminated for thirty seconds, as indicated by the display recycle delay counter, the program is advanced to clear the keyboard counter of RAMs 121-124, operation 485. Operation 485 is followed by setting the display recycle delay counter to 30, operation 486, the last operation in the diagnostic subroutine.

When the operator depresses rate key 37, the program is branched to the subroutine having the flow diagram illustrated in FIG. 6I. After activating key 37, the operator sets the rate for each of reservoirs 51-55 of all of units 14 by activating one of keys 32 for one of the numerals 1 to 5; the entered numeral key indicates the rate for the particular reservoir 51-55 that is to be entered. After the reservoir number is keyed, the price per drink for the reservoir is entered as a first digit for the dollar value, followed by activation of decimal point key 33 and then activation of two digit keys 32 for the number of cents to be charged for each dispensing action. Data processor 22 responds to these operations by storing the rate for each drink of each reservoir in the station table of RAMs 121-124 and activating display 23 so that for each reservoir there are displayed, from left to right, the characters "BOTTLE", the number of reservoir (1-5) as entered on keys 32, the rate for the reservoir, and the characters "EA". When a room occupant checks out, the operator activates room total key 41 and the occupied room number whereby the number of dispensed drinks for each bottle at the room is transmitted from unit 14 to console 11. The arithmetic unit of microprocessor 111 multiplies the stored rate for each reservoir and the number of dispensed drinks for each reservoir of the room being checked. The arithmetic unit of microprocessor 111 accumulates these products to enable display 23 to indicate the total amount the room occupant is to be charged for the dispensed drinks.

After the rate subroutine is initially entered, the first operation 491 determines if the bottle number and not the rate has been entered on keys 32. Operation 491 involves determining whether only one digit has been entered, with the assumption that if more than one digit was entered, the multiple digits are for the rate. In response to only one digit being entered, the program advances to operation 492, during which the first entered digit is stored in RAMs 121-124 as a pointer for the station table. The stored pointer is fed to display 23 to indicate the bottle number for which the rate is being set. A determination is then made, during operation 493, as to whether the first digit entered, and the selected bottle number, is in the range of 1 to 5. If operation 493 indicates that the selected bottle number was not within the range of 1 to 5, character representing signals are read, during operation 494, from PROMs 117 and 118 to display 23 to advise the operator that there was an incorrect bottle entry. If, however, the bottle number was in the range of 1 to 5, the program is stepped to operation 495, during which the old rate for the particular bottle is retrieved from RAMs 121-124 and fed to display 123.

Upon completion of operation 495, the program is advanced to operation 496, during which the keyboard entry counter of RAMs 121-124 is cleared to zero. Then, during operation 497, the character recycle delay counter is set to 30 seconds, which is followed by an exit of the set rate subroutine.

If the operator has activated more than one key during the preceding 30 second interval, the program is advanced from operation 491 to operation 498, during which a determination is made as to whether four digits were entered during the 30 second interval. If four digits have not been entered, the program proceeds to operation 492, described supra. If operation 489 indicates that four digits have been entered, the bottle number at the pointer address of RAMs 121-124 which has written into during operation 492 is compared in the arithmetic unit of microprocessor 111 with the values 1-5 to assure that a bottle entry number has been entered by the operator. If operation 499 indicates that the bottle number key was not struck, the program advances to prompt operation 501, which advises the operator to make an appropriate change in his keying procedure.

If operation 499 indicates that the bottle key is properly activated, the program advances to operation 502, at which time a determination is made as to whether the decimal point was properly inserted between the second and third digits, i.e., between the dollar digit and the most significant cents digit. The determination of operation 499 involves a comparison by microprocessor 111 of the fourth key activated after activation of rate key 23 with a signal stored in a designated address of PROMs 117, 118 for the code of dot key 33. If operation 502 indicates that dot key 33 was not correctly activated, the program advances to operation 503, during which the operator is prompted by display 23 that he incorrectly entered the rate; after operations 501 and 503, the key entries are erased and the set rate subroutine is exited. If the decimal point was properly inserted, the program proceeds from operation 502 to operations 504, 505 and 506, during which the keyed amount to the left of the decimal point is stored as the number of dollars for each dispensing operation for the particular bottle, and the value to the right of the decimal point is stored, as the number of cents for each drink. These values are stored in the station table of RAMs 121-124 at the address indicated by the bottle pointer, set during operation 492. After the dollar and cents values have been stored, they are displayed, during operation 506. After operation 506, the program is activated so that the keyboard counter is cleared and the keyboard recycle delay counter is set to 30, during operation 497.

In response to the operator activating the cancel or clear key 39, the program is advanced to operation 511, which commands display 23 to be cleared. Operation 511 is followed by operation 496, clearing of the keyboard counter, and operation 497 during which the recycle delay counter is set to 30.

To assign a particular one of units 14 to a given room, the operator activates assign key 47. He then inserts a four digit number with keys 32 to indicate the unit number, then dot or decimal point key 33 is activated; and then activates four keys for the room number. For each additional unit 14 assigned to a room with multiple units, the operator again activates assign key 47, a different entry for the unit number, and the same room number. If multiple units are assigned to a single room, the addresses of RAMs 121-124 where the room number for each unit are stored have a binary one in the most significant room number bit position. In response to the most significant bit of the room number having a binary one value, display 23 is activated to indicate multiple units in response to activation of room total key 41. Room numbers are stored in RAMs 121-124 as two, 8-bit hexi-decimal bytes; one byte indicates the floor number, while the other byte indicates the number on the floor of a particular room. To provide adequate storage space for the 8 bits of the number of floor bytes, the number of floors is limited to 79.

A flow diagram for the operations performed by data processor 24 in response to the operator activating assign key 47 and the eight numerical keys following activation of the assign key is illustrated in FIG. 6J. Initially, a determination is made, during operation of 521, as to whether eight digits were keyed in by the operator within a 30-second recycle character delay time. If eight digits were entered, the program advances to operation 522, during which a determination is made as to whether a decimal point was entered between the four digits for the unit number and the four digits for the room number. In response to operation 522 indicating that such a decimal point was entered, the program advances to operation 523, during which the entry for the unit number (the four first digits entered before the decimal point) are converted to a binary code. After conversion of the unit number to binary, the program advances to opration 524, during which a determination is made as to whether the two most significant digits (for the room floor number) after the decimal point have a value equal to or in excess of 80. If operation 524 indicates that the floor number is less than 80, the program advances to operation 525. If, however, any of operations 521, 522 or 524 indicates that eight digits were not entered, or that a decimal was not entered between the first four digits and the second four digits, or that the floor entered was equal to or less than 80, the program is advanced to operation 526, during which a message is supplied to display 23 to advise the operator to re-enter the unit and room numbers. After operation 526, the previously entered unit and room numbers are removed from RAMs 121-124 and the subroutine is exited.

During operation 525, a determination is made as to whether four zeros were entered for the room number. If four zeros were entered for the room number, the unit is no longer assigned to the particular room. If, however, the unit is being assigned to a particular room, the program advances to operation 526 upon completion of operation 525. During operation 526, the room number is loaded into the station table portion of RAMs 121-124 at a memory location that is correlated with the particular unit number. Upon completion of operation 526, the program advances to operation 527, during which the keyed room and unit numbers are displayed so that the operator can be sure that a correct assignment has been made. If, however, the unit is being removed from the room, so the operator activates the zero key four times after activation of the unit number and decimal point, the program advances to remove room operation 528. During operation 528, the station table is entered for the location of the particular unit and all zeros are inserted for the room number assignment. After operation 528, the program is advanced to operation 529, during which the unit number is displayed together with "REMOVED".

Upon completion of either operation 527 or operation 529, the program is advanced to operation 531, to clear keyboard counter operation 530, which is followed by the display recycle delay counter being set to thirty.

When it is desired to determine the total amount that has been spent for beverages at a particular room, the operator activates disable key 46 and the room number so that the mechanism in the room is deactivated and the room occupant cannot obtain additional beverages from the reservoirs. The room number is entered as a four digit number so that the first two significant digits indicate the floor and the last two digits represent the room on the floor; if the floor number is less than 10, a zero is entered as the first digit. After disable key 46 and the room number have been activated, room total key 41 and the room number are depressed.

The operations performed at console 11 in response to activation of assign key 41 and some of the operations in response to activation of disable key 47, as well as the numerical keys for the room numbers are indicated in the flow diagram of FIG. 6K. After key 41 has been activated, a determination is made during operation 534, as to whether more than four digits are entered by the operator within the thirty second recycle display time. In response to fewer than four digits being entered, the program proceeds to operation 535, during which a suitable location in RAMs 121-124 is examined to determine whether the disable key 46 was the function key activated immediately before activation of key 41. In response to the previously entered function key being disable key 46, the program advances to operation 536. If, however, either of operations 534, 535 indicates that more than four digits were entered or that the last function key was not disable key 46, display 23 is activated during operations 537 and 538 to indicate that the incorrect number of digits was entered or that disable key 46 was not correctly activated. After either of operations 537 or 538, the entries are cleared and the subroutine exited.

Operation 536 involves determining whether the digit key for the numeral nine was pressed twice immediately after the room total key 41 was activated; if 99 was keyed, a "floor=99" flag is set to enable the total number of drinks dispensed by the system to be displayed during operation 538, which is preceded by operation 537, during which the characters "system" are supplied to display 23. Operation 538 is performed by interrogating a location in RAMs 121-124 where the total number of drinks from the rooms which have been disabled by key 46 are accumulated. The grand total of drinks displayed during operation 538 indicates only the drinks which have been charged and does not indicate the drinks which are dispensed from the rooms which are presently occupied and continuing in use. The primary purpose of displaying the grand total number of drinks is for information purposes, for example, relating to determining the charge of a user of the equipment to a supplier thereof.

If the operator did not enter floor 99, the program proceeds from operation 536 to operation 539, during which a determination is made as to whether the two most significant digits entered by the operator are less than 80. If the floor number was correctly entered as being less than 80, the program advances to operation 540, during which a determination is made as to whether the operator activated the zero key four times for the room number. If operation 539 or operation 540 indicates that the operator made an incorrect keyboard entry, with a floor number greater than 79 or a room temperature of zero, the program is advanced to operations 541 or 542, respectively, during which display 23 is activated to advise the operator of the nature of his mistake. Operations 541 and 542 are followed by clearing of the keyboard entries and then exiting of the subroutine.

If, however, the room and floor numbers were correctly entered, the program is advanced to operation 543, during which the station table of RAMs 121-124 is searched to locate the room number and correlate the room number with the unit number. After the unit number has been determined, the program proceeds to operation 544 and a signal is supplied to a queue in RAMs 121-124 that controls communications with the various units 14. When a communication link is established to the unit, the unit sends data back from the room where it is installed to designated locations in RAMs 121-124. In the RAMS, the number of drinks dispensed for each of the reservoirs at the unit is stored and multiplied in the arithmetic unit of microprocessor 111 with the price set for the particular type of reservoir. The resulting product for each reservoir of the particular unit 14 is supplied to an accumulator in the arithmetic unit of microprocessor 111 to provide an indication of the total amount of money to be charged to the room occupant for dispensing of beverages from reservoirs 51-55. If multiple units are in a particular room, each of the multiple units is addressed in sequence in response to the operator activating next key 43. The operator is advised to operate next key 43 because display 23 responds to the operator key inputs and the signals from the addressed station to display, from left to right, the room, the total cost of the dispensed beverages, as a three digit number for dollars, and a two digit number for cents. If there are units in the room which have not been processed, the character "+" appears to the right of the two cents digits in response to the most significant bit of the room number stored in the station table of RAMs 121-124 being a binary one.

These operations are described in greater detail in connection with FIG. 6Q. The signals read out during operation 544 indicating the number of drinks dispensed from reservoirs 51-55 are supplied to the counter in RAMs 121-124 which enables the grand total number of drinks to be determined during operation 538. Upon completion of operation 538 or operation 544, the program advances to clear keyboard counter operation 545, which is followed by setting the RAM delay recycle counter to thirty, during operation 546.

To determine which reservoirs are empty, the operator presses empties key 44 and the room number which is to be interrogated for empties or the nine keys twice or next key 43. In response to any of the sequences, there is displayed from left to right on display 23 the room number, the characters EMPTY, and the bottle number, as a one digit number from 1-5. If a room number is keyed after activation of empties key 44, that room number is displayed. If the nine key is activated twice, data processor 22 is activated so a sequential addressing of units 14 is begun to determine one of the units having an empty reservoir. If the nine key is activated twice or next key 43 is activated after empties key 44 has been activated, the displayed room number is the number of one of the rooms having empties. After the operator has written the displayed information into a ledger, he again presses next key 43 and another room number having empties is displayed. The operator continues to sequentially activate next key 43 in this manner until all of units 14 have been addressed and the room number for each unit having empties is displayed.

The program flow chart in response to activation of empties key 44 and next key 43 is illustrated in FIG. 6L. During the first operation 535 all of units 14 are sequentially addressed, and a determination is made as to whether any empties exist at the addressed unit. As indicated in connection with FIG. 5, each addressed unit, when it receives a signal requesting empties to be transmitted to console 11, derives a signal for the empty reservoir numbers. This number is stored in RAMs 121-124 and read out, with the number for the room, to display 23 each time next key 43 is activated. RAMs 121-124 are read out in this manner, in response to each activation of next key 43, until the data for all of units 14 having empties therein have been read out and displayed. Operation 536, after operation 535, determines if RAMs 121-124 store any additional empty indications. If no additional empty unit indications are stored in RAMs 121-124, the program advances to operation 540 during which designated addresses in PROMs 117, 118 cause display 23 to be supplied with the characters "NO MORE".

If all of the addressed units have not been interrogated for empties, operation 536 is followed by queue and data command operation 537, discussed in detail in connection with FIG. 6Q. Upon completion of queue and data command operation 537, the keyboard counter is cleared, during operation 538 and then, the display recycle delay counter is set to 30 during operation 539. Following operation 539 the next empty subroutine is exited.

When it is desired to determine whether empties exist at a particular room, the operator activates empties key 44 and the room number as a four digit number. During operation 541, a determination is made as to whether one to four keys have been entered within the last 30 seconds as indicated by the recycle delay counter. In response to no digits or more than four digits being entered within a thirty second delay recycle time, the program is advanced from operation 541 to operation 542, during which characters are displayed to advise the operator that he had an incorrect key entry. If the correct number of digits has been entered, a test is made during operation 543 to determine if the two most significant digits of the room number have a value of 99, which initiates the sequential addressing of units 14 and serves the same purpose as activating next key 43. If operation 43 determines that the two most significant digits were 99, the program is advanced to operation 535 and data for the first unit 14 having empty reservoirs are read out from RAMs 121-124 to display 23.

If operation 543 indicates that the two most significant room number digits are not 99, the station table of RAMs 121-124 is searched, i.e., sequentially scanned, during operation 545 so that the room numbers where units are in use are read out to the arithmetic unit of microprocessor 111. The arithmetic unit compares each of the room numbers supplied to it from the station table with the keyed room number during operation 545.

If searching and comparison operations 544 and 545 indicate that the keyed room does not have a unit therein, display 23 is activated during operation 546 by PROMs 117, 118 with characters to advise the operator with a visual indication of such a fact. If, however, the keyed room has been assigned a unit, an address signal is sent to the keyed room during queue and data command operation 537 and the addressed room sends a reply to console 11, which reply is supplied to display 23.

Consideration will now be given in greater detail to operations performed in response to activation of next key 43 by referring to the flow diagram of FIG. 6M. Activation of next key 43 is preceded by activation of either empties key 44 or room total key 41, in connection with a room having multiple units. As seen in FIG. 6M, the first operation 551 performed after activation of the next key is to determine if activation of empties key 44 was the previous command to data processor 22. If the last command was activation of empties key 44, the program is activated to operation 535, FIG. 6L, so that the next assigned unit number is located in the station table of RAMs 121-124.

If, however, operation 555 indicates that the last command was not activation of empties key 44, the program is advanced to operation 532, during which time a determination is made as to whether the last command was activation of room total key 41. If operation 552 indicates that the last command was activation of room total key 41, the program is stepped to operation 553, during which a determination is made by reading out the station table of RAMs 121-124 to determine if all of the multiple units in the room have been interrogated for the total amount therein. The operator is advised to press next key 43 because the display has a "+" sign after the two digit cent indication for the total for the previously addressed unit. During operation 553 the most significant bit in the room number is examined to determine if it has a binary 1 value, to indicate there are data for additional units in a room to be supplied to display 23. In response to either of operations 552 or 553 determining that the last command is not activation of room total key 41, or that there is not another unit in the system to be examined for the total, the program is advanced to operation 554, during which time display 23 is cleared. Operation 554 is followed by the keyboard counter of RAMs 121-124 being cleared during operation 555, in turn followed by setting the display recycle delay counter to a count of five seconds during operation 556. Upon completion of operation 556, the subroutine is exited.

If, however, operation 553 indicates that there is another unit to be considered in the room total, the program advances to operation 557, at which time the station table portion of RAMs 121-124 is searched to determine the number of the next unit to be interrogated for total purposes. During operation 555 this unit number is supplied to a communication gueue of RAMs 121-124 so that the unit can be addressed to respond in order to signals from console 11. Upon completion of operation 558, the keyboard counter is cleared during operation 559, which is followed by setting the recycle delay display counter to 30, operation 560. Upon completion of operation 560, the program is exited, to await the following depression of next key 43.

If speaker 27 is being activated in response to one of tamper switches 107 being closed, and operator believes that the tampering problem has been rectified, the operator activates alarm reset key 38. In response to alarm reset key 38 being activated, the program reaches step 562, FIG. 6M, during which the eight bits of the flag byte are retrieved from RAMs 121-124 and supplied to microprocessor 111 where the bit assigned to the tamper flag is changed to status so that it no longer indicates that the tamper flag has been set. After operation 562, the program advances to operation 563, during which the activating bit for speaker 27 is reset to command turn off of the speaker. Then, during operation 564 the system flag byte is returned from microprocessor 111 to the designated address for the byte in RAMs 121-124. Upon completion of operation 564, the program advances to clear display operation 554, clear keyboard counter operation 555, and to set the recycle display delay counter to 30, operation 556, which is followed by an exit.

After the operator has read the total amount to be charged to a checking out occupant of a room, he activates clear room total key 42 so that the totals stored in the station table of RAMs 121-124 for the unit(s) at the checked out room are erased. Activation of key 42 should be preceded by activation of room total key 41 and the keys for the four digit number of the room.

In response to activation of clear room total key 42, the program is energized so that the clear total subroutine of FIG. 6N is executed. The first operation 566 involved in the clear total subroutine is determining whether room total key 41 was the function key which was activated immediately prior to activation of clear room total key 42. If the last command was not in response to read total key 41, clear room total key 42 was erroneously energized because the room total should not be cleared unless the operator has determined the total amount spent by the room occupant, at the time of checkout. In response to operation 566 indicating that the last command was not a read total, a "BLEEP" flag is set during operation 567, whereby speaker 27 is activated and the operator is provided with an audio alarm that he has performed a serious error. After the audio alarm flag has been set, a visual display is activated during operation 568 to indicate that the clear total key was erroneously activated and that this key is only to be activated after the room total key has been activated. After operation 568, the signal stored in response to activation of key 42 is erased from RAMs 121-124 and the clear subroutine is then exited.

If, however, operation 566 indicates that the previous command was activation of room total key 41, the program is advanced to operation 569, during which the data stored in the station table of RAMs 121-124 for the unit read out in response to activation of room total key 41 is cleared. Upon completion of operation 569, the program is advanced to operation 570, during which the letters "CLEARED" are supplied to display 23 so that the operator is apprised of the fact that the data for the particular unit has been cleared. After operation 570, the program advances to operation 571, during which a determination is made as to whether there is another unit in the room being checked out. The determination of operation 571 is made by examining the most significant bit of the code indicating the room number. In response to another unit being in the room, display 23 is activated during operation 574 so that a "+" sign is displayed. The "+" indicates to the operator that he should press next key 43 so that the total of an added unit at the room being checked out can be processed as indicated supra in connection with FIG. 6M. If operation 571 indicates that there are no additional units in the room, or upon completion of operation 572, the program advances to clear keyboard counter operation 573, which is followed by operation 574, which involves setting the display recycle delay counter to 30; operation 574 is followed by exiting of the clear total subroutine.

In response to activation of able and disable keys 45 and 46, the operations illustrated by the flow diagram of FIG. 6P are performed. Activation of enable and disable keys 45 and 46 is followed by entry of the room number which is to be enabled or disabled. Therefore, the first operation 576 involved in the enable and disable subroutines involves determining if one to four digits have been entered within the 30 second interval of the recycle display delay counter. If operation 576 indicates that one to four digits were not timely entered, display 23 is activated so that the operator is advised that he is to re-enter the correct room number; after activation of the display the entries are cleared and the subroutine exited. If, however, operation 576 indicates that one to four digits were entered, the program advances to operation 577, during which a determination is made as to whether the two most significant digits, normally representing a floor number for the room being enabled or disabled, are 99. If the two most significant digits are both 9's and either enable or disable key 45 or 46 is activated, all of the units in the system are to be activated or deactivated. There are very infrequent activations of the nine key twice, as the two most significant digits, in combination with enable and disable keys 45 and 46. However, the feature of enabling and disabling the entire system automatically is inserted into the system because of the problems that would be associated with manual activation and deactivation of all of the system units.

If operation 577 indicates that 99 floor was entered, the program proceeds to operation 578, which determines from the station table, whether more units are in the system to be disabled. Operation 578 is never reached during an enabling operation because there are no active units in the station table prior to enabling of the system. If no more units 14 are in the system, display 23 is supplied with the characters DISABLED if key 46 is depressed. If, however, operation 578 determines that there are more units 14 in the station table, the next room unit 14 which has not been disabled is read from the station table during operation 579. After operation 579, the program proceeds to operation 580, during which the next unit in the station table is put in the queue command. Upon completion of queue command operation 580, during which the selected room number is put in a queue to be processed for communication purposes, the keyboard counter in RAMs 121-124 is cleared during operation 581, which is followed by setting the recycle display delay counter to 30, during operation 582, which is followed by an exiting of the enable or disable subroutine.

If operation 577 determines that the system is not to be enabled or disabled, the program is advanced to operation 583 during which a determination is made as to whether the two most significant key entries indicate a floor number equal to or greater than 80; floor 79 is the highest allowable floor number. In response to operation 583 indicating that the keyed floor is equal to or greater than 80, display 23 is activated so that the operator is advised that he has incorrectly entered the floor number. If the floor which has been keyed is less than 80, the program is advanced to operation 584, during which the room number is displayed together with the characters "ENABLED", in response to activation of key 45, or the room number is displayed together with the characters "DISABLED", in response to activation of key 46. Upon completion of operation 584, the program is advanced to queue command operation 580, during which the unit number for the keyed room number is entered into the queue for polling of units 14.

To call units 14 at the various rooms, data processor 22 is activated in accordance with the POLEM flow diagram illustrated in FIG. 6Q. Initially, a determination is made during operation 585 to determine if the last operation which was being performed by the data processor has been completed. If a last operation complete flag is not set, the subroutine immediately exits and polling cannot be conducted until the last operation has been completed. If the last operation has been completed, the program advances to operation 586, during which a last function command register of microprocessor 111 is interrogated to determine whether the last command ordered UART 161 to receive data from units 14, i.e., to command an addressed unit to send data. In response to operation 586 determining that send data from unit 14 was the last command function, the program is advanced to operation 587, during which time signals transmitted from the addressed unit 14 back to UART 161 and thence to the station table of RAMs 121-124 are sensed to determine if any of the five reservoirs 51-55 at the addressed unit have had any drinks dispensed from them. If operation 587 reveals that drinks have been served from the addressed unit 14, the program advances to operation 588, whereby a clear signal is supplied as a command byte for the communication polling queue to remove the addressed unit from the queue. Upon completion of operation 588, the program is advanced to operation 589, during which time the number of drinks which were received by data processor 22 from the addressed unit 14 is updated in the station table.

Upon completion of operation 589, or if operation 587 indicates that no drinks were served by the addressed unit 14, the program advances to operation 591, during which the tamper status flag is examined to determine if the unit 14 which sent a message to console 11 signalled that tampering occurred at the unit. In response to the tampering flag being set, the program proceeds to operation 592, at which time speaker 27 is activated to provide an audio alarm. Then operation 593 is performed whereby display 23 is supplied with a visual indication of tampering through the display of the characters "TAMPER". Upon completion of operation 593, the program is advanced to operation 594, during which a reset tamper message is sent from console 11 to the addressed unit 14.

If operation 586 indicates that the last command signal transmitted from console 11 to the addressed unit 14 is not a send data command or if operation 590 indicates that the sending unit 14 did not set the tamper flag, the program advances to operation 595, during which the signal indicating last activated function key of keyboard 23 is retrieved. Then, during operation 596, microprocessor 111 determines whether this function indication signal is the same as the previous keyboard function. If operation 596 indicates that the same function key was activated twice in a row, the function indicated by the function key is performed during operation 597. Upon completion of operation 597, the program is advanced to operation 598, during which the previously queued functions to be executed by data processor 22 are cleared.

If operation 596 indicates that the keyboard function which was retrieved during operation 595 is not the same as the most previously activated keyboard function, the program advances to operation 600, during which the next addressed unit to polled is selected, as stored in the communications queue. Upon completion of operation 600, the program advances to operation 601, during which time a determination is made as to whether there are any function indication signals in the function queue. If operation 601 indicates that there are queued functions, the program advances to operation 597 and the next function in the queue is initiated. If operation 601, however, indicates that there are no queued functions, the program advances to operation 602, during which the queue to control signalling to the units 14 is interrogated and the next unit in the queue is addressed. Upon completion of operation 602, the subroutine is exited.

The program described in connection with the flow diagram of FIG. 6 is written in detail in the INTEL 8080A assembly language in accompanying Appendix I.

While there has been described and illustrated one specific embodiment of the invention, it will be clear that variations in the details of the embodiment specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8##