US 4,231,022 AGrant
Interpolative PCM Decoder Utilized for .Mu.-Law and a-Law
Issue Date:1980-10-28
•3 Claims
•2 Drawing Sheets
Abstract
An interpolative PCM decoder converts PCM signals having polarity bits, segment selection bits and uniform quantization bits into an analog signal. The PCM decoder may be used both for .mu.-law and A-law conversion by use of simple circuits and includes an AND gate circuit which produces a logical product between a selection signal for selecting a minimum unit of an analog value of a lower end of a segment and a control signal for change-over between the .mu.-law and the A-law, and a circuit generating the same analog values as the minimum unit of the analog value in accordance with an output of the AND gate circuit.
Metadata
Assignee
- Hitachi, Ltd.
Inventors
- Hiroshi Kosugi
- Hirofumi Inoue
- Hirotoshi Shirasu
Application Information
Application Number:US 9698418
Filing Date:1978-12-15
Priority Date:1978-01-06
Art Unit:236
Classifications
IPC:
H03K 1302
Field of Search:
340179347 M;347 DA15 AV
Patent Drawings (2 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to interpolative PCM decoders, and more particularly to an interpolative PCM decoder which can be changed-over between A-law and .mu.-law uses.
2. Description of the Prior Art
An interpolative PCM decoder is described in detail in G. R. Ritchie et al; "Interpolative Digital to Analog Converters", IEEE, COM-22, 11, Nov. 1974.
The feature of this system resides in that all the quantization levels are not realized with a ladder circuit, but that only the ends of segments are realized with the ladder circuit, equally divided levels within the segments being realized by time-related averaging operations.
As will be stated in detail later, the interpolative PCM decoder disclosed in the above literature is for the .mu.-law. It cannot be used as an interpolative PCM decoder for the A-law, which needs to be constructed separately. Whether an interpolative PCM decoder is for the A-law or for the .mu.-law is decided, as will be stated later, depending on whether a logic circuit within the decoder is for the A-law or for the .mu.-law. Therefore, in order to use one interpolative PCM decoder for both the A-law and the .mu.-law, both a logic circuit for the .mu.-law and a logic circuit for the A-law must be included in the decoder, and approximately twice as many hardware elements as those for the .mu.-law use alone are required.
Summary of the Invention
This invention has for its object to provide an interpolative PCM decoder which can be very simply changed-over between A-law and .mu.-law uses.
In order to accomplish the object, this invention makes improvements in an interpolative PCM decoder having holding means for holding a polarity bit signal, segment selection bit signals and uniform quantization bit signals for one sampling period, means for receiving the uniform quantization bit signals from the holding means and expanding the bit signals into a group of 1-bit signals on a time axis, means for adding the signals from the expansion means and the segment selection bit signals, a digital-to-analog (D/A) converter which generates an analog value of a lower end of each segment through selection of any of a group of switches contained therein, and a logic circuit for the .mu.-law which receives an output of the addition means and which generates a selection signal for the switch; and is characterized by additionally disposing therein an AND circuit which takes a logical product between a selection signal for selecting a minimum unit of the analog value of the lower end of the segment and a control signal for change-over between the .mu.-law and the A-law, a further switch which is selected by the output of the AND circuit, and means for generating the same analog value as the minimum unit of the first-mentioned analog value through the switch.
In this invention, the expression "means for expanding the uniform quantization bit signals into a group of 1-bit signals on a time axis" signifies means such as e.g. a binary rate multiplier wherein binary codes to a number corresponding to the magnitude of a bit signal composed of a plurality of bits are made "1" on a time axis, the other binary codes being made "0". That is, the means expands the uniform quantization bit signal into a 1-bit signal of "1" or "0" every subinterval within one sampling period.
Brief Description of the Drawing
FIG. 1 is a diagram showing the schematic arrangement of an interpolative PCM decoder,
FIG. 2 is a diagram showing a detailed circuit of a part in FIG. 1, and
FIGS. 3 and 4 are diagrams each showing the essential portions of an embodiment of this invention.
Description of the Preferred Embodiments
Before the detailed description of an embodiment of this invention, a prior-art interpolative PCM decoder for the .mu.-law will be discussed with reference to FIG. 1. In the following description, a PCM code is assumed to be a signal of 8 bits.
In FIG. 1, among bit signals b.sub.0 -b.sub.7, the polarity bit signal b.sub.0 and the segment selection bit signals b.sub.1 -b.sub.3 are stored in a logic memory circuit 1 constructed of a register, and the uniform quantization bit signals b.sub.4 -b.sub.7 are stored in a logic memory circuit 1' constructed of a register. The uniform quantization bit signals b.sub.4 -b.sub.7 are entered into a binary rate multiplier (BRM) 2 which turns these signals into 1-bit signals expanded on a time axis. The segment selection bit signals b.sub.1 -b.sub.3 of the logic memory circuit 1 and a carry signal being an output of the binary rate multiplier 2 are added in an adder 3. An output of the adder 3 is entered into a .mu.-law logic circuit 4 (the contents of which will be described in detail later). An output of the logic circuit 4 and the polarity bit signal b.sub.0 are entered into a digital-to-analog (D/A) converter 5 which is composed of a ladder circuit (ladder resistor network), selector switches etc. Thus, decoded analog signals can be obtained.
In the .mu.-law of CCITT, the analog values of the lower ends of segments are determined to be 0, 1, 3, 7, 15, 31, 63 and 127 when the full scale is 255. The correspondence between these analog values and the segment selection bit signals b.sub.1, b.sub.2, b.sub.3 is specified as given in Table 1.
In the interpolative decoder, only the lower ends of the respective segments in Table 1 and "255" are realized with the ladder circuit. Moreover, it is operated at a speed which is 16 times higher than that of a non-interpolative decoder. Thus, a uniform quantization level of 1/16 in each segment is obtained by performing a time average concerning 1 sampling period.
The ladder circuit in the D/A converter 5 is constructed as shown in FIG. 2. This ladder circuit is called the R-2R type. Ordinarily, R is termed the series resistance and 2R the parallel resistance. For the convenience of the explanation, it is supposed that the polarity bit signal b.sub.0 is always "1". Voltage switches VS.sub.1 -VS.sub.8 transmit a voltage of +V.sub.H (V) when drive signals S.sub.1 -S.sub.8 of the corresponding logic signal ladder switches are "1", and transmit a voltage of 0 (V) when they are "0". Thus, S.sub.1 -S.sub.8 have weights of 2.sup.0, 2.sup.1, . . . and 2.sup.7 for an output voltage V.sub.OUT respectively.
The relationship between b.sub.1, b.sub.2, b.sub.3 representative of the segment numbers in the PCM codes of the .mu.-law and S.sub.1 -S.sub.8 becomes as indicated in Table 2.
Logic for converting the segment selection bit signals b.sub.1 -b.sub.3 into the logic signals S.sub.1 -S.sub.8 (which is called the logic .mu.) is realized by the .mu.-law logic circuit 4. In the output of the adder 3 (FIG. 1) and Table 2, b.sub.1 ' indicates a signal which is necessary for denoting the maximum value appearing when the signal from the BRM 2 is added to the segment selection bit signals b.sub.1, b.sub.2, b.sub.3.
The inventor made studies for applying this interpolative PCM decoder to a case of the A-law stipulating another sort of PCM codes. According to the A-law, the lower ends of segments are specified as 0, 2, 4, 8, 16, 32, 64 and 128 with the full scale being 256. Therefore, a table prepared for the A-law similarly to Table 2 for the .mu.-law becomes Table 3.
That is, logic for converting the segment selection bit signals b.sub.1 -b.sub.3 into S.sub.1 ' and S.sub.1 -S.sub.8 and different from the case of the .mu.-law (this shall be called the logic A) is required within the decoder. Therefore, in order to use a single decoder for both the .mu.-law and the A-law, logic circuits of both the logic .mu. and the logic A must be included within the decoder.
Hereunder, this invention having solved the above problem will be described in detail.
Table 4 is for explaining the principle, and indicates the relationship among the segment selection bit signals in the 8 bits of the decoder input, the logic signals or drive signals S.sub.1 -S.sub.8 of the ladder switches, and the ladder output values.
In Table 4, S.sub.1 has a weight of 2.sup.7, S.sub.2 a weight of 2.sup.6, . . . , S.sub.7 a weight of 2.sup.1, and S.sub.8 a weight of 2.sup.0. By endowing S.sub.8 ' with a weight of 2.sup.0 likewise to S.sub.8, the analog values of the A-law become equal to the codes of the .mu.-law with S.sub.8 '=2.sup.0 added thereto. For example, when "b.sub.1 ' b.sub.1 b.sub.2 b.sub.3 " is "0011", "S.sub.1 -S.sub.8 " is "00000111" and its analog value is 2.sup.2 +2.sup.1 +2.sup.0 =7 in the .mu.-law. On the other hand, in the A-law, "S.sub.1 -S.sub.8, S.sub.8 '" is "000001111" and its analog value becomes 2.sup.2 +2.sup.1 +2.sup.0 +2.sup.0 =8. That is, it is proper to always make S.sub.8 ' "0" in case of the .mu.-law and to make S.sub.8 '=S.sub.8 in the A-law. S.sub.8 can be said to be a selection signal for selecting the minimum unit of the analog value of the lower end of the segment. An understanding of this invention can be obtained referring to FIG. 3 and FIG. 4.
FIG. 3 is a diagram showing the essential portions of an embodiment of this invention.
In order to make the weight by S.sub.8 ' equal to the weight by S.sub.8, a point A may be connected to a point B through a resistance R and the point B may be connected to the voltage switch VS.sub.8 through the resistance 2R and similarly to a voltage switch VS.sub.8 ' through a resistance 2R as illustrated in FIG. 3. That is to say, the resistance 2R is connected in parallel with the parallel resistance corresponding to the minimum analog value, and the voltage switch V.sub.8 ' is connected to this resistance 2R. Thus the impedance viewed below from the point A becomes 2R and the impedance viewed towards the voltage switch VS.sub.7 from the point A is also 2R, so that the total weight of S.sub.8 and S.sub.8 ' and the weight of S.sub.7 become equal. Both the impedances viewed towards the voltage switches VS.sub.8 and VS.sub.8 ' from the point B are 2R, so that the weights of S.sub.8 and S.sub.8 ' become equal and that the weight of each of S.sub.8 and S.sub.8 ' becomes 1/2 of the weight of S.sub.7.
To establish S.sub.8 '=0 for the .mu.-law and S.sub.8 '=S.sub.8 for the A-law as indicated in Table 4 can be realized by employing an AND circuit AND and a control signal for change-over "A" as illustrated in FIG. 3. The control signal "A" is made "1" for the A-law and "0" for the .mu.-law. Thus, an output S.sub.8 ' of the AND circuit AND becomes "0" for the .mu.-law and equal to S.sub.8 for the A-law.
In this way, it is unnecessary to employ logic circuits of both the logic .mu. and the logic A, and it suffices to use only the logic circuit for the logic .mu.. The decoder becomes usable also for the A-law with its hardware remaining identical to that of the decoder for the .mu.-law only.
FIG. 4 is a diagram showing the essential portions of an embodiment in which the polarity bit signal b.sub.0 is also taken into account.
In the figure, voltage switches +VS.sub.1 to +VS.sub.8, +VS.sub.8 ', -VS.sub.1 to -VS.sub.8 and -VS.sub.8 ' provide outputs +V.sub.H (V) when the logic signals are "1" and the polarity bit signal b.sub.0 is "1", and they provide outputs -V.sub.H (V) when the logic signals are "1" and b.sub.0 is "0". Consideration is now given to the problem of how an output voltage changes depending on the value of the polarity bit b.sub.0 will be indicated as to the bit S.sub.8. Assuming S.sub.8 to be "1" and b.sub.0 to be "1", both the voltage switches +VS.sub.8 and -VS.sub.8 provide +V.sub.H owing to an inverter (INV), an OR circuit (OR) and an AND circuit (AND), and assuming S.sub.8 to be "1" and b.sub.0 to be "0", both the voltage switches +VS.sub.8 and -VS.sub.8 provide -V.sub.H. Therefore, +V.sub.H (V) and -V.sub.H (V) are respectively delivered as the output voltages through a resistance 2R. On the other hand, when S.sub.8 is "0", the output voltages become 0 (V) irrespective of the values of b.sub.0.
The operation above described is quite similar as regards S.sub.1 -S.sub.7 and S.sub.8 '. With the present embodiment, the decoder can naturally be used for the A-law by disposing only the logic circuit for the logic .mu.. Although, in the foregoing two embodiments, the ladder circuits have been illustrated as being of the voltage drive type, it goes without saying that a ladder circuit of the current drive type may be employed.
Claims
We claim:
1. In an interpolative PCM decoder having holding means for holding a polarity bit signal, segment selection bit signals and uniform quantization bit signals for one sampling period, means for receiving uniform quantization bit signals from the holding means and expanding the bit signals into a group of 1-bit signals on a time axis, means for adding the signals from the expansion means and the segment selection bit signals, a digital-to-analog converter which generates an analog value of a lower end of each segment, and a logic circuit for the .mu.-law which receives an output of the addition means and which delivers a selection signal for generating the analog value to cause the output of the digital-to-analog converter to be switched from the lower boundary value of a given segment to the lower boundary value of the next higher segment as a function of time within one sampling period, said interpolative PCM decoder further comprising an AND circuit which receives the selection signal for selecting a minimum unit of the analog value of the lower end of the segment and a control signal for change-over between the .mu.-law and the A-law, and means for generating the same analog value as the minimum unit of the first-mentioned analog value in accordance with an output of said AND circuit.
2. An interpolative PCM decoder according to claim 1, wherein said expansion means is a binary rate multiplier.
3. An interpolative PCM decoder according to claim 1 or 2, wherein said digital-to-analog converter consists of a ladder circuit and a group of driving switches which are selected by the selection signals, and the generation means consists of a resistance which is connected in parallel with a parallel resistance corresponding to the minimum value of the analog values of said ladder circuit and a driving switch which is connected in series with the first-mentioned resistance.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3893102 | 1975-07-01 | Candy | |
| US3987436 | 1976-10-01 | Candy et al. |
Non-Patent Literature (1)
- Ritchie et al., "Interpolative Digital-to-Analog Converters," IEEE Transactions on Communications, Nov. 1974, pp. 1797-1806 (COM-22; No. 11).