US 4,230,980 AGrant
Bias Circuit
Issue Date:1980-10-28
•12 Claims
•4 Drawing Sheets
Abstract
A bias circuit for generating bias voltages or bias currents including first and second elements for generating a voltage corresponding to the sum of two voltage drops in a forward p-n junction; first and second transistors for generating a negative feedback current; at least one resistor for determining the value of a constant current for generating bias voltages; a negative feedback circuit; a third resistor connected in the feedback circuit, and; a starting element for supplying currents to the first and second elements and to the first and second transistors in an initial state when the power is turned on, whereby the feedback circuit operates to generate the constant current which is used for forming bias voltages.
Metadata
Assignee
- Fujitsu Limited
Inventors
- Yoshiaki Sano
- Toshio Hanazawa
- Hideo Honda
Application Information
Application Number:US 0404063
Filing Date:1979-05-18
Priority Date:1978-05-24
Art Unit:212
Classifications
IPC:
G05F 320
Field of Search:
307323330296 R1;4;16;19;22 T296;297;127
Patent Drawings (4 sheets)
Description
Background of the Invention
(1) Field of the Invention
The present invention relates generally to a bias circuit and, more particularly, to a bias circuit for generating bias voltages, i.e., constant voltages, which may be, for example, supplied to the inputs of a pre---amplifier and to the inputs of an input stage of a power amplifier, in an audio-amplifier.
(2) The Prior Art
In a pre-amplifier or an input stage of a power amplifier, in order to stabilize its operation, it is necessary to apply stable bias voltages to the inputs of the pre-amplifier or the like. In addition, in recent years, the pre-amplifier or the like has been manufactured by using semiconductor technology, especially, integrated circuit technology, so the bias voltages applied to the pre-amplifier or the like are relatively low. Therefore, it is necessary to apply low and stable bias voltages to the pre-amplifier or the like.
One prior art bias circuit for generating bias voltages which may be, for example, applied to the inputs of a pre-amplifier or the like, is composed of diodes whose forward voltages serve as bias voltages. However, the change of the voltage applied to the diodes varies the forward resistance of the diodes, i.e., varies the forward voltages of the diodes. Therefore, the bias voltages generated from the bias circuit formed by diodes are unstable with respect to the change of the power voltage supplied to the bias circuit.
Another prior art bias circuit is composed of Zener diodes whose Zener voltages serve as bias voltages. The bias voltages generated from the bias circuit formed by Zener diodes are stable with respect to the change of the power voltage supplied to the bias circuit. However, it is difficult to generate a low bias voltage, for example, less than 5 volts.
Summary of the Invention
Therefore, a principal object of the present invention is to provide a bias circuit for generating low bias voltages which are stable with respect to the change of the power voltage supplied to the bias circuit.
It is another object of the present invention to provide a bias circuit for generating bias currents which are stable with respect to the change in power voltage supplied to the bias circuit.
The present invention provides a bias circuit for generating bias voltages or bias currents comprising: first and second elements for generating a voltage corresponding to the sum of two voltage drops in a forward p-n junction; first and second transistors for setting a negative feedback current; at least one resistor for determining the value of a constant current for generating bias voltages; a negative feedback circuit; a third resistor connected in the feedback circuit, and; a starting element for supplying currents to the first and second elements and to the first and second transistors in an initial state when the power is turned on, whereby the feedback circuit operates to generate the constant current which is used for forming bias voltages.
The present invention will be more apparent from the following description with reference to the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a circuit diagram illustrating a first embodiment of the bias circuit according to the present invention;
FIG. 2 is a graph showing the relationship between the current I.sub.3 and the currents I.sub.4 and I.sub.6, appearing in FIG. 1:
FIG. 3 is a circuit diagram illustrating the bias circuit of FIG. 1 connected to a pre-amplifier of an audio-amplifier;
FIG. 4 is a circuit diagram illustrating a second embodiment of the bias circuit according to the present invention;
FIG. 5 is curves showing the relations between the current I.sub.3 and the currents I.sub.4 and I.sub.6, appearing in FIG. 4;
FIG. 6 is a circuit diagram illustrating the bias circuit of FIG. 4 connected to a pre-amplifier of an audio-amplifier.
Detailed Description of the Preferred Embodiments
Referring to FIG. 1, the bias circuit comprises a starting resistor R.sub.1, a first circuit formed by a transistor Q.sub.3, a resistor R.sub.3 and a transistor Q.sub.5 connected in series, a second circuit formed by two transistors Q.sub.4 and Q.sub.6 and a resistor R.sub.4 connected in series, and a third circuit for supplying constant currents to the first and second circuits, formed by two transistor Q.sub.1 and Q.sub.2. V.sub.cc, V.sub.R and GND indicate, a d.c. supply terminal, an output terminal of the bias circuit and a grounded terminal, respectively. C.sub.1 is a phase-compensating capacitor for preventing the generation of a positive feedback by the phase shift of a high frequency which may invite the oscillation of the negative feedback loop composed of the transistors Q.sub.1, Q.sub.6 Q.sub.4 and Q.sub.2 and a resistor R.sub.2. Therefore, if there is no possibility of such oscillation, the phase-compensating capacitor C.sub.1 can be omitted. R.sub.2 is a resistor for restricting the base current of the transistor Q.sub.1 and stabilizing the gain of the negative feedback loop.
The operation of the bias circuit of FIG. 1 is as follows.
When the d.c. supply is turned on, a forward voltage is applied to the emitter of the transistor Q.sub.1. However, since the transistor Q.sub.2 does not conduct yet, the base current of the transistor Q.sub.1 does not flow, so that the transistor Q.sub.1 does not conduct. Therefore, current supplied from the d.c. supply flows only through two paths, one of which is composed of the resistor R.sub.1, the transistor Q.sub.3, the resistor R.sub.3 and the transistor Q.sub.5, while the other is composed of the resistor R.sub.1, the transistor Q.sub.4, the transistor Q.sub.6 and the resistor R.sub.4. These transistors Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 are selected so as to satisfy the formulas (1) and (2) below.
where S.sub.E3, S.sub.E4, S.sub.E5 and S.sub.E6 are the emitter areas of the transistors Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6, respectively. As a result, as shown in FIG. 2, in an initial state wherein the collector current I.sub.3 of the transistor Q.sub.3 is relatively low, the collector current I.sub.4 of the transistor Q.sub.4 is greater than the collector current I.sub.6 of the transistor Q.sub.6. Therefore, a current I.sub.B which equals (I.sub.4 -I.sub.6) is supplied to the base of the transistor Q.sub.2, so that the transistor Q.sub.2 conducts. This conduction of the transistor Q.sub.2 causes the base current of the transistor Q.sub.1 to flow. As a result, the transistor Q.sub.1 also conducts. Therefore, the current which is supplied from the d.c. supply terminal V.sub.cc to the transistors Q.sub.3 and Q.sub.4 flows through the transistor Q.sub.1, not through the starting resistor R.sub.1. Thus, the operation of the starting resistor R.sub.1 is completed. In order to maintain the transistor Q.sub.1, conductive it is preferable that the value of the starting resistor R.sub.1 be selected between the value of the saturation resistance and the value of the cut-off resistance in the transistor Q.sub.1. It should be noted that a junction FET (Field Effect Transistor), or other switching means which may effect the above-mentioned operation, can also be employed instead of the resistor R.sub.1.
In the bias circuit of FIG. 1 in which the transistor Q.sub.1 is conducting, the base current I.sub.B of the transistor Q.sub.2 is selected to be small and neglible compared with the currents I.sub.4 and I.sub.6. The actual value of the current I.sub.B is I.sub.1 /.beta..beta.' where I.sub.1 is the collector current, and .beta. and .beta.' are the current amplification factors of the transistors Q.sub.1 and Q.sub.2, respectively. As a result, the current I.sub.4 and the current I.sub.6 are nearly equal. This corresponds to the state when the current I.sub.3 equals I.sub.3 (OP) in FIG. 2. In addition, the current I.sub.6 is fixed to be a constant value by the collector-base connected transistor Q.sub.5, which serves as a diode. This causes the currents I.sub.1 and I.sub.2 to be constant, so that the currents I.sub.3 and I.sub.5, which are equal, are also constant. Therefore, a voltage at the point A, namely, at the terminal V.sub.R , is constant, which voltage V.sub.R1 can be expressed as follows.
where V.sub.BE3 and V.sub.BE5 are the base-emitter voltages of the transistors Q.sub.3 and Q.sub.5, respectively. The bias voltage V.sub.R1 is a constant voltage regardless of the change of the d.c. supply voltage, since such a change of voltage is absorbed in the emitter-collector voltage V.sub.EC of the transistor Q.sub.1.
The selection of the transistors Q.sub.3 through Q.sub.6 and the resistors R.sub.3 and R.sub.4 of FIG. 1 will be explained below.
V.sub.BE3 and V.sub.BE5 in the equation (3) can be expressed as follows.
where V.sub.BEi is the base-emitter voltage of the transistor Qi(i equals 3 through 6). In general, ##EQU1## where k: Boltzmann's constant
T: Absolute temperature
q: Charge
I.sub.c : Collector current
I.sub.s : Saturated base-emitter current.
Then, the equations (4) and (5) can be rewritten as follows. ##EQU2## where I.sub.si is the saturated base-emitter current of the transistor Qi (i equals 3 through 6). In general, in a monolithic integrated circuit manufactured on a chip, the saturated base-emitter current of a transistor is in proportion to the area of the emitter of the transistor. When a plurality of transistors whose emitter areas are the same are connected in parallel, the saturated base-emitter current as a whole is in proportion to the number of the parallel-connected transistors. Therefore, defining two constants n.sub.1 and n.sub.2 as I.sub.s4 /I.sub.s3 and I.sub.s5 /I.sub.s6, respectively, and using the condition that I.sub.3 =I.sub.5 and I.sub.4 =I.sub.6, the equation (9) is obtained. ##EQU3## Thus, as understood from the equation (9), the constant value of the current I.sub.3 can be determined by selecting four values, namely, the two constants n.sub.1 and n.sub.2 depending upon the emitter areas of the transistors Q.sub.3 through Q.sub.6 and the two values of the resistor R.sub.3 and R.sub.4. As a result, the voltage V.sub.R1 at the point A becomes a constant voltage.
In the bias circuit of FIG. 1, since a constant voltage can be obtained by causing the current I.sub.3 to be constant, a plurality of constant voltages can also be obtained by inserting one or more diodes between the points B and C. For example, a low bias voltage which is n-times of a base-emitter voltage V.sub.BE of a transistor can be obtained by inserting a plurality of transistors which serve as diodes.
In FIG. 1, a transistor Q.sub.7, whose base and emitter are connected to the base of the transistor Q.sub.1, and the d.c. supply terminal V.sub.cc, respectively, serves as a constant d.c. supply source. The collector current of the transistor Q.sub.7 is a constant current which is in proportion to the current I.sub.1 and the ratio of the emitter area of the transistor Q.sub.7 to that of the transistor Q.sub.1.
FIG. 3 is a circuit diagram illustrating the bias circuit of FIG. 1 connected to a pre-amplifier of an audio-amplifier. In FIG. 3, the elements illustrated in FIG. 3 which are identical with those of FIG. 1 are given the same reference numerals as in FIG. 1. In FIG. 3, the bias circuit B.sub.1 further includes two transistors Q.sub.8 and Q.sub.9 which serve as diodes, in addition to the bias circuit of FIG. 1, so that four bias voltages V.sub.R1, V.sub.R2, V.sub.R3 and V.sub.R4 are obtained at the terminals A, B, B' and C, respectively. The pre-amplifier of FIG. 3 is composed of a signal source SS, a capacitor C.sub.11 for cutting off the direct-current component of the input signal, an input resistor R.sub.11, an input transistor Q.sub.12, two bias transistors Q.sub.11 and Q.sub.13 for the input transistor Q.sub.12, two Darlington-connected transistors Q.sub.14 and Q.sub.15 which serve as an amplifier, a bias transistor Q.sub.7 for the two transistors Q.sub.14 and Q.sub.15, and two output transistors Q.sub.16 and Q.sub.17 connected in series. In this case, the bias transistor Q.sub.7 supplies a bias current, which is stable regardless of the change of the d.c. supply voltage, to the transistors Q.sub.14 and Q.sub.15. The terminal V.sub. out between the output transistors Q.sub.16 and Q.sub.17 is an output terminal of the pre-amplifier. Thus, the bias circuit of FIG. 1 is applicable to a pre-amplifier which needs a plurality of bias voltages and a bias current.
FIG. 4 is a circuit diagram illustrating a second embodiment of the bias circuit according to the present invention. In FIG. 4, the elements illustrated in FIG. 4 which are identical with those of FIG. 1 are given the same reference numerals as in FIG. 1. Although the bias circuit of FIG. 1 includes two resistors R.sub.3 and R.sub.4 for determining the magnitude of a constant current therein, the bias current of FIG. 4 includes a resistor R.sub.5 instead of the resistor R.sub.3 and R.sub.4.
The operation of the bias circuit of FIG. 4 is as follows.
In the same way as mentioned in the case of FIG. 1, when the d.c. supply is turned on, current supplied by the d.c. supply flows only through two paths, one of which is composed of the resistor R.sub.1, the transistors Q.sub.3 and Q.sub.5 and the resistor R.sub.5, while the other is composed of the resistor R.sub.1, and the transistors Q.sub.4 and Q.sub.6. These transistors Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 are selected so as to satisfy the formulae (1)' and (2)' as follows.
S.sub.E5 >S.sub.E6 (2) '
where S.sub.E3, S.sub.E4, S.sub.E5 and S.sub.E6 are the emitter areas of the transistors Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6, respectively. As a result, as shown in FIG. 5, in an initial state, wherein the collector current I.sub.3 of the transistor Q.sub.3 is relatively low, the collector current I.sub.4 of the transistor Q.sub.4 is greater than the collector current I.sub.6 of the transistor Q.sub.6. Therefore, a current I.sub.B which equals (I.sub.4 -I.sub.6) is supplied to the base of the transistor Q.sub.2, so that the transistor Q.sub.2 conducts, and after that, the transistor Q.sub.1 conducts. Then, the current which is supplied from the d.c. supply terminal V.sub.cc to the transistors Q.sub.3 and Q.sub.4 flows through the transistor Q.sub.1, not through the resistor R.sub.1. Thus, the operation of the starting resistor R.sub.1 is completed.
In the bias circuit of FIG. 4, in which the transistor Q.sub.1 is conducting, the base current I.sub.B of the transistor Q.sub.2 is selected to be negligible compared with the currents I.sub.4 and I.sub.6. As a result, the current I.sub.4 and the current I.sub.6 are nearly equal, which corresponds to the state when the current I.sub.3 equals I.sub.3 (OP) in FIG. 5. In addition, the current I.sub.6 is fixed to be a constant value by the collector-base connected transistor Q.sub.5, which serves as a diode. This causes the currents I.sub.1 and I.sub.2 to be constant, so that the currents I.sub.3 and I.sub.5 are also constant. Therefore, a voltage at the point A, namely, at the terminal V.sub.R, is constant, and the voltage V.sub.R1 can be expressed as follows.
where V.sub.BE4 and V.sub.BE6 are the base-emitter voltages of the transistors Q.sub.4 and Q.sub.6, respectively.
The selection of the transistors Q.sub.3 through Q.sub.6 and the resistor R.sub.5 of FIG. 4 will be explained below.
V.sub.BE4 and V.sub.BE6 in the equation (3)' can be expressed as follows.
where V.sub.BEi is the base-emitter voltage of the transistor Qi (i equals 3 through 6). In general, as mentioned above, in the equation (6) ##EQU4##
Then, the equations (4)' and (5)' can be rewritten as follows. ##STR1## Therefore, defining two constant n.sub.1 and n.sub.2 as I.sub.s4 /I.sub.s3 and I.sub.s5 I.sub.s6, respectively, and using the condition that I.sub.3 =I.sub.5 and I.sub.4 =I.sub.6, the equation (9)' is obtained. ##EQU5## Thus as understood from the equation (9)', the constant value of the current I.sub.3 which equals the current I.sub.5 can be determined by selecting three values namely, the two constant n.sub.1 and n.sub.2, depending upon the emitter areas of the transistors Q.sub.3 through Q.sub.6 and the value of the resistor R.sub.5. As a result, the voltage V.sub.R1 at the point A becomes a constant voltage.
In the bias circuit of FIG. 4, a plurality of constant voltages can also be obtained by inserting one or more diodes between the points B and C.
FIG. 6 is a circuit diagram illustrating the bias circuit of FIG. 4 connected to a pre-amplifier of an audio-amplifier. In FIG. 6, the elements illustrated in FIG. 6 which are identical with those of FIG. 4 given the same reference numerals as in FIG. 4. In FIG. 6, the bias circuit B.sub.2 further includes a transistor Q.sub.10, in addition to the bias circuit of FIG. 4, so that three bias voltages V'.sub.R1, V'.sub.R2 and V'.sub.R3 are obtained at the terminals A, B and C, respectively. The pre-amplifier of FIG. 6 is composed of a signal source SS, a capacitor C.sub.21 for cutting off the direct-current component of the input signal, an input resistor R.sub.21, an input transistor Q.sub.22, two bias transistors Q.sub.21 and Q.sub.23 for the input transistor Q.sub.22, two Darlington-connected transistors Q.sub.24 and Q.sub.25, which serve as an amplifier, a bias transistor Q.sub.7 for two transistors Q.sub.24 and Q.sub.25, and two output transistors Q.sub.26 and Q.sub.27 connected in series. Also, in this case, the bias transistor Q.sub.7 supplies a bias current, which is stable regardless of the change of the d.c. supply voltage, to the transistors Q.sub.24 and Q.sub.25. The terminal V.sub.out between the output transistor Q.sub.26 and Q.sub.27 is an output terminal of the pre-amplifier. R.sub.22 and R.sub.23 are resistors for determining the ratio of the feedback of the pre-amplifier and C.sub.22 is a capacitor for cutting off the direct-current component in the feedback current of the pre-amplifier. C.sub.23 is a capacitor for cutting off the high-frequency component of the input signal. Thus, the bias circuit of FIG. 4 is applicable to a pre-amplifier which needs a plurality of bias voltages and a bias current.
As explained hereinbefore, the bias circuit according to the present invention has the following advantages as compared with those of the prior art.
(1) A bias voltage generated from the bias circuit is stable regardless of the change of the d.c. supply V.sub.cc, since such a change can be absorbed by the transistor Q.sub.1.
(2) A bias voltage generated from the bias circuit is relatively low, since the bias circuit can generate a constant current which causes the bias voltage by using diodes or the like whose forward resistance is relatively small.
(3) The bias circuit also can generate a bias current which is stable regardless of the change of the d.c. supply V.sub.cc.
Claims
What is claimed is:
1. A bias circuit, having a d.c. supply terminal, a bias output terminal, and a reference potential terminal, comprising: first and second elements arranged in series between the bias output terminal and the reference potential terminal of said bias circuit, said first and second elements generating a voltage between the bias output terminal and the reference potential terminal, said voltage being equal to the sum of two voltage drops in a forward p-n junction; first and second transistors connected in series, the collectors of said first and second transistors being connected at a node, each of said first and second transistors having a base which is connected to a terminal between said first and second elements, wherein said first and second transistors generate a difference current at said node equal to the difference between the collector currents of said first and second transistors; resistor means, operatively connected to said second element, for determining the value of a constant current for generating bias voltages; a third transistor arranged between the bias output terminal and the d.c. supply terminal; a negative feedback circuit arranged between the base of said third transistor and said node, said difference current being introduced as an input thereto; a starting element, connected to the d.c. supply terminal, for supplying currents to said first and second elements and to said first and second transistors in an initial state when the power is turned on, whereby said negative feedback circuit operates to generate said constant current.
2. A bias circuit as set forth in claim 1, wherein said resistor means comprises a first resistor connected between said first and second elements and a secnod resistor operatively connected to said second transistor.
3. A bias circuit as set forth in claim 1, wherein said resistor means comprises of a single resistor connected to said second element.
4. A bias circuit as set forth in claim 1, wherein said bias circuit further comprises a fourth transistor whose base and emitter are connected to the base and the emitter of said third transistor, respectively, whereby a collector current of said fourth transistor may be obtained as a bias current.
5. A bias circuit as set forth in claim 1, further comprising at least one diode arranged between said first and second elements, whereby a plurality of bias voltages may be output from the terminals of said at least one diode.
6. A bias circuit as set forth in claim 5, wherein said at least one diode is a base-collector connected transistor.
7. A bias circuit as set forth in claim 1, wherein each of said first and second elements is a transistor.
8. A bias circuit as set forth in claim 1, wherein said starting element is a resistor.
9. A bias circuit, having a voltage supply terminal, a ground terminal, and an output terminal, comprising: a first transistor, having a collector, emitter and base, said first transistor emitter operatively connected to the voltage supply terminal and said first transistor collector operatively connected to the output terminal; a first resistor operatively connected between the voltage supply terminal and the output terminal; a second transistor, having a collector, emitter and base, said second transistor collector operatively connected to said first transistor base; a second resistor operatively connected to said second transistor emitter and to the ground terminal; a first capacitor operatively connected to said second transistor base and to the ground terminal; a third transistor, having a collector, emitter and base, said third transistor emitter operatively connected to the output terminal and said third transistor base operatively connected to said third transistor collector; a fourth transistor, having a collector, emitter and base, said fourth transistor emitter operatively connected to the output terminal, said fourth transistor base operatively connected to said third transistor collector and said third transistor base, and said fourth transistor collector operatively connected to said second transistor base and said first capacitor; a fifth transistor, having a collector, emitter and base, said fifth transistor base and collector operatively connected to said third transistor base, said fifth transistor emitter operatively connected to the ground terminal; a sixth transistor, having a collector, emitter and base, said sixth transistor collector operatively connected to said fourth transistor collector, said second transistor base, and said first capacitor, said sixth transistor base operatively connected to said fifth transistor base and collector, said sixth transistor emitter operatively connected to the ground terminal; and a seventh transistor, having a collector, emitter and base, said seventh transistor emitter operatively connected to the voltage supply terminal, said seventh transistor base operatively connected to said first transistor base and said second transistor collector.
10. The bias circuit as set forth in claim 9, further comprising: a third resistor operatively connected between said third transistor collector and base; and a fourth resistor operatively connected between said sixth transistor emitter and the ground terminal.
11. The bias circuit as set forth in claim 10, further comprising at least one diode operatively connected between said third resistor and said fifth transistor collector.
12. The bias circuit as set forth in claim 9, further comprising a third resistor operatively connected between said fifth transistor emitter and the ground terminal.
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| US3742338 | 1973-06-01 | Sugano et al. | |
| US3743850 | 1973-07-01 | Davis | |
| US3911353 | 1975-10-01 | van de Plassche | |
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