Loss of Clock Detector Circuit

This invention relates to the field of semiconductor apparatus, and more particularly to MOS integrated circuits.

In the art of MOS (metal-oxide-semiconductor) integrated circuits, many types of such circuits require an input clock signal, that is, a periodic sequence of electrical pulses, in order to provide a means for the proper timing of various electrical circuit functions. Among such types of MOS circuits that require such timing are the semiconductor charge coupled devices (CCD) and synchronous logic circuit devices such as the microprocessor. In many of these cases it is desirable to have a means for detecting clock interruption, that is, when the input clock stops (is "stuck"), at its high, low, or any intermediate voltage level.

A circuit for detection of loss of clock is achieved (FIG. 1) by means of a first electrical inverter (I.sub.1) connected for feeding its output to an electrical differentiator (.DELTA.). This differentiator is connected for feeding its output to a thresholding amplifier (A), that is, an amplifier of input signals above a threshold. This amplifier is connected for feeding its output to a unidirectional current inhibitor (D), such as an MOS diode. The current inhibitor is connected for feeding its output to a second inverter (I.sub.2). The second inverter is connected in parallel both with a charge storage capacitor (C) and with a leakage current source (J.sub.L). During operation, input from the clock source to be monitored is fed to the first inverter (I.sub.1), whereby the resulting binary output level of the second inverter (I.sub.2) indicates the presence vs. absence of clock pulses at the input, i.e., whether or not the clock is properly furnishing periodic pulses. All these circuit elements (I.sub.1, .DELTA., A, I.sub.2, C, J.sub.L) can be realized in MOS technology in the form of an integrated circuit in a single semiconductor crystal body, ordinarily semiconductive silicon.

In a specific embodiment of the invention (FIG. 2), the first inverter I.sub.1 is provided by a pair of MOS transistors (T.sub.1 and T.sub.2); the differentiator .DELTA. is provided by a capacitor (T.sub.3) feeding an MOS transistor load T.sub.4, the thresholding amplifier (A) is composed of two auxiliary inverters in tandem (T.sub.5, T.sub.6 ; T.sub.7, T.sub.8); the diode (D.sub.1) is provided by an MOS transistor (T.sub.9) whose gate electrode is connected to its drain; the second inverter (I.sub.2) is provided by another MOS transistor pair (T.sub.14, T.sub.15); the storage capacitor is provided by another MOS transistor (T.sub.13) whose source is connected to its drain; the leakage current source J.sub.L is provided by an MOS transistor (T.sub.10) whose gate electrode is connected to the node (N.sub.12) in the high current path between a pair of auxiliary MOS transistors (T.sub.11, T.sub.12) having a relatively large transconductance ratio. One of the auxiliary transistors (T.sub.11) has its source terminal connected to a voltage source V.sub.SS and its gate connected to the drain; the other of these auxiliary transistors (T.sub.12) has its drain connected to another voltage source V.sub.DD and its gate connected to yet another voltage source V.sub.GG which keeps this transistor T.sub.12 strongly in its "on" state. In this way, the output of the second inverter is essentially binary, indicating whether or not clock input is being properly fed to the first inverter input terminal (gate of T.sub.2), that is, whether clock pulses within predetermined frequency limits are being fed as input to the detector circuit.

This invention, together with its features, objects, and advantages can be better understood from the following detailed description when read in conjunction with the drawings in which:

FIG. 1 is a functional block diagram of a loss-of-clock detector circuit, in accordance with the invention; and

FIG. 2 is a schematic electrical circuit diagram of a loss-of-clock detector, in accordance with a specific embodiment of the invention in MOS technology.

As shown in FIG. 1 a clock source to be monitored feeds a first inverter I.sub.1, which feeds a differentiator .DELTA., which feeds a thresholding amplifier A, which feeds a unidirectional current inhibitor diode D, which feeds a charge storage capacitor C in parallel both with a leakage current source J.sub.L and a second inverter I.sub.2.

When the clock input source CLK is working properly by periodically delivering pulses to the first inverter, then the differentiator correspondingly periodically delivers "spikes" (almost delta functions) to the thresholding amplifier A, which charges the capacitor C positively to a maximum possible voltage V.sub.DD through the unidirectional diode D; thereby the output of the second inverter I.sub.2 is at a relatively "low" level, the leakage current source J.sub.L being insufficient to discharge the charge storage capacitor C. On the other hand, when the clock input source is stopped (or "stuck") at any voltage level, then there is zero output of the differentiator .DELTA., and thence the output of the amplifier A is at zero volts (or "ground"); thereby the storage capacitor C is discharged by the leakage current J.sub.L and hence the output of the second inverter goes to a relatively high voltage level, V.sub.DD for example. By appropriate choice of C and J.sub.L, this output can be made to change within for example as little as about four periods P of the clock input as measured when working properly.

FIG. 2 shows a schematic electrical circuit diagram of a loss-of-clock detector, in which the functional blocks of FIG. 1 are realized in MOS technology. Every transistor in FIG. 2 is an MOS transistor labeled with its transconductance .beta. (except for T.sub.3 and T.sub.13 whose respective capacitances rather than transconductances are given), for purposes of illustration of a specific example in N-MOS technology. The clock input is in the form of a clock pulse signal sequence of period P when operating properly, and the output of the detector circuit at node N.sub.0 is then at the voltage level of essentially V.sub.SS, but this output goes to the level of essentially V.sub.DD when the clock stops at any voltage level.

The parameters of the circuit shown in FIG. 2 are suitable for detection of a clock input of frequency (1/P) between about 4 kHz and 16 kHz, typically about 8 kHz.

Typical values of operating voltages are: V.sub.SS =0; V.sub.DD =+5 volts; and V.sub.GG =+12 volts. It should be noted that transistors (such as T.sub.6, T.sub.14, and T.sub.12), whose gate electrodes are connected to V.sub.GG and whose drains are connected to V.sub.DD, are always strongly in their "on" states during operation; whereas transistors (such as T.sub.1 and T.sub.7), whose gate electrodes and drains are connected to V.sub.GG, are characterized by a threshold voltage drop from source to drain during operation.

All transistors (including those such as T.sub.3 and T.sub.13 connected as capacitor elements) in the circuit shown in FIG. 2 are advantageously integrated in a single crystal P type silicon body, as known in N-MOS technology. Transistors T.sub.3 and T.sub.4 are advantageously surrounded by a guard ring (dotted line 30), of N+ type conductivity, connected to the most positive voltage supply source V.sub.GG ; this N+ guard ring is formed typically by impurity diffusion or ion-implantation at the surface of the silicon body at the same time as the source and drain diffusion or implantations of the transistors, as known in the art, in order to absorb and offer a sink for injected electrons and thereby to prevent these electrons from diffusing in the semiconductor substrate to other portions of the circuit.

The overall operation of the circuit shown in FIG. 2 is as follows:

Clock Input Working Properly: Output voltage=V.sub.SS ;

Clock Input Interrupted: Output voltage=V.sub.DD.

This operation results as follows. In the absence of clock input, that is, when the clock suddenly stops at a fixed input voltage, say V.sub.2, at input node N.sub.2, the voltage at node N.sub.3 asymptotically goes to a fixed value V.sub.3 depending upon the fixed voltage V.sub.2 at the input node N.sub.2. Accordingly, the voltage at N.sub.5 goes asymptotically to V.sub.SS, thereby keeping T.sub.5 in its "off" state regardless of the value of the fixed input voltage V.sub.2. As a result of T.sub.5 being "off", the gate of T.sub.8 goes to the voltage potential of V.sub.DD by virtue of T.sub.6 being always "on". Hence, T.sub.8 is "on" and the node N.sub.9 goes essentially to V.sub.SS, the transconductance .beta. of T.sub.8 being much greater than that of T.sub.7. Thus, there is no tendency for current to flow through T.sub.9, since T.sub.9 conducts current only in response to positive voltages at N.sub.9 which are at least a threshold above V.sub.SS. Accordingly, the transistor T.sub.15 turns off after T.sub.10 discharges the capacitor T.sub.13. At all times, T.sub.10 remains always slightly "on" during operation since its gate is connected to the node N.sub.12 between T.sub.11 and T.sub.12. As a consequence of T.sub.15 thus being "off", the output node N.sub.0 goes asymptotically to V.sub.DD by reason of the source-drain current path through T.sub.14. This voltage of V.sub.DD at node N.sub.0 represents an "alarm" indication that the clock input has been interrupted.

On the other hand, in the presence of clock input at the input node N.sub.2, when this input suddenly goes negative to V.sub.SS at the beginning of the first half-clock period, T.sub.2 turns "off", allowing the node N.sub.1 to go to V.sub.DD and causing a positive charge Q suddenly to surge from capacitor T.sub.3 to the gate of transistor T.sub.5, thereby turning it "on" momentarily. This charge Q depends upon both the height of the input voltage and the series capacitance of capacitor T.sub.3 and the gate-source of T.sub.5. While the input remains at V.sub.SS for a half-clock period, the gate electrode of the transistor T.sub.5 discharges charge Q through the source-drain path of transistor T.sub.4, which is always "on". This discharge of charge Q advantageously occurs within a time interval less than the half-clock period (P/2) during which the clock input is at +V.sub.IN, that is, the "on" impedance of T.sub.4 is sufficiently low that the relevant RC time constant for the discharge of Q is less than this half-clock period. Thus, at the commencement (say, t=0) of this half-clock period, T.sub.5 is turned "on" and remains "on" only for an initial portion of this period (until, say, t=.DELTA.t). Specifically, T.sub.5 turns "off" when the discharge of Q has progressed to the point (t=.DELTA.t) where the voltage on the gate electrode of T.sub.5 falls below the threshold of T.sub.5. In any event, only during the time interval (0, .DELTA.t) is T.sub.5 "on"; thereby the node N.sub.8 quickly goes to V.sub.SS during this interval (0, .DELTA.t), but goes to V.sub.DD otherwise. Thus the combination of T.sub.3 and T.sub.4 serves as a voltage differentiator with output at node N.sub.5.

It should be noted that although the impedance of T.sub.4 in its "on" state should be sufficiently small (transconductance .beta. sufficiently large) that the RC time constant of T.sub.3 with T.sub.4 be less than a half-clock period; nevertheless, the impedance of T.sub.4 in its "on" state should also be sufficiently large (transconductance .beta. sufficiently small) that the discharge time of node N.sub.5 is longer than the rise time of the voltage transition of node N.sub.1.

During the other (second) half-clock period, when the clock input voltage is V.sub.DD, the transistor T.sub.5 remains "off", since there is then no tendency for any positive charge to flow into its gate electrode (but only negative charge) injected with the substrate. Thus, during each full-clock period, only during an initial phase of duration .DELTA.t in each such period will the transistor T.sub.5 be in its "on" state. Consequently, only during the initial interval (0, .DELTA.t) of each clock period will the node N.sub.8 be essentially at potential V.sub.SS, the transconductance of T.sub.5 being much greater than that of T.sub.6 ; otherwise this node N.sub.8 will be at a potential equal to V.sub.DD (during the rest of each clock period after the initial phase .DELTA.t). As a consequence, only during each such time interval .DELTA.t will the transistor T.sub.8 be "off", and hence only during each such interval (.DELTA.t) will the node N.sub.9 be essentially at potential V.sub.GG (and at V.sub.SS otherwise), the transconductance of T.sub.8 being much greater than that of T.sub.7. Thereby, only during each such time interval .DELTA.t will current flow through the source-drain path of T.sub.7 (to node N.sub.9) and through T.sub.9 (connected as a unidirectional current inhibiting diode) to the node N.sub.13. This current flow brings the node N.sub.13 to the potential V.sub.GG less the thresholds of T.sub.7 plus T.sub.9. On the other hand, during each entire clock period of duration P, the transistor T.sub.10 is always slightly "on", as a result of its gate electrode connection to the common node N.sub.12 between T.sub.11 and T.sub.12. Thus, a leakage current J.sub.L flows from N.sub.13 through T.sub.10. This leakage current J.sub.L is constant so long as there is any positive charge (above a threshold) on the node N.sub.13 ; whereas, in the absence of such charge on this node, no leakage current flows through T.sub.10. The value of this constant leakage current J.sub.L is equal to the constant current through T.sub.11 multiplied by .beta..sub.10 /.beta..sub.11, i.e., the ratio of the transconductance of T.sub.10 to that of T.sub.11. Accordingly, the parameters of T.sub.10 and T.sub.11 are selected such that this leakage current is sufficient to discharge the node N.sub. 13 when the clock input is interrupted and hence when no current flows through T.sub.9, that is, when the value of .DELTA.t goes to zero. On the other hand, this current J.sub.L should not be sufficient to discharge the node N.sub.13 when the clock input is working properly, and hence when the node N.sub.13 is being brought essentially to the potential V.sub.DD during periodic intervals of duration .DELTA.t. Thus, if and when the clock input is interrupted, the potential of the node N.sub.13, and hence the output of the circuit shown in FIG. 2, falls essentially to V.sub.SS only after at least one full period of interruption, and advantageously only after many periods.

In particular, for the parameters shown in FIG. 2, a clock input at 8 kHz would have to stop for at least about 0.5 milliseconds, i.e., about four such clock periods, before the output of the circuit would go from essentially V.sub.SS to V.sub.DD.

Although the invention has been described in conjunction with a specific embodiment, various modifications can be made without departing from the scope of the invention. For example, instead of N-MOS, it is obvious that P-MOS technology can be used with appropriate changes in the values of the voltage sources V.sub.SS, V.sub.DD, and V.sub.GG, and with all circuit elements still integrated in a single semiconductor crystalline body. Also, it is obvious that in certain cases, where the voltage levels of the clock input source are appropriate, there is no need for the first inverter I.sub.1 and the clock input can then be fed directly to the differentiator .DELTA.. In any event, instead of the inverter I.sub.1, any voltage level shifting device can be used which is characterized by an output in response to the clock input which is suitable for the differentiator. Also, the second inverter I.sub.2 can be replaced with any means for detecting the voltage at node N.sub.13 which does not draw current from this node, that is, a very high impedance output detector.