US 4,223,522 AGrant
Electronic Timepiece
Issue Date:1980-09-23
•8 Claims
•10 Drawing Sheets
Abstract
An electronic timepiece having a reversible stepping motor to actuate time-indicating hands to provide a time display, which comprises a driver circuit to produce driving current pulses composed of compound pulses appearing each time unit. A rotor of the stepping motor rotates a plurality of steps during each time unit to cause one of the time-indicating hands to advance through unequal intervals to provide a modulated display.
Metadata
Assignee
- Citizen Watch Co., Ltd.
Inventors
- Yasushi Nomura
- Fumio Nakajima
- Kenji Yamada
- Takayasu Machida
Application Information
Application Number:US 9605169
Filing Date:1978-11-13
Priority Date:1976-02-06
Art Unit:217
Classifications
IPC:
G04C 300G04B 3712
Field of Search:
5834023 R;23 BA;23 A;23 D;28 R;28 D;34;85.5;152 H636;660-663
Patent Drawings (10 sheets)
Description
This invention relates to an analog electronic timepiece equipped with an electro-mechanical transducer and capable of providing a modulated display.
In conventional analog electronic timepieces having in addition to a time display function such functions as an alarm or warning function to indicate that the life of a battery has expired, it was necessary to provide additional display devices such as light emitting diodes or other photo-electric display means which change in appearance in order to notify the user that a given function is operating. Since these additional functions added to the cost of a timepiece and increased the size of the movement these efforts were not successful and the additional functions were abandoned. Such conventional timepieces although capable of providing two different kinds of hand movement, either continuous or intermittent, featured hands which advanced through fixed and equal intervals and thus were quite simple and could not compete with digital timepieces having the capability of providing a large number of functions in a small amount of space.
It is accordingly an object of this invention to provide an analog electronic timepiece which is capable of advancing the hands of the timepiece through unequal intervals to provide a modulated display.
It is another object of this invention to provide a timepiece in which the modulated display is used as the display means for displaying the operational states of additional functions.
It is another object of the present invention to provide an electronic timepiece equipped with a stepping motor adapted to be driven in a plurality of steps within every one unit time to thereby advance the hands of the timepiece through unequal intervals.
It is a further object of the present invention to provide an electronic timepiece including a stepping motor to advance the rotatable hands of the timepiece so as to provide a modulated display in a normal operating mode.
It is a further object of the present invention to provide an electronic timepiece including a stepping motor to advance the rotatable hands of the timepiece through unequal intervals to provide a modulated display in response to an output from a state sensor adapted to detect the operational states of the timepiece.
These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a preferred embodiment of an electronic timepiece according to the present invention;
FIG. 2 is an example of a detail circuitry for the timepiece shown in FIG. 1;
FIG. 3 is a waveform diagram illustrating the operation of the circuit shown in FIG. 2;
FIG. 4 is a schematic view of a preferred example of a reversible stepping motor incorporated in the timepiece shown in FIG. 1;
FIG. 5 is a view showing the movement of the seconds hand driven by the stepping motor shown in FIG. 4;
FIG. 6 is another example of a detail circuitry for the timepiece shown in FIG. 1;
FIG. 7 is a waveform diagram showing various pulses obtained by the circuit of FIG. 6;
FIG. 8 is a view illustrating the movement of the seconds hand attained by the circuit of FIG. 6;
FIG. 9 is a block diagram of a modification of the timepiece shown in FIG. 1;
FIG. 10 is a block diagram of another preferred embodiment of the electronic timepiece according to the present invention;
FIGS. 11A and 11B show an example of a detail circuitry for the timepiece shown in FIG. 10;
FIGS. 12A and 12B show a waveform diagram showing various pulses produced in the circuit of FIGS. 11A and 11B; and
FIG. 13 is a view showing the movement of the seconds hand of the timepiece shown in FIG. 10.
Referring now to FIG. 1, there is shown a block diagram of a preferred embodiment of an electronic timepiece embodying the present invention. The electronic timepiece comprises a frequency standard 10 which is controlled by a quartz crystal (not shown) to produce a relatively high frequency signal of, for example, 32,768 Hz. This relatively high frequency signal is applied to a frequency divider 12 composed of a plurality of flip-flops (not shown) to produce a first low frequency signal of 1 Hz as a time unit signal, and a second low frequency signal which is higher in frequency than the first low frequency signal. The first low frequency signal is applied to a waveform converter 20 responsive to the first and second low frequency signals delivered from the frequency divider 12, to produce a first train of output pulses and second train of compound output pulses having the same polarity and delayed in phase from the first train of output pulses in response to the first low frequency signal. The first train of output pulses are applied to a driver circuit 14, which produces first driving current pulses in response to the first train of output pulses. These driving current pulses are applied to a stepping motor 16, which is driven stepwise to advance time-indicating hands 18 of the timepiece to display time. The second train of output pulses are applied through a change-over circuit 21 controlled by a state sensor 22 to the driver circuit 14, which produces second driving current pulses composed of a first pulse and second compound pulses appearing at predetermined timings during each time unit (i.e., per second) by which the stepping motor 16 rotates, a plurality of steps each in one of clockwise and counter-clockwise directions at the predetermined timings during each time unit. This rotation allows the seconds hand 18a to advance at unequal intervals to provide a modulated display.
FIG. 2 shows one example of the detail electric circuitry for the timepiece shown in FIG. 1. In FIG. 2, the waveform converter 20 comprises a first circuit section 23 composed of first and second positive going-edge triggered type flip-flops 24 and 26 having their inputs coupled to an output of the frequency divider 12 and an output of an inverter 28, respectively. An input of the inverter 28 is coupled to the output of the frequency divider 12 to receive the first low frequency signal .phi. therefrom. Clock input terminals of the flip-flops 24 and 26 are coupled to an intermediate stage of the frequency standard 12, to receive the second low frequency signal .phi.o therefrom. Outputs of the flip-flops 24 and 26 are coupled to the driver circuit 14 composed of OR gates 30 and 32 whose outputs are connected to inverters 34 and 36, respectively. Outputs of the inverters 34 and 36 are connected to a driving coil 16a of the stepping motor 16.
The waveform converter 20 also comprises a shift circuit 37 composed of first, second and third data-type flip-flops 38, 40 and 42 having their clock input terminals applied with the second low frequency signals .phi.o to provide outputs .phi.' and .phi.'" delayed in phase from each other. The output .phi.' of the first flip-flop 38 is directly applied to one input of an AND gate 44 and applied through an inverter 39 to one input of an AND gate 46. The remaining input of the AND gate 44 is coupled through an inverter 43 to the third flip-flop 42 to receive the output .phi.'", and the remaining input of the AND gate 46 is directly coupled to the output of the flip-flop 42. Thus, the AND gates 44 and 46 form part of a second circuite section 45 to generate output signals .phi.'.phi.'" and .phi.'.phi.'", respectively, as shown in FIG. 3. The output .phi.'" of the flip-flop 42 is directly applied to one input of an AND gate 48 and applied through the inverter 43 to one input of AND gate 50. The other input of the AND gate 48 is coupled to the output of the frequency divider 12 to receive the first low frequency signal therefrom, and the other input of the AND gate 50 is coupled through the inverter 28 to the output of the frequency divider 12 to receive the inverse of the low frequency signal .phi.. Outputs of the AND gates 48 and 50 are coupled to inputs of an OR gate 52, which generates an output signal .phi..phi.'"+.phi..phi.'" which is applied to one input of an AND gate 54 of the change-over circuit 21. As seen in FIG. 3, the output signal .phi..phi.'"+.phi..phi.'" has a pulse width .tau. less than the interval between the normal driving pulses, to open the AND gate 54 so that the output of an inverter 55 is gated therethrough only during a predetermined time interval to prevent an error in operation. Thus, the gates 48, 50 and 52 serve as an erroneous operation preventive circuit. The other input of the AND gate 54 is coupled through the inverter 55 to an output of the state sensor 22, which is directly coupled to one input of an AND gate 56 whose remaining input is coupled to an output of an OR gate 57 having its inputs coupled to the outputs of the flip-flops 24 and 26 of the driver circuit 14. Outputs of the AND gates 54 and 56 are coupled to a set terminal S and a reset terminal R of flip-flop 58 whose Q output is directly coupled to first inputs of AND gates 60 and 62 to control these gates. The AND gates 60 and 62 serve as a compound pulse generator forming part of the second circuit section 45 and have second inputs both coupled through an inverter 64 to the intermediate stage of the frequency divider 12 to receive the inverse of the second low frequency signal .phi.o. Third inputs of the AND gates 60 and 62 are coupled to the outputs of the AND gates 44 and 46, respectively. Outputs of the AND gates 60 and 62 are coupled to the remaining inputs of the OR gates 30 and 32 of the driver circuit 14.
In the circuit diagram of FIG. 2, the state sensor 22 is shown as a battery voltage drop detector which is composed of a resistor 66 connected to the positive side V.sub.dd of a battery, a nonlinear element 68 connected in series with the resistor 66, and an inverter 70 for voltage drop detection.
At normal voltage of the battery, the output of the inverter 70 is at a "1" logic level and the output of the inverter 55 is at a "0" logic level so that the AND gate 54 of the change-over circuit 21 no output. In this instance, outputs of the flip-flops 24 and 26 of the waveform converter 20 are applied through the OR gate 57 to the AND gate 56 which is opened by the output of the inverter 70. Therefore, the AND gate 56 generates an output by which the flip-flop 58 is reset, and the output of the change-over circuit 21 remains at "0" logic level. Consequently, the compound pulse generator composed of the AND gates 60 and 62 does not produce outputs at terminals a and a'. Under these circumstances, the flip-flops 24 and 26 of the waveform converter 20 provide output pulses at terminals b and b' in response to the first low frequency signal .phi. as shown in FIG. 3. These output pulses are applied through the OR gates 30 and 32 to the driving inverters 34 and 36, by which normal driving current pulses are generated. Thus, the stepping motor is driven stepwise to advance the rotatable hands 18 to provide time display.
When the battery voltage drops below a predetermined value, the output of the detection inverter 70 goes to a "0" logic level, inhibiting the AND gate 56. At the same time, the output of the inverter 55 goes to a "1" logic level and applied to the AND gate 54, which is opened in response to the output of the OR gate 52 of the erroneous operation preventive circuit to pass the output of the inverter 55 to the set terminal S of the flip-flop 58. Therefore, the flip-flop 58 is set and the output of the change-over circuit 21 goes to a "1" logic level. This output is applied to the AND gates 60 and 62 of the compound pulse generator, which is enabled to provide compound output pulses .phi.o.phi.'.phi.'" and .phi.o.phi.'.phi.'" at terminals a and a'. These outputs are applied to the OR gates 30 and 32, to which the output pulses b and b' are also applied. The OR gates 30 and 32 serves as synthesizing means which provides synthesized pulses 70 to 72 and 73 to 75 at the terminals c' and c as shown in FIG. 3. The synthesized pulses are applied to the driving inverters 36 and 34, by which modulated driving current pulses are generated as shown by the waveform d-d' in FIG. 3. The modulated current pulses are applied to the driving coil 16a of the stepping motor, which is driven at unequal intervals. More specifically, the stepping motor is rotated clockwise, counter-clockwise and clockwise at first, second and third steps, respectively, within several tens of milliseconds, each step having an interval corresponding to one second.
FIG. 4 shows an example of the stepping motor 16 adapted to be driven by the modulated driving current pulses mentioned above. In FIG. 4, the stepping motor 16 comprises a permanent magnet rotor 76, stators 78 and 80, and the driving coil 16a. In FIG. 4, the pulse 70 is applied to the driving coil 16a through which a current is therefore caused to flow. This brings the stator 78 to a state of South magnetization and stator 80 to a state of North magnetization such that the rotor 76 rotates clockwise in the first step as shown in FIGS. 4(b) and 5. In FIG. 4, reference numeral 82 denotes the core of the driving coil, and 84 and 86 designate points of static equilibrium. When the pulse 71 arrives under these conditions the stators 78 and 80 are excited and brought to the same states of magnetization as mentioned above so that the rotor 76 now rotates counter-clockwise in the second step as shown in FIG. 5 and returns to the attitude shown in FIG. 4(a). When the pulse 72 arrives the stators 78 and 80 are once again brought to respective states of South and North magnetization and the rotor 76 thus rotates in a third step as shown in FIG. 5 returning to the attitude it had in FIG. 4(b). The rotor in this fashion rotates between points of static equilibrium.
The clockwise-counterclockwise rotation is used to modulate the seconds hand 18a of the time-indicating mechanism 18 (see FIG. 1) which is coupled through the dial train drive to the stepping motor 16 such that the seconds hand follows this clockwise-counterclockwise movement. This modulated movement can be completed within several tens of milliseconds and will be repeated every one second, the seconds hand providing a modulated display.
One second after the initial pulse 70 has been applied the pulse 73, arrives and brings the stator 78 to a state of North magnetization and the stator 80 to a state of South magnetization whereby the rotor 76 rotates clockwise and assumes the attitude shown in FIG. 4(a). When the pulse 74 arrives under these conditions the stators 78 and 80 are once again brought to respective states of North and South magnetization such that the rotor 76 now rotates counter-clockwise to the attitude shown in FIG. 4(b). When the pulse 75 arrives the same states of magnetization are again induced and the rotor 76 thus rotates clockwise to the attitude shown in FIG. 4(a). Again the rotor 76 rotates between points of static equilibrium. As was previously the case, this clockwise-counterclockwise rotation modulates the seconds hand, thereby allowing the second hand to follow the clockwise-counterclockwise movement. This operation continues in a repetitive manner, modulating the seconds hand of the display device so that a drop in the battery voltage is clearly indicated.
FIG. 6 depicts a modified form of the circuit shown in FIG. 2. The circuitry shown is substantially identical with that of FIG. 2, except that the output of the AND gate 60 is connected to one input terminal of the OR gate 32 and the output of the AND gate 62 is connected to one input terminal of the OR gate 30. The waveforms which appear at output terminals g, g' are as shown in FIG. 7, and the driving coil 16a is supplied with modified alternating current pulses h-h' so that a driving current flows through its windings. The alternating current pulses h-h' are composed of a pulse train of three successive pulses 70', 71' and 72'. These successive pulses will cause the stepping motor to rotate in a clockwise-clockwise-counterclockwise manner which will modulate the seconds hand of the display such that the seconds hand follow this clockwise-clockwise-counterclockwise rotation in first, second and third steps as shown in FIG. 8. In this case the seconds hand 18a is advanced through intervals corresponding to two seconds during first and second steps and caused to return to the one second position during the third step. In this manner, the seconds hand 18a provides a modulated display.
Thus in accordance with a feature of the invention a drop in battery voltage is detected by a detecting device and the hands of a display device for a timepiece which employs a reversible stepping motor are modulated in order to clearly indicate that the battery should be replaced. This makes it possible to effect the replacement before the hands of the timepiece come to a halt. It is also possible to adapt the invention in such a way that the detecting device is utilized to detect the temperature within the timepiece and thus modulate the display to give a clear indication of an abnormal internal temperature. A further modification can be made in which the detector is adapted to detect the humidity within the timepiece. Thus a rise in the humidity would be detected and the hands of the display appropriately modulated to give the proper indication. It is also possible to detect certain specified times or dates of which the following are some examples:
(1) The compound modulated display can be adapted so that the hands of the display begin to be modulated at a specific time each day; the daily lunch hour or coffee break, for example.
(2) The compound modulated display can be adapted so that the hands of the display are modulated on a specified day such as a birthday.
(3) It is also possible to provide differing compound modulated displays for a specified respective time, date and day of the week. For example, changes in the days of the week can be discriminated by employing a compound modulated display without providing a separate display device for the week display.
By combining these features and varieties of hand movement with a normal method of time display it is possible to realize a unique, hitherto unavailable electronic timepiece characterized by a highly variable display.
While in the preferred embodiment of FIG. 1 the electronic timepiece has been shown as including the state sensor 22 and the change-over circuit 21, these components may be dispensed with as shown by a block diagram of FIG. 9 in which like or corresponding components are designated by the same reference numerals as those used in FIG. 1. In this case, the erroneous operation preventive circuit of the waveform converter 20 may be directly coupled to the compound pulse generator or may be dispensed with. With this arrangement, the compound pulse generator of the waveform converter 20 generates compound output pulses in normal operation mode of the timepiece. These compound pulses are applied to the synthesizer of the driver circuit 14, by which modulated driving pulses are generated in the normal timekeeping mode such that the stepping motor 16 advances the seconds hand 18a at unequal intervals to provide a modulated display in the normal operation.
A modified form of the electronic timepiece is shown in FIG. 10, in which like or corresponding component parts are designated by the same reference numerals as those used in FIG. 1 with the exception that a single prime (') has been added to those numerals indicative of modified elements. In this modification, a waveform converter 20' generates first output pulses composed of a plurality of single pulses, and second output pulses composed of a single pulse and compound pulses in response to low frequency signals from a frequency divider 12'. The first and second output pulses are selectively passed through a changeover circuit 21' controlled by a state sensor 22 to a driver circuit 14'. The driver circuit 14' generates normal driving pulses and modulated driving pulses in response to the first and second output pulses delivered from the waveform converter 20'. When the normal driving pulses are applied to a stepping motor 16, it rotates clockwise stepwise at an equal interval to advance rotatable hands 18 in a normal mode to provide normal time display. When, however, the modulated driving pulses are applied to the stepping motor 16, it causes the seconds hand 18a to advance at unequal intervals to provide a modulated display, indicating particular states of the timepiece such as those previously stated.
As shown in FIG. 11A, the freqeuncy divider 12' comprises a plurality of flip-flops, of which only FF9 to FF17 are shown. The waveform converter 20' comprises a first circuit section 100 and a second circuit section 102. The first circuit section 100 includes a flip-flop 104 having its one input coupled to the Q output of the flip-flop FF9 and another input coupled to the Q output of the flip-flop FF15, and an AND gate 106 having its one input coupled to an output of the flip-flop 104 and another input coupled to the Q output of the flip-flop FF15. The Q output of the flip-flop FF9 has a frequency of 64 Hz, and the Q output of the flip-flop FF15 has a frequency of 1 Hz. The AND gate 106 thus produces a first pulse train comprising a series of single pulses, each of which is separated by a unit time interval of one second from the succeeding single pulse. The output pulses .phi. are passed through the change-over circuit 21' to the driver citcuit 14' as will be described later. The second circuit section 102 comprises an AND gate 108 and 110. The AND gate 108 has inputs coupled to the Q outputs of the flip-flops FF13 to FF15, and Q outputs of the flip-flops FF16 and FF17, to provide an output .phi..sub.1 as shown in FIG. 12A. The AND gate 110 has inputs coupled to the Q outputs of the flip-flops FF13 and FF14 and Q outputs of the flip-flops FF15 and FF16, to provide an output .phi..sub.2, which is applied to a clock input terminal of a negative going-edge triggered type flip-flop 112. The data terminal of the flip-flop 112 is coupled to the Q output of the flip-flop FF17, to provide an output .phi..sub.3. The output .phi..sub.3 and the Q output of the flip-flop FF17 are applied to an AND gate 114, which provides an output .phi..sub.4. The output .phi..sub.4 is applied to one input of an OR gate 116, to the other input of which is applied the output .phi..sub.1. Thus, the OR gate 116 provides an output .phi..sub.5 which is applied to one input of an AND gate 118 to the other input of which is applied an output .phi..sub.6 of an AND gate 120. The AND gate 120 has inputs coupled to the Q output of the flip-flop FF9 and the Q outputs of the flip-flops FF10 to FF12. AND gate 118 thus generates a second pulse train .phi..sub.7 in response to the outputs .phi..sub.5 and .phi..sub.6. The outputs .phi..sub.5, .phi..sub.6 and .phi..sub.7 are shown in an enlarged scale in FIG. 12B. As best shown in FIG. 12A, the second pulse train .phi..sub.7 is composed of successive groups of pulses, each of said groups of pulses comprising three successively occurring single pulses, with the time from the start of the first pulse in a group of pulses to the end of the last pulse in that group being significantly less than one second, with each group of pulses being separated from the succeeding group by a unit time interval of four seconds, the second pulse train further consisting of a series of single pulses which consist of a single pulse produced after a time interval of three seconds from the commencement of each group of three pulses. The outputs .phi..sub.7 and .phi..sub.8 are applied to the change-over circuit 21'. When an output C of the state sensor 22 is at a low logic level, an AND gate 122 is opened to pass the output .phi..sub.8 to the driver circuit 14'. When, however, the output C goes to a high logic level, an AND gate 126 is opened to pass the output .phi..sub.7 to the driver circuit 14'.
The driver circuit 14' comprises and Gates 128 and 130, a negative going-edge triggered type data type flip-flop 132, and driving inverters 134 and 136. Inputs of the AND gates 128 and 130 are coupled to an output of an OR gate 124 of the change-over circuit 21', and the remaining inputs are coupled to the Q output and Q output of the flip-flop 132, respectively. The data input terminal of the flip-flop 132 is also coupled to the Q output of the flip-flop 132. The set terminal of the flip-flop 132 is coupled to an output of the AND gate 128, and the clock input terminal is coupled to an output of the AND gate 130. The AND gates 128 and 130 generate outputs a and b as shown in FIG. 12A, and the driving inverters 134 and 136 generate driving pulses D.C. having the waveform shown in FIG. 12A. As shown in FIG. 12A, when the output C is at a high logic level, the driving inverters 134 and 136 produce a train of modulated drive pulses whose timing corresponds to that of the second pulse train. The modulated drive pulse train comprises successive groups of three pulses of alternating polarity, 140, 141 and 142, as shown in FIG. 12A, each of these groups being followed by a single pulse 143 after an interval of 3 seconds from the commencement of the group. When these modulated drive pulses are applied to the drive coil 16a of the stepping motor, then the rotor of the stepping motor is rotated through a unit angular displacement, once for each of the drive pulses. Each time the stepping motor rotor is rotated through this unit angular displacement, the seconds hand of the timepiece is advanced clockwise by a step which indicates the passage of one second of time on the timepiece dial. Thus, in response to the train of modulated drive pulses, the seconds hand is advanced in a manner illustrated in FIG. 13. In response to each of the groups of thress successive pulses 140, 141 and 142 shown in FIG. 12A, the seconds hand is advanced clockwise through three successive steps, corresponding to an indication of three seconds on the timepiece dial, within a time of several tens of milliseconds. Three seconds later, the seconds hand is advanced clockwise through one step. Thus, during an interval of four seconds, the seconds hand has been advanced by a correct amount, although the advancement has been performed in an irregular manner. One second later, the seconds hand is again rapidly advanced through three successive clockwise steps, and after three seconds have again elapsed the seconds hand is again advanced clockwise by one step. In this manner, the movement of the seconds hand is modulated in such a way as to be irregular, although no error is introduced into the time displayed by the seconds hand over a long period of time. This irregular movement of the seconds hand is extremely noticeable, and will quickly attract the attention of the user, by reason of its considerable difference from the normal regular movement of the seconds hand of a timepiece, so that the user is quickly made aware of the condition which has been sensed by the state sensor 22.
When the output C is at a low logic level, the driving inverters 134 and 136 produce a normal drive pulse train comprising single drive pulses of alternating polarity, which cause the rotor of the stepping motor to be advanced through a unit angular displacement once per second, so that the seconds hand is advanced by a step indicating one second on the timepiece dial, in each one second unit time interval. The present invention has been described with respect to an embodiment in which the seconds hands are driven by successive groups of three drive pulses with a single drive pulse occurring between each group, in order to provide modulated movement of the seconds hand to indicate some abnormal state of the timepiece.
It will now be appreciated from the foregoing description that in accordance with the present invention the rotatable hands of the timepiece are advanced through unequal intervals during each unit time for thereby providing a modulated display.
While the present invention has been shown and described with reference to particular embodiments in which the seconds hand is adapted to provide a modulated display, it should be noted that in a case where the electronic timepiece includes only a minutes and hours hands the minutes hand may be advanced through unequal intervals in a manner as previously described to provide a modulated display. It should also be understood that one of the rotatable hands may be rotated counterclockwise in a first step and rotated clockwise in second and third steps in a repetitive fashion to provide a modulated display.
Claims
What is claimed is:
1. An electronic timepiece, powered by a battery, comprising: a frequency standard providing a relatively high frequency signal; a frequency divider providing relatively low frequency signals in response to said relatively high frequency signal; a waveform converter including first circuit means responsive to said relatively low frequency signals for providing a first pulse train comprising a first series of single pulses consisting of a single pulse produced at the start of each of a series of first unit time intervals, said first pulse train being generated by said first circuit means during normal operation of the timepiece, and second circuit means for providing a second pulse train comprising successive groups of pulses, each of said groups of pulses comprising a predetermined plural number of pulses, the duration of each of said groups of pulses being less than that of each of said first unit time intervals, one of said groups of pulses being produced at the start of each of a series of second time intervals, each of said second unit time intervals having a duration equal to that of said first unit time interval multiplied by a factor which is equal to said predetermined plural number plus one, said second pulse train further comprising a second series of single pulses consisting of a single pulse produced at a predetermined time following the completion of one of said groups of pulses and prior to the commencement of an immediately succeeding group of pulses; a driver circuit responsive to said first pulse train for providing normal drive pulses and responsive to said second pulse train for providing modulated drive pulses; means for selectively rendering said first circuit means operative while said second circuit means is held inoperative and rendering said first circuit means inoperative while said second circuit means is held operative, in accordance with whether the timepiece is in a normal and an abnormal operating condition respectively; a stepping motor responsive to said normal drive pulses for rotating a rotor thereof through a unit angular displacement at the start of each of said first unit time intervals and responsive to said modulated drive pulses for successively rotating said rotor through said unit angular displacement by a number of times equal to said predetermined plural number at the start of each of said second time unit intervals, and for further rotating said rotor once through said unit angular displacement during each of said second unit time intervals; and display means including at least one hand which is driven by said rotor to be advanced by a single step, which corresponds to one of said first unit time intervals, in response to each rotation of said rotor through said unit angular displacement, whereby said hand is advanced by one step for each of sid first unit time intervals when the timepiece is in said normal operating condition and whereby said hand is advanced by a number of steps equal to said predetermined plural number at the start of each of said second unit time intervala and is further advanced by a single step during each of said second unit time intervals, when the timepiece is in said abnormal operating condition, whereby an indication is givent of said abnormal operating condition.
2. An electronic timepiece according to claim 1, in which said means for selectively rendering said first and second circuit means operative and inoperative comprise sensing means for sensing a normal and abnormal operating condition of the timepiece, to produce an output signal when said abnormal condition is sensed, and changeover circuit means responsive to said output signal for rendering said first circuit means inoperative and said second circuit means operative.
3. An electronic timepiece according to claim 1, in which each of said first unit time intervals has a duration of one second.
4. An electronic timepiece according to claim 3, in which said predetermined plural number has a value of three, whereby said second unit time intervals has a duration of four seconds.
5. An electronic timepiece according to claim 4, in which each pulse of said second series of single pulses is produced after a period of three seconds following the commencement of one of said groups of pulses of the second pulse train.
6. An electronic timepiece according to claim 2, in which said sensing means comprises a battery voltage detector for detecting a drop in voltage of said battery below a predetermined level and for generating said output signal when such a drop is detected.
7. An electronic timepiece according to claim 1, in which said frequency divider produces signals having frequencies of 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz, 1/2 Hz and 1/4 Hz, and wherein said first circuit means comprises a flip-flop which is triggered to a first state in response to said 64 Hz signal and which is triggered to a second state in response to said 1 Hz signal, and a gate circuit having an output of said flip-flop coupled to one input thereof and said 1 Hz signal coupled to another input thereof, for thereby producing said firt pulse train as a series of single pulses .phi..sub.8 having a period of one second and very short pulse width, and wherein said second circuit means comprises a gate circuit coupled to receive said 1/4 Hz signal, said 1/2 Hz signal, said 1 Hz signal, the inverse of said 2 Hz signal and the inverse of said 4 Hz signal at inputs thereof, for thereby producing a signal .phi..sub.1 having a period of 4 Hz, a gate circuit coupled to receive said 4 Hz signal, said 2 Hz signal, the inverse of said 1 Hz signal, and the inverse of said 1/2 Hz signal, at inputs thereof, for thereby producing a signal .phi..sub.2 having a period of 2 seconds, a data-type flip-flop circuit having a data terminal coupled to receive the inverse of said 1/4 Hz signal and a clock terminal coupled to receive said .phi..sub.2 signal, a gate circuit coupled to receive an inverted output from said data-type flip flop and the inverse of said 1/4 Hz signal at input terminals thereof, for thereby producing a signal .phi..sub.4 having a period of 2 seconds, a gate circuit coupled to receive said signals .phi..sub.4 and .phi..sub.1 for thereby producing a signal .phi..sub.5 consisting of a train of relatively long pulses with a period of 4 seconds and with a relatively short pulse occuring at an intermediate point between each pair of said relatively long pulses, a gate circuit coupled to receive said 64 Hz signal, and the inverses of said 32 Hz signal, said 16 Hz signal, said 8 Hz signal at inputs thereof, for thereby producing a signal .phi..sub.6 comprising a train of pulses of very short pulse width and with a period of 1/8 seconds, and a gate circuit coupled to receive said signals .phi..sub.5 and .phi..sub.6 at inputs thereof, for thereby producing a signal .phi..sub.7 comprising successive groups of three pulses of very short pulse width with a period of 4 seconds between each of said groups of three pulses and with a period of 1/8 seconds between successive pulses in a group, and with a single pulse of very short pulse width occuring at a point in time 3 seconds after the initial pulse of each of said groups of three pulses.
8. An electronic timepiece, comprising: a frequency standard providing a relatively high frequency signal; a frequency divider providing a plurality of relatively low frequency signals in response to said relatively high frequency signal; a waveform converter including first circuit means responsive to said relatively low frequency signals for providing a first pulse train comprising a first series of single pulses consisting of a single pulse produced at the start of each of a series of first unit time intervals, said first pulse train being generated by said first circuit means during normal operation of the timepiece, and second circuit means for providing a second pulse train comprising successive groups of pulses, each of said groups of pulses comprising a predetermined plural number of pulses, the duration of each of said groups of pulses being less than that of each of said first unit time intervals, one of said groups of pulses being produced at the start of each of a series of second time intervals, each of said second time intervals having a duration equal to that of said first unit time interval multiplied by a factor which is equal to said predetermined plural number plus one, said second pulse train further comprising a second series of single pulses consiting of a single pulse produced at a predetermined time following the completion of each one of said groups of pulses and prior to the commencement of the immediately succeeding group of pulses; state sensor means for sensing an operating state of the electronic timepiece, and for producing a first output signal when a normal operating state is sensed and producing a second output signal when an abnormal operating state is sensed; a changeover circuit comprising gate circuit means coupled to receive said first pulse train and said second pulse train from said waveform converter, being responsive to said first output signal from said state sensor means for passing said first pulse train to an output terminal thereof and inhibiting passage of said second pulse train, and further responsive to said second output signal from the state sensor means for passing said second pulse train to an output terminal thereof, and for inhibiting passage of said first pulse train; a driver circuit coupled to receive said first pulse train from said changeover circuit means and responsive thereto for producing a train of normal driving pulses corresponding in timing to said first pulse train, and further coupled to receive said second pulse train from said changeover circuit and responsive thereto for producing a train of modulated driving pulses corresponding in timing to said second pulse train; a stepping motor responsive to said normal drive pulses for rotating a rotor thereof through a unit angular displacement at the start of each of said first unit time intervals and responsive to said modulated drive pulses for successively rotating said rotor through said unit angular displacement by a number of times equal to said predetermined plural number at the start of each of said second time unit intervals, and for further rotating said rotor once through said unit angular displacement during each of said second unit time intervals; and display means including at least one hand which is driven by said rotor to be advanced by a single step which indicates the passage of one of said unit time intervals, in response to each rotation of said rotor through said unit angular displacement, whereby said hand is advanced by one step for each of said first unit time intervals when said electronic timepiece is in said normal operating state and whereby said hand is advanced by a number of steps equal to said predetermined plural number at the start of each of said second unit time intervals and is further advanced by a single step during each of said second unit time intervals, when the electronic timepiece is in said abnormal operating state, whereby an indication of said abnormal operating state is given.