Delayed Line for Sense Amplifier Pulse

This invention relates to an integrated logic circuit, more specifically to an integrated logic circuit including a pulse generator means capable of reducing the influence of signal delay where wiring which inevitably delays signals exists in the integrated logic circuit.

In general, a dynamic memory system or synchronous static memory system has an integrated logic circuit including a memory cell array. When a word line of the memory cell array is activated, data stored in the memory cell is read out onto a data line. The read data is transmitted to a sense amplifier connected to the data line, and then detected and amplified. In operating the sense amplifier at a high speed without wrong operation, the phase difference between a word line driving pulse (first drive pulse) for activating the word line and a drive pulse (second drive pulse) for driving the sense amplifier is a question of vital interest. In other words, there exists, as a requisite for stable operation of the dynamic memory system, a requirement that the sense amplifier be supplied with the second drive pulse after the information read out from the memory cell is transferred to the sense amplifier by means of the data line. In order to fulfill such requirement, prior art systems have been employing a method as mentioned later. According to such method, however, the operating speed of the sense amplifier cannot be increased to a satisfactory degree, and the sense amplifier would cause malfunction if the supply voltage is raised for a speed-up. These defects have been pointed out as problems to be solved. This invention provides a new solution to such problems. In order to facilitate the understanding of this invention, there will now be described a prior art semiconductor memory system with reference to FIGS. 1 to 7.

FIG. 1 is a block diagram showing a typical example of a conventional dynamic-type RAM (random access memory) system. In this drawing, numeral 10 designates a main body of the memory system including a memory cell array 5 and peripheral circuits coupled thereto. The body 10 is controlled by output pulses from a pulse generator 9. External row and column address signals A.sub.R and A.sub.C are amplified by a row address buffer circuit 1 and a column address buffer circuit 2 respectively. Outputs A or A of these buffer circuits select outputs of a row address decoder 3 and a column address decoder 4 respectively. In data reading, data stored in memory cells connected to a row of the memory cell array 5 which is designated by the output of the row address decoder 3 are amplified by a sense amplifier 6. Among the amplifier outputs, only the datum of a memory cell selected by the column address decoder 4 is delivered as an output Dout to the outside through a data output circuit 7. Data stored in those memory cells which belong to the selected row and nonselected columns are amplified by the sense amplifier 6, rewritten in their corresponding memory cells or refreshed. In writing data in the memory cell array 5, on the other hand, an input data Din is written through an input circuit 8 in a memory cell belonging to the designated row and column. The pulse generator 9, which receives a control pulse .phi..sub.c as an input, provides clock pulses, such as chip selection pulses, clock pulses for driving the address buffer circuits 1 and 2, decoders 3 and 4, sense amplifier 6, input circuit 8, and the output circuit 7. In FIG. 1, for example, the pulse generator 9 produces .phi..sub.p (precharge pulse) and .phi..sub.1 to .phi..sub.5, which are to be supplied to predetermined devices of the memory system body 10.

FIG. 2 shows an example of a circuit diagram corresponding to the drawing of FIG. 1. In FIG. 2, the memory cell array is denoted by numeral 5, and a 1-transistor/cell-type memory cell consisting of an MOS transistor 12 and a capacitor C.sub.S for storing a single information is used for each of the memory cells 11. For each of the address buffer circuits 1 and 2 (FIG. 1), there is used such a circuit as disclosed in U.S. Pat. No. 3,902,082 and shown in the drawing of FIG. 3 hereof. In this circuit, V.sub.DD and V.sub.SS are first and second power sources respectively, and .phi..sub.p is a pulse for precharge. When the row address input A.sub.R or column address input A.sub.C is applied to the gate of an MOS transistor 17, a real address signal A and a supplementary address signal A are produced in synchronism with the clock pulse .phi..sub.2. That is, nodes 15 and 16 in the states charged to a level "1" or V.sub.DD level, since MOS transistors 13 and 14 are turned on while the level of the precharge pulse .phi..sub.p is "1". When the level of the clock pulse .phi..sub.1 becomes "1" while the address input A.sub.R or A.sub.C is at "1", MOS transistors 17 and 18 are turned on, so that only the charges on the node 15 are discharged. When, in this state, the clock pulse .phi..sub.2 gets the level "1", MOS transistors 19 and 20 are turned on, while MOS transistors 21 and 22 are turned off, so that the real and supplementary address signals A and A become "1" and "0" respectively. While the address input A.sub.R or A.sub.C is at "0", on the other hand, the MOS transistor 17 is off, so that the nodes 15 and 16 maintain the level "1". When the level of the clock pulse .phi..sub.2 then becomes "1", A at a relatively high voltage and A at a relatively low voltage appear at the output although the transistors 19 to 22 are all on. The reason for this is that the conductance of the MOS transistor 21 is set to be larger than that of the MOS transistor 20 and that the conductance of the MOS transistor 19 is set to be smaller than that of the MOS transistor 22. When the voltage of A exceeds threshold voltage Vth of an MOS transistor 23, the MOS transistor 23 is turned on, and the MOS transistors 19 and 20 are turned off, thereby reducing A definitely to the level "0". Meanwhile, the potential of A gradually increases to the level "1". Where the memory array 5 is so constructed as to have a capacity of 16 K bits, the sum of the numbers of the row address buffer circuits 1 and the column address buffer circuits 2 may be 14, for example.

The row address decoder 3 as shown in FIG. 2 is connected to, for example, one end of each corresponding word line 25. In this decoder 3, seven outputs A or A of the row address buffer circuit 1 (FIG. 3) are supplied respectively to the gates of MOS transistors 24.sub.1 to 24.sub.7, which are connected in parallel with the gate of an MOS transistor 26 coupled to the one end of the word line 25. Further, the gate of the transistor 26 is connected with an MOS transistor 27 for precharging such gate, while the gate of the transistor 27 is supplied with the precharge pulse .phi..sub.p.

The column address decoder 4 as shown in FIG. 2 is connected to the gate of each data line selection MOS transistor 30 which is connected to, for example, one end of each corresponding data line 29. The address decoder 4 includes MOS transistors 28.sub.1 to 28.sub.7 with the drains connected in common and the sources coupled to the second power source V.sub.SS, an MOS transistor 32 with the source connected to the common drains and the drain coupled to the first power source V.sub.DD, and a drive transistor 31 with the source connected to the gate of the transistor 30 and the drain supplied with the clock pulse .phi..sub.5. The gates of the transistors 28.sub.1 to 28.sub.7 are supplied respectively with the outputs A or A of the seven column address buffer circuits 2 as shown in FIG. 3. Whereas the drain of the transistor 26 of the row address decoder 3 is supplied with the drive pulse .phi..sub.3 of the word line 25, the clock pulse .phi..sub.5 is applied to the drain of the transistor 31 of the column address decoder 4.

The sense amplifier 6 as shown in FIG. 2 is disclosed in the specification of U.S. Pat. No. 3,774,176. The amplifier 6 is a circuit to detect and amplify fine changes of voltage on the data line 29 that is supplied to a node a. That is, the voltage read out onto the data line 29 correspondingly to the stored data "0" or "1" in the memory cell 11 is amplified by properly selecting the ratio of a capacitance of a stray capacitor C.sub.D of the data line 29 to that of a capacitor C.sub.D ' of the sense amplifier 6. More specifically, MOS transistors 33 and 34 which receive the precharge pulse .phi..sub.p as the gate input charge the capacitors C.sub.D and C.sub.D ', while an MOS transistor 35 which also receives the precharge pulse .phi..sub.p as the gate input maintains output ends a and b at the same potential. MOS transistors 36 and 37 constitute a flip-flop. If one of the memory cells 11 in which the stored data in the capacitor C.sub. S is "0" is selected and the MOS transistor 12 is turned on, the voltage of the capacitor C.sub.D drops a bit. At this point of time, when the drive pulse .phi..sub.4 of the sense amplifier 6 is supplied to the gate of a transistor 38 to turn on the transistor 38, the potential at the output point a of the sense amplifier 6 drops to the level "0". On the other hand, if a memory cell 11 in which the stored data in the capacitor C.sub.S is "1" is selected, then the potential at the output point a of the sense amplifier 6 is maintained at the level "1". This is done because the capacitors C.sub.D and C.sub.D ' are so set that the discharge of the capacitor C.sub.D ' may be finished ahead of the discharge of the capacitor C.sub.D.

An MOS transistor 39 as shown in FIG. 2, which receive the precharge pulse .phi..sub.p as the gate input, tends to precharge an input-output line 40.

FIG. 4 shows a clock pulse generator circuit 40 built in the pulse generator 9 as shown in FIG. 1. This circuit 40 is a delay circuit composed of MOS transistors which is disclosed in the specification of U.S. Pat. No. 3,898,479. In the circuit 40, a clock pulse .phi..sub.n-1 (n=1,2, . . . , 5) is applied to the gates of MOS transistors 49 and 48 to provide an output pulse .phi..sub.n after a fixed time. By cascade connecting five such circuits 40 and applying the control pulse .phi..sub.c (FIG. 1) to a first-stage input gate, the internal clock pulses .phi..sub.1 to .phi..sub.5 of the memory system are obtained as outputs of the first to fifth circuits 40, respectively. As for the aforementioned generator circuit for the precharge pulse .phi..sub.p, which produces the precharge pulse .phi..sub.p by means of the control pulse .phi..sub.c, it will later be described in detail. In the circuit 40 of FIG. 4, MOS transistors 41 to 44 are on, MOS transistors 45 and 46 are off, and an MOS transistor 47 is on while the level of the precharge pulse .phi..sub.p is "1". When the levels of the pulses .phi..sub.p and .phi..sub.n-1 become "0" and "1" respectively, an MOS transistor 48 is turned on to charge a capacitor 50, and then the transistor 46 is turned on. Since conductance gm of the transistor 49 is set smaller than that of the transistor 48, the transistor 45 is turned on with a time lag from a point of time when the transistor 46 is turned on, and then the transistor 47 is turned off. Before the transistor 47 is turned off, an output end O.sub.1 is at a potential determined by the conductance ratio between the transistors 46 and 47. When the transistor 47 is turned off, however, the output end O.sub.1 is charged with the first supply voltage V.sub.DD, so that the gate potential of the transistor 46 is pulled up under the influence of the capacitor 50 to a level above the supply voltage V.sub.DD. Accordingly, the transistors 46 and 51 operate in a triode region, and the output at an output end O.sub.2 attains the level "1" corresponding to the voltage V.sub.DD. The "1"-level output serves as an input for the next-state circuit 40. When the precharge clock pulse .phi..sub.p resumes the level "1", 100.sub.n (n=1,2 . . . , 5) is reduced to the level "0". Although the clock pulse .phi..sub.n used in FIG. 4 is usually produced from the output end O.sub.2 at the junction of the transistors 44 and 51, it may alternatively be one which is generated from the output end O.sub.1 at the junction of the transistors 46 and 47.

An example of the generator circuit for the precharge pulse .phi..sub.p, which is contained in the pulse generator 9 (FIG. 1), is shown in FIG. 5 and denoted by numeral 60. Namely, a delay circuit 55 is connected to the output end of an inverter formed of an MOS transistor 52 to receive the external control pulse .phi..sub.c as its gate input and load MOS transistors 53 and 54, and thus the output of the delay circuit 55 is taken out as the precharge pulse .phi..sub.p. The delay circuit 55 is illustrated in detail within a chain line in FIG. 6. In the circuit 55, the output of the inverter is supplied to the gates of the transistors 48 and 49 of the circuit 40 of FIG. 4, .phi..sub.c is supplied to the gates of the transistors 41, 42, 43 and 44, and .phi..sub.p is taken out from the output end O.sub.2. Therefore, elements in FIG. 6 corresponding to the elements in FIG. 4 are denoted by like reference numerals but with primes, and detailed description of such elements is omitted. The circuit 55 of FIG. 5 is not limited to the precise circuit arrangements shown in FIG. 6.

FIGS. 7A to 7L are timing charts for illustrating the operations of the circuits as shown in FIGS. 1 and 2. When the level of the external control pulse .phi..sub.c (FIG. 7A) becomes "1" (active cycle), the precharge pulse .phi..sub.p (FIG. 7B) is reduced to the level "0" with a short time delay, and then the internal clock pulses .phi..sub.1 to .phi..sub.5 are produced one after another following the precharge pulse (FIGS. 7C to 7G). The address output A or A is delivered in synchronism with the clock pulse .phi..sub.2 (FIG. 7H, FIG. 3). The decoders 3 and 4, which have been charged to the level "1" by the precharge pulse, are all discharged to the level "0", excepting ones for a selected row and a selected column. When the level of the drive pulse .phi..sub.3 for the word lines 25 becomes "1" (FIG. 7E), only a word line 25 for the selected row gets the level "1", the other word lines 25 for the nonselected rows remaining "0". When the data stored in the capacitor C.sub.S of a memory cell belonging to the selected word line 25 is at "0", for example, the charges on the capacitor C.sub.D are distributed according to the ratio between the capacitor C.sub. S of the memory cell and the capacity C.sub.D of the data line 29 (here C.sub.D >>C.sub.S), so that the voltage at the output end a of the sense amplifier 6 is slightly reduced (57 in FIG. 7K). When the level of the drive pulse .phi..sub.4 for the sense amplifier 6 becomes "1" (FIG. 7E) after the data of the cell 11 is fully transferred to the output point a, that is, after the fine voltage at the output point a is produced, the sense amplifier 6 is driven to discharge the data line 29 to the level "0" (FIG. 7K). Subsequently, when the clock pulse .phi..sub.5 is supplied to the column address decoder 4, only the data of the data line 29 belonging to the selected column (FIG. 7L) is read out to the outside through the input-output line 40 and the output circuit 7. In writing data in the cell, input data is written in the selected cell through the input circuit 8, input-output line 40 and data line 29. At time of such data writing, the level of the drive pulse .phi..sub.4 for the sense amplifier 6 is returned to "0" (FIG. 7F), so that there will be created no DC path between the first and second power sources V.sub.DD and V.sub.SS through the sense amplifier 6. When the level of the external control pulse .phi..sub.c becomes "0" (FIG. 7A), the precharge pulse .phi..sub.p attains the level "1" (FIG. 7B), and the output pulses .phi..sub.1 to .phi..sub.5 of the pulse generator 9 and the outputs of the address buffer circuits 1 and 2 return to the stand-by state or level "0". At the same time, the data line 29, input-output line 40 and address decoders 3 and 4 are charged to the level "1" for a subsequent active cycle.

It has already been mentioned, as a condition for stable or proper operation of the above-described dynamic memory system, that the pulse .phi..sub.4 must be supplied after the information read out from the memory cell 11 is transferred to the output point a of the sense amplifier 6 by means of the data line 29. For the fulfillment of such requirement, the signal delay on the word line 25 or data line 29 is matter of importance, since transmitted signals will inevitably be delayed on the word or data line 25 or 29. Now there will be described examples of such signal delay.

In manufacturing a semiconductor memory, the silicon gate process is usually employed. According to this process, the word line 25 and the data line 29 of the memory cell array 5 are required to cross at right angles. To attain this, there may be given two methods to be employed. In a first method, the word and data lines 25 and 29 are formed of aluminum wiring and a diffusion layer respectively. In a second method, on the other hand, the word and data lines 25 and 29 are formed of a polysilicon layer and aluminum wiring respectively. However, the layer resistances of the diffusion layer and polysilicon layer are large; approximately 10 to 50 .OMEGA./.quadrature. for the former and 30 to 100 .OMEGA./.quadrature. for the latter when manufacturing an N-channel MOS memory array, for example. In a large-capacity memory with a number of memory cells 11 connected to the word and data lines 25 and 29, the stray capacity and resistance of the word or data line are large, so that the delay times of signals or data transmitted by means of such lines are naturally long. In forming a 16K-bit RAM, for example, each of the word and data lines is connected with 128 memory cells (64 memory cells connected to each side of each data line, when using a balanced sense amplifier), so that the total resistance of each data line is approximatey 4 to 15 k.OMEGA. and the stray capacity ranges from 1 to 2 pF where the data line 25 is formed of the diffusion layer. Accordingly, the time constant required for the data propagation of the data line is about 4 to 30 nsec. If the memory cell 11 farthest from the sense amplifier 6 is selected, the time required for the data read out from such cell to reach the output end a of the sense amplifier by means of the data line 29 will be prolonged. If the word line 25 is formed of the polysilicon layer, then the capacity of load connected to the word line and the layer resistance of the word line are increased as compared with the data line, so that additionally long time would be required to activate the word line. In consequence, more time is required for the data of the cell 11 to reach the output point a of the sense amplifier after the pulse .phi..sub.3 is applied to the decoder 3.

When using the silicon gate process, as described above, the pulse generator 9 must be designed with allowance for a time interval between the drive pulse .phi..sub.3 for the word line 25 and the drive pulse .phi..sub.4 for the sense amplifier 6, in consideration of the signal delay time on the word line 25 or data line 29 besides the delay time required for the operation of the MOS transistor 12 of the memory cell 11. Generally, the delay time of the output .phi..sub.n compared with the input .phi..sub.n-1 of the circuit 40 as shown in FIG. 4 may be adjusted by changing the conductance gm of the transistor 49 or the capacitance of a capacitor 61. In the prior art system, therefore, such conductance or capacitance has been adjusted taking account of the sum of the delay time required for the transfer transistor 12 of the memory cell 11 and the signal delay time on the word or data line 25 or 29. Since the transfer transistor 12 has the same construction with the transistors of the clock pulse generator circuit 40 (FIG. 4), the delay time required for the operation thereof may be automatically adjusted if the supply voltage V.sub.DD or device parameters (e.g., gate oxide film, channel length, etc.) are changed. Thus, the time interval between the pulses .phi..sub.3 and .phi..sub.4 may be determined by the conventional method without involving any substantial trouble. Caused without regard to the operations of the transistors, however, the signal delay time on the word or data line 25 or 29 is subject to the influences of the variations in the device parameters and supply voltage. In order to avoid such influences, the delay time of the pulse .phi..sub.4 compared with the pulse .phi..sub.3 has conventionally been determined as follows. That is, supposing that the layer resistance of the diffusion layer (data line) or polysilicon layer (word line) is within a fixed range, the phase difference between the pulses .phi..sub.3 and .phi..sub.4 has been so determined by the prior art method (adjustment of the conductance of the transistor 49 and the capacitance of the capacitor 61 as shown in FIG. 4) as to secure stable operation of the sense amplifier 6, even if the layer resistance takes its upper limit value or the signal delay time on the word or data line is maximized, and if the supply voltage V.sub.DD is maximized within its allowable range or the time interval between the clock pulses .phi..sub.3 and .phi..sub.4 is minimized.

It has been found, however, that the aforesaid prior art method is subject to some defects as follows:

(1) Since there exist fluctuations and variations in the supply voltage and device parameters (e.g., gate oxide film, channel length, etc.), it is necessary to make allowance for the data propagation delay time on the word line 25 or data line 29 to operate sense amplifier 6 without malfunction. By doing this, the operating speed of the sense amplifier 6 or the memory system may be reduced.

(2) When the layer resistance of the polysilicon layer, for example, for the word line 25 or the diffusion layer, for example, for the data line 29 is large and the supply voltage is increased, wrong operation of the sense amplifier 6 will be caused if the anticipated propagation delay time as mentioned in item (1) cannot compensate for the increase of the layer resistance.

(3) When the layer resistance is small and the supply voltage is lowered, in contrast with the case of item (2), the propagation delay time as mentioned in item (1) is given too much allowance, so that the operating speed of the sense amplifier 6 is reduced.

Accordingly, the object of this invention is to provide an integrated logic circuit including a logic circuit, an output selection circuit for the logic circuit and a sense amplifier circuit to detect selected output, in which the integrated logic circuit further includes a pulse generator circuit capable of preventing wrong operation of the sense amplifier circuit and increasing the operating speed in spite of variations in parameters of devices constituting the integrated circuit as well as fluctuations in supply voltage for the integrated circuit.

The integrated circuit of this invention comprises a logic circuit, an output selection circuit coupled to the logic circuit for obtaining a desired output from the logic circuit, a detector for detecting the output of the logic circuit, and a pulse supply means for supplying first and second drive pulses at least to the output selection circuit and the detector respectively; the pulse supply means including a delay line receiving the first drive pulse as an input and a pulse generator composed of MOS transistors which receives as an input a delayed pulse from the delay line and delivers the second drive pulse, the delay line exhibiting a signal delay characteristic substantially equivalent to that of a signal transmission line provided between the selection circuit and the detector.

According to an embodiment of the invention, there is provided an integrated circuit which comprises a plurality of word lines formed of polysilicon layers, a plurality of data lines formed of aluminum layers, a plurality of memory cells coupled to the word and data lines at the intersecting points thereof, a plurality of address decoders coupled to the respective word lines and supplying first drive pulse to the memory cells coupled to the word lines, a plurality of sense amplifiers coupled to the respective data lines and detecting signals read out from the memory cells coupled to the data lines when the second drive pulse is supplied, and a pulse supply means for supplying first and second drive pulses at least to the address decoders and the sense amplifiers respectively. The pulse supply means includes a delay line formed of a polysilicon layer which receives the first drive pulse as an input and a pulse generator circuit composed of MOS transistors which receives as an input a delayed pulse from the delay line and delivers the second drive pulse, the delay line exhibiting a signal delay characteristic substantially equivalent to that of the word lines.

According to the above-mentioned embodiment of the invention, an address decoder is connected with a memory cell by means of a word line formed of a polysilicon layer, while the memory cell is connected with a sense amplifier by means of a data line formed of an aluminum layer. The signal delay between the address decoder and sense amplifier, therefore, depends on the signal delay on the word line. Hereupon, the delay line in the pulse generator means of the invention is so formed as to have the signal delay characteristic substantially equivalent to that of the word line. By way of example, the cross-sectional area and overall length of the delay line are substantially equal to those of the word line, and a capacity belonging to the delay line is substantially as large as a capacity attached to the word line. Accordingly, if the signal delay time on the word line is changed due to variations in parameters of devices constituting the integrated circuit, the signal delay time on the delay line in the pulse generator means will also vary in accordance with such changes of the signal delay time on the word line. Thus, it will be very easy to supply the second drive pulse to the sense amplifier after the signal from the memory cell has reached the sense amplifier, eliminating the aforementioned defects of the prior art system.

FIG. 1 is a block diagram showing an example of the configuration of a prior art system;

FIG. 2 is a detail drawing of a circuit corresponding to the diagram of FIG. 1;

FIG. 3 is a detail drawing showing an example of an address buffer circuit as shown in FIG. 1;

FIG. 4 is a detail drawing of a pulse generator circuit included in a pulse generator as shown in FIG. 1;

FIG. 5 is a block diagram of a precharge pulse generator included in the pulse generator as shown in FIG. 1;

FIG. 6 is a detail drawing of the precharge pulse generator of FIG. 5;

FIG. 7 including 7A-7L, is a timing chart illustrating drive pulses for the system as shown in FIGS. 1 and 2.

FIG. 8 is a block diagram showing an embodiment of this invention;

FIG. 9 is a block diagram showing an example of a pulse generator means as shown in FIG. 8, including a partial detail circuit diagram; and

FIG. 10 is a block diagram showing another example of the pulse generator means of FIG. 8, including a partial detail circuit diagram.

In FIG. 8, a circuit designated by numeral 10 is the same as the circuit 10 of FIG. 1, so that it will not further be described here to avoid repetition. Like the circuit 9 of FIG. 1, a circuit 9a as shown in FIG. 8 is supplied with the external control pulse .phi..sub.c as an input and delivers the precharge pulse .phi..sub.p, drive pulses .phi..sub.1 to .phi..sub.5, etc., although the circuit 9a differs from the circuit 9 in the internal circuit arrangement. Therefore, only the pulse generator 9a will be described hereinafter.

Referring now to FIG. 9, the external control pulse .phi..sub.c is supplied to the precharge pulse generator 60 as shown in FIG. 6, from which the precharge pulse .phi..sub.p may be obtained as already mentioned. The drive pulse .phi..sub.1 is obtained from a first-stage pulse generator circuit 40 as shown in FIG. 4 by supplying the external control pulse .phi..sub.c to the gates of the transistors 48 and 49 of the first-stage circuit 40. Likewise, the drive pulse .phi..sub.2 is obtained by supplying the drive pulse .phi..sub.1 to the gates of the transistors 48 and 49 of a second-stage pulse generator circuit 40, and the drive pulse .phi..sub.3 is obtained by supplying the drive pulse .phi..sub.2 to the gates of the transistors 48 and 49 of a third-stage pulse generator circuit 40. A fourth-stage pulse generator circuit 40a is formed of a delay line 71 and pulse generator circuit 40b. The drive pulse .phi..sub.3 (or first drive pulse) is applied to the delay line 71, and the delayed pulse is supplied to the gates of the transistors 48 and 49 of the circuit 40b. Although having the same configuration of the circuit 40, the circuit 40b is so constructed that the output .phi..sub.n (.phi..sub.4 for this embodiment) is taken out from the junction of the transistors 46 and 47, so that the transistors 44 and 51 are omitted in FIG. 9. The output .phi..sub.4 (or second drive pulse) of the pulse generator circuit 40b is supplied to the gates of the transistors 48 and 49 of a fifth-stage pulse generator circuit 40 (FIG. 4), and the drive pulse .phi..sub.5 is taken out from the fifth-stage circuit. As for the pulses .phi..sub.p and .phi..sub.1 to .phi..sub.5 that are supplied to the memory 10, they have already been described with reference to FIGS. 2 and 7. Omitting detailed description of such pulses and referring to FIG. 2, therefore, there will now be explained only how the drive pulses .phi..sub.3 (first pulse) and .phi..sub.4 (second pulse) are supplied.

Hereupon, let us suppose a case where the word lines 25 (FIG. 2) and the data lines 29 are formed of polysilicon and aluminum layers respectively. In this case, the delay line 71 is formed in the LSI (large-scale integrated) circuit under the same forming conditions for the word lines 25. For example, the delay line 71 may be so formed as to have substantially the same cross section and overall length as those of the word lines 25 and that a capacity belonging to the delay line 71 may be formed substantially as large as a capacity attached to a word line 25. Even though the word line 25 is rectilinear, the delay line 71 may be bent but with the same length. Moreover, it is to be understood that the delay line 71 may be so designed as to provide a little longer signal delay time, as well as greater length and load capacity, as compared with the word line 25.

By providing the aforesaid delay line 71, the drive pulse .phi..sub.3 for the word lines 25 (FIG. 2) is supplied to the transistors 48 and 49 of the pulse generator 40b at the same time when the pulse .phi..sub.3 is propagated to the farthest memory cell 11 from the decoder 3, thereby producing the sense amplifier driving pulse .phi..sub.4. Accordingly, the time interval between the pulses .phi..sub.3 and .phi..sub.4 is equal to the sum of the time interval between the input and output pulses of the pulse generator 40b itself and the signal delay time on the word line 25. The signal delay time at the pulse generator 40b itself needs only to be coincident with the response time of the data transfer transistor 12 of the memory cell 11, and the change of the signal delay time on the word line 25 may be automatically adjusted by the delay line 71 itself. Namely, if the layer resistance, etc. of the word line (formed of a polysilicon layer) changes with variations of device parameters to vary the signal delay time on the word line 25, the delay time of the delay line 71 will also vary in accordance with such variation. Accordingly, the phase difference between the pulses .phi..sub.3 and .phi..sub.4 is automatically adjusted so that the sense amplifier 6 may operate under the optimum conditions. It will be seen from the above description that the aforementioned defects (items (1), (2) and (3)) of the prior art system, which have been requiring remedies, may be eliminated according to this invention.

Now let us suppose a case where the word and data lines 25 and 29 are formed of aluminum and diffusion layers respectively. Since, in this case, the signal delay time on the word line 25 becomes substantially zero because the resistance of the aluminum line is very small, so that consideration needs to be given only to the signal delay time on the data line 29. That is, in this case, it is necessary only that the delay line 71 be formed of the same diffusion layer of the data line 29 so that the delay characteristic of the delay line 71 may be substantially the same as that of the data line 29.

FIG. 10 shows another example of the pulse generator means, in which the delayed pulse from the delay line 71 is supplied only to the gate of the transistor 49 of the pulse generator circuit 40b. This arouses no special problem because the delay time of the output pulse .phi..sub.4 at the pulse generator 40a as compared with the input pulse .phi..sub.3 is determined on the side including the transistors 49 and 41 and the capacitor 61.

Although in the above embodiments the logic circuit is described as a dynamic memory cell array, this invention may be applied also to such a memory system that a memory cell array operates statically and peripheral circuits connected to the array operate in synchronism with the external control pulse .phi..sub.c. Moreover, the logic circuit is not limited to the memory cell array, but may be applied also to a circuit which, having a relatively long wiring formed of a diffusion layer or polysilicon layer, operates when supplied with first and second pulses between which a phase difference needs to exist, and such that the phase difference between the pulses must be adjusted by the signal delay time of the wiring. Although the embodiments as shown in FIGS. 9 and 10 are explained, to facilitate the understanding of the invention, as such that the pulses .phi..sub.p, .phi..sub.1, .phi..sub.2 and .phi..sub.5, besides the first and second pulses .phi..sub.3 and .phi..sub.4, may be produced from the pulse generator means, the pulses are not limited to that precise number. Furthermore, the arrangements of the pulse generator circuit formed of the MOS tansistors are not limited to those illustrated.