Circuit Arrangement for the Control of a Digitally Settable Load

My present invention relates to a circuit arrangement for controlling, preferably by hand, a digitally settable load such as a frequency synthesizer or a voltage selector, used for example in a radio transmitter or receiver or in an electronic test circuit, which is to be adjustable in very small increments.

A digitally settable frequency synthesizer disclosed in commonly owned U.S. Pat. No. 3,453,542 has a multiplicity of decadic stages associated with respective selector switches. While such individual stage selectors enable the rapid establishment of a desired frequency, they are less convenient for scanning a chosen frequency range since several selectors must be concurrently displaced upon the occurrence of a decimal carry (e.g. upon a switchover from . . .099 to . . .100 Hz). An analogous problem exists in the decadic setting of voltages or other parameters such as gain or bandwidth, for example.

In German Pat. No. 977,780 there is described a superheterodyning receiver in which a ring counter is settable by pulses that are manually generated by the rotation of a control knob. The pulse generator comprises a set of mechanical switches which discriminate, by their sequence of actuation, between the two directions of rotation to drive the counter either forward or backward, at a rate of one step per knob revolution.

The general object of my present invention is to provide a compact, purely electronic system for translating, without the use of wear-prone mechanical elements, a simple motion of a reversible control element into a succession of signal combinations representative of progressively varying digital values to be used for the setting of a load of the type referred to above.

A more particular object is to provide means in such a system for facilitating a rapid presetting or coarse tuning, followed by a fine adjustment, by making the switching rate a nonlinear--preferably exponential--function of the control motion.

In accordance with my present invention, I provide a direct-current generator such as a tachometer which is operable to produce a driving voltage of variable polarity and magnitude, as by rotating a knob carried on the generator shaft. A discriminating network connected to that generator emits one of two control signals upon detecting a driving voltage of a respective polarity exceeding (in absolute magnitude) a corresponding, preferably adjustable threshold. A pulse-generating unit, inserted between the discriminating network and a reversible pulse counter, respectively translates the two control signals into forward-stepping and reverse-stepping pulses for that counter which has a plurality of stage outputs connectable to the load, e.g. to corresponding stage inputs of a digital frequency synthesizer of the type described in the aforementioned U.S. Pat. No. 3,453,542.

Pursuant to a more specific feature of my invention, the discriminating network includes a storage capacitor which is chargeable by the driving voltage in the output of the d-c generator and is dischargeable by a feedback connection from the output of that network whose stepping pulses (which are of constant amplitude) progressively deplete the capacitor charge.

In order to facilitate fast switching with only a moderate increase in the speed of shaft rotation, the storage capacitor advantageously forms part of an input circuit of an operational amplifier including nonlinear impedance means, specifically a pair of antiparallel diodes which could be inserted either in a charging path of the capacitor or in a voltage divider serving to bias the inverting input of that amplifier whose noninverting input receives the driving voltage from the d-c generator. The current through these diodes varies substantially exponentially with the voltage difference .DELTA.V applied thereacross, and so does the output voltage of the differential amplifier which is fed in parallel to a pair of comparators forming part of the discriminating network. Each of these comparators has a first input connected to the amplifier output and a second input connected to a supply of reference potential whose magnitude determines the recurrence frequency or cadence f.sub.p of the stepping pulses. Thus, the pulse cadence f.sub.p generally conforms to the equation f.sub.p =e.sup.k..DELTA.V where k is a factor depending on the reference potential.

The above and other features of my invention wil now be described in detail with reference to the accompanying drawing in which:

FIG. 1 is an overall circuit diagram of a control system embodying my invention; and

FIGS. 2 and 3 show respective modifications of some of the circuitry of FIG. 1.

In FIG. 1 I have shown a rotatable control knob 1 fixedly mounted on the shaft of a direct-current generator 2, designed as a tachometer, whose output voltage is of one or the other polarity--depending on the direction of knob rotation--and of a magnitude proportional to the rotary speed. A storage capacitor 4 is connected, in series with a resistor 3, across the generator 2 to be charged by the driving voltage developed by the latter. Charging resistor 3 is shunted by a pair of antiparallel diodes 33, 34 which should be omitted if a substantially linear relationship between knob speed and pulse cadence is desired.

Capacitor 4, whose ungrounded terminal is connected to a noninverting input of an operational amplifier 5, is shunted by two pairs of series-connected diodes 6, 7 and 8, 9 which are also in antiparallel relationship with each other. Amplifier 5 has its inverting input connected, in the usual manner, to a tap on a voltage divider inserted between its output and a point of fixed potential (ground), this divider consisting of two series resistors 25, 26.

Two comparators 10 and 11, also designed as operational amplifiers, respectively respond to positive and negative charges of capacitor 4. Comparator 10 has an inverting input tied to the slider of a potentiometer 12 which is connected between ground and a point of positive voltage +V; comparator 11 has a noninverting input tied to the slider of a potentiometer 13 which is connected between ground and a point of negative voltage -V. The noninverting input of comparator 10 and the inverting input of comparator 11 are connected in parallel to the output of amplifier 5. Thus, comparator 10 conducts to emit a first signal voltage when amplifier 5 has a positive output voltage which exceeds the biasing voltage supplied by potentiometer 12; analogously, comparator 11 conducts to emit a second signal voltage when the amplifier has a negative output voltage surpassing in its absolute value the biasing voltage supplied by potentiometer 13. Either of these signal voltages, assumed to be of positive polarity, is passed by an OR gate 14 to an input terminal 28 of a pulse generator--here a Schmitt trigger 15--whose output terminal 27 is tied to respective inputs of a NAND gate 18 and an AND gate 19. NAND gate 18 has another input connected to the output of comparator 10; similarly, AND gate 19 has another input connected to the output of comparator 11. Gate 18 works through a coupling condenser 20 into the junction of diodes 6 and 7 whereas gate 19 works through a coupling condenser 21 into the junction of diodes 8 and 9.

Comparators 10 and 11 also work, respectively, into two control inputs F (forward) and R (reverse) of an up/down pulse counter 16 of BCD type displaying its count in decadic form; in the present instance, the reading of the counter (5,831,742 MHz) is the same as that chosen by way of example for the output of the frequency synthesizer disclosed in U.S. Pat. No. 3,453,542 referred to above. Such a frequency synthesizer 17 is shown connected to the several stage outputs of counter 16 which carry the binary configurations corresponding to digits "3", "1" and "7"; these 4-bit words are decoded within synthesizer 17 and applied to respective stage inputs thereof as taught in that prior patent. Synthesizer 17 receives a reference frequencz (e.g. of 0.1 MHz) from an oscillator 35.

When the knob 1 is manually rotated in one direction or the other, the charge accumulating on capacitor 4 drives the output of amplifier 5 either positive or negative. When the threshold of the corresponding comparator 10 or 11 has been reached, Schmitt trigger 15 is activated by way of OR gate 14 and steps the counter 16 forward or backward, depending on whether control input F or R is energized by comparator 10 or 11. The stepping pulses appearing on terminal 27 are also delivered to gates 18 and 19; in the presence of a positive charge, comparator 10 enables the blocking of the previously conducting NAND gate 18 by these stepping pulses so that condenser 20 feeds back a negative pulse via diode 6 to capacitor 4, whereas in the presence of a negative charge the previously nonconducting AND gate 19 is unblocked by comparator 11 to pass the stepping pulses so that condenser 21 feeds back a positive pulse via diode 8. In either case, the charge present on capacitor 4 is diminished or canceled by these feedback pulses so that the stepping of counter 16 is halted as soon as the rotation of knob 1 is stopped. Coupling condenser 20 or 21 is discharged, after the disappearance of any stepping pulse transmitted to it, via diode 7 or 9, respectively.

With diodes 33 and 34 included in the circuit, the current flowing therethrough increases substantially exponentially with the voltage difference .DELTA.V existing thereacross. An accelerated rotation of knob 1, therefore, causes a rapid recharging of capacitor 4 and a correspondingly high pulse rate. A similar result can be obtained if, as illustrated in FIG. 2, these diodes are connected in shunt with biasing resistor 25.

In FIG. 3 I has shown a different pulse-generating unit, synchronized with the operation of the frequency synthesizer 17, connected between terminals 27 and 28 in lieu of the Schmitt trigger 15. This unit comprises a frequency divider 32 which steps down the reference of oscillator 35 and feeds a pulse shaper 29 working into a switching input X of a data-type flip-flop 31. Input terminal 28 is tied to the data input D of this flip-flop whose reset output Q, assumed to go positive when the flip-flop is set, is connected to one input of an AND gate 30 having another input connected to the output of pulse shaper 29; gate 30 works into output terminal 27. As long as terminal 28 is energized, via the OR gate 14 shown in FIG. 1, AND gate 30 is unblocked so that the periodically recurring switching pulses from component 29 are passed to terminal 27. When the storage capacitor 4 (FIG. 1) is sufficiently discharged to de-energize the terminal 28, flip-flop 31 is reset by the next switching pulse and gate 30 is blocked. If desired, a delay line can be inserted between pulse shaper 29 and gate 30 to compensate for the lag in the switchover of the flip-flop.

Knob 1 need not be mounted directly on the shaft of generator 2 but could be coupled therewith through a step-up transmission, for example.