Microelectronic Fabrication Method Minimizing Threshold Voltage Variation

The invention relates to microelectronic processing, and in particular to fabrication of large CCD arrays or MOS/LSI circuits in which variations in the absolute value of the MOS threshold voltage could exceed acceptable limits.

Various methods for controlling threshold voltage variation through processing techniques are known in the prior art. The threshold voltage is a function of several parameters, including the gate oxide thickness, the doping of the substrate, and the gate to silicon work function .PHI..sub.GS. The threshold voltage can therefore be controlled by precisely controlling each of these variables. In practice, however, there are always non-uniformities in all of the variables.

One prior art technique adjusts for non-uniformities in certain ones of the parameters is varying the gate oxide thickness. This technique is frequently used in the prior art but does not result in the ultimate possible reduction in the threshold voltage variation in large wafers, since the range of t.sub.ox (the gate oxide thickness) is limited by device performance considerations and the physical limits on its dielectric integrity.

Another prior art technique is to use lightly doped initial substrate material and then ion implant the channel regions so as to create a more uniform doping at the surface. Yet another prior art technique is to use polysilicon gates with as low sheet resistivity as possible. The latter technique permits the .PHI..sub.GS term, the work function between the gate and the silicon substrate, to be more uniform.

All of these techniques used together limit the threshold voltage variation to reasonable levels for most applications. However, for demanding applications using large substrate areas such as large CCD arrays or MOS/LSI circuits with a large die area such techniques still do not permit the threshold voltage variation to be within acceptable limits. One of the side effects of the fabrication process which is not affected by such prior art techniques is the problem of autodoping of gate regions adjacent to degenerate diffusions, during gate oxide growth. Such autodoping results in appreciable local and wafer scale variations in the threshold voltage which are unacceptable for certain applications and which cannot be minimized using the prior art techniques.

Briefly, and in general terms, a method for minimizing the threshold voltage variation across the surface of a body of semiconductor material is disclosed. The method consists of making a semiconductor material structure by doping a pattern on the body with a dopant species such that the maximum concentration of the dopant species lies below the surface of the body and such that the surface concentration is approximately 10.sup.18 atoms/cm.sup.3 or less.

Devices are subsequently formed at the active areas of the body so that the maximum concentration of dopant species ultimately lies at the newly defined surface of the semiconductor region.

More specifically, the present invention provides a method of making a semiconductor material structure having a substantially uniform doping concentration on the surface thereof and substantially uniform threshold voltage, including the steps of providing a body of semiconductor material of a predetermined conductivity type and resistivity; defining a pattern along a laterally extended major surface for active areas of said body doping the pattern with a dopant species for forming a region of semiconductor material of different resistivity so that the maximum concentration of the dopant species lies below the major surface of the body by a predetermined distance, and the concentration of the dopant species lies at the surface of the semiconductor region by the end of the fabrication process.

FIG. 1 is a diagramatic view of the process of autodoping in a silicon wafer such as found in the prior art processes;

FIG. 2 is a graph of the concentration of dopant atoms in a silicon wafer in prior art processes as a function of the distance along the silicon surface;

FIG. 3a is a graph of the concentration of boron atoms in the silicon wafer as a function of distance into the substrate along a line normal to the surface before the oxidation and diffusion steps according to the present invention;

FIG. 3b is a graph of the final concentration of boron atoms in the silicon wafer after the sequence of process steps have taken place, indicating that the process steps have resulted in the growth of an oxide region on the surface of the silicon substrate such that the maximum value of the boron concentration now lies at the silicon surface;

FIG. 4 is a cross-sectional view of the surface of the silicon during the first of the process steps known as field masking;

FIG. 5 is a cross-sectional view of the surface of the silicon during the second in the process steps known as field oxidation;

FIG. 6a is a cross-sectional view of the surface of the silicon during the third in the sequence of process steps known as p+ mask and implant;

FIG. 6b is a graph of the concentration as a function of distance into the substrate along a line normal to the silicon surface through the p+ region of the cross-section shown in FIG. 6b;

FIG. 7a is a cross-sectional view of the silicon wafer during the next in the process steps known as n+ mask and implant;

FIG. 7b is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the n+ region in the cross-section shown in FIG. 7a;

FIG. 8a is a cross-sectional view of the surface of the silicon during the gate implant step;

FIG. 8b is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the p+ region in the cross-section shown in FIG. 8c;

FIG. 8c is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the channel region between the p+ and n+ implants in the cross-section shown in FIG. 8c.

FIG. 8d is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the n+ region in the cross-section shown in FIG. 8c;

FIG. 9 is a cross-sectional view of the surface of the silicon during the first poly gate fabrication step;

FIG. 10 is a cross-sectional view of the surface of the silicon during the second poly gate fabrication step;

FIG. 11a is a cross-sectional view of the surface of the silicon during the metal contact window mask fabrication step;

FIG. 11b is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the p+ region in the cross-section shown in FIG. 11c;

FIG. 11c is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the channel region between the p+ and n+ implants in the cross-section shown in FIG. 11c; and

FIG. 11d is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the n+ region in the cross-section shown in FIG. 11c.

The present invention is concerned with minimizing the variation in the threshold voltage of a transistor element through an improvement in the fabrication process.

The threshold voltage V.sub.T of a MOS transistor element is basically determined by the impurity concentration, the dielectric constant of the semiconductor substrate, and the thickness and dielectric constant of the gate insulating layer. More specifically, for a p-channel MOS field effect transistor, the threshold voltage V.sub.T is given the following formula: ##EQU1## where Q.sub.SS is the surface charge at the SiO.sub.2 surface (units: coulomb/cm.sup.2);

t.sub.ox is the gate oxide thickness (cm);

.rho..sub.ox is charge distribution in the silicon oxide (coulombs/cm.sup.3);

C.sub.ox is gate oxide capacitance per unit area (farad/cm.sup.2)

K.sub.Si is dielectric constant of silicon;

.epsilon..sub.o is dielectric permittivity of free space;

q is electronic charge;

N.sub.D is concentration of dopant atoms in the n-type region (atoms/cm.sup.3);

.PHI..sub.F is Fermi potential of silicon at a given temperature (with respect to .PHI..sub.i, the intrinsic Fermi potential);

.PHI..sub.GS is gate to silicon work function. (>0)

The first term in the above definition for the threshold voltage is minimized by clean processing techniques which avoid contamination of the oxide, and although there may be slight gradual variations in C.sub.ox over the wafer of 1-5%, such variations are assumed to be scaled smaller over the area of a single die.

The second, third and fourth terms in the threshold voltage definition above are affected by variations in the substrate dopant concentration N.sub.D. The strongest dependence upon N.sub.D is in the second term, in which the threshold voltage varies as a function of the square root of N.sub.D. The fourth term .PHI..sub.GS is affected by variations in the polysilicon gate dopant concentration, as well as by N.sub.D. However it must be pointed out that the polysilicon is normally deposited with as low as a sheet resistance (R.sub.S) as possible, and the variations in R.sub.S over a single die are minimized. Therefore, variations in .PHI..sub.GS due to variations in the polysilicon R.sub.S are negligible compared with the square root of N.sub.D term since .PHI..sub.GS varies quite slowly with R.sub.S.

To indicate how the threshold voltage might vary, assume that as an example, C.sub.ox and the polysilicon R.sub.S are constant, and the gate oxide thickness (t.sub.ox) is 1500 Angstroms. Consider a 5% variation in N.sub.D, which is normally equal to 10.sup.15 atoms/cm.sup.3. This would result in a 31.5 millivolt change in V.sub.T. Presently the most uniform wafers commercially available have from 10-20% uniformity in N.sub.D across the wafer radius. (Neutron transmutation doped silicon wafers claim a 5% uniformity in N.sub.D but the minority carrier lifetime in such wafers is too short for high performance MOS devices).

We first consider the fabrication method for producing a MOS/LSI or CCD circuit, and in particular a double polysilicon layer circuit using the well known isoplanar processes using a silicon wafer. Although such processes are described here as an embodiment of the present invention, the invention is not limited to such processes, and could be used with different semiconductor processes, such as the bipolar process, or with different semiconductor materials as well.

Several observations must first be made concerning the process step of deposition of dopant ions by prior art techniques of gaseous furnace deposition or shallow ion implantation. The impurity distribution in either case results in a very large surface concentration, C.sub.S, which decays Gaussian with depth into the wafer. After such deposition, and during the first few moments of the gate oxidation, dopant ions from the doped n+ and p+ regions will outgas from such regions according to the flux equation:

where F is the dopant flux, n is the unit normal to the silicon surface, h is the surface transport coefficient and .DELTA.C is the concentration difference (or flux potential) between the silicon and the ambient. In the case of the prior art .DELTA.C=C.sub.S, the concentration of the dopant at the surface. After the dopant atoms leave the n+ (or p+) surface, they will enter the ambient atmosphere where they have a relatively long mean free path and settle on nearby regions of lighter doped silicon, that is the nearest gate regions. This process, illustrated in FIG. 1, is known as "autodoping". The amount of autodoping will decrease with the distance from the source of the flux, as well as be affected by a number of external factors such as the carrier gas flow velocity in the furnace tube and temperature. After a few hundred Angstroms of the oxide is grown, the source of doped regions therefore becomes sealed, and the gate areas are masked and the autodoping process ceases. However, the autodoping which has already occurred results in unacceptable variations in the threshold voltage.

FIG. 2 is a graph of the resultant concentration of dopant atoms at the surface of the silicon substrate. Region 1 is a p+ defined region, region 2 is the laterally diffused p+ region, and region 3 is the adjacent gate region which has been counter doped by p+ autodoping.

It is noted that the degenerate doping profile is basically a Gaussian with a peak at the surface of the silicon. The peak value is C.sub.S. Typical values of C.sub.S for a p-channel surface mode CCD would be 5.times.10.sup.20 /cm.sup.3 for p+, and 1.times.10.sup.20 /cm.sup.3 for n+. The value of C.sub.S for furnace depositions on large wafers is relatively non-uniform, and can vary as much as 20% over the surface of a 3" diameter wafer.

The present invention eliminates such localized variations in N.sub.D due to autodoping by the reduction in .DELTA.C at the time of the first gate oxidation. Such reduction must however be achieved so that the p+ and n+ diffusions which form the active regions of the circuit have the correct R.sub.S or C.sub.S at the end of the fabrication sequence for proper operation of the device. This is done in the present invention by using ion implantation for the n+ and p+ deposition subject to the following criteria:

a. specifying that the initial peak of the ion implant profile is considerably below the surface, i.e. at least 2.2 standard deviations of the projected range of the implant profile, so that C.sub.S is better than 1/e.sup.5 less than the peak value of the impurity distribution profile;

b. specifying the range (i.e. the distance of the implant peak from the surface) and dose of the n+ and p+ ion implants such that after all the post-implant oxidation and other high temperature steps and etches in the fabrication process have taken place, the correct sheet resistances and junction depths have been obtained as required by the specification of the device; and

c. minimizing the high temperature processing after the n+ and p+ implants prior to the first gate oxidation so that the peaks remain below the surface and C.sub.S remains small;

The present invention implements these criteria by specifying the energy at which the ion implantation of the dopant species is to take place. The value of the energy depends upon the specific dopant and operational requirements, and may be calculated from known formulas once the desired range is specified. As one example, the prior art may specify an ion implantation energy for boron at 50 keV, while the present invention specifies an ion implantation energy of 120 keV in the same application.

Following the above protocol according to the present invention, reductions in C.sub.S of 10.sup.2 or 10.sup.3 can be accomplished. As a result the local variations in N.sub.D may be kept to below 1%. In such a situation the local variation of the threshold voltage can be kept below 7 millivolts for N.sub.D =10.sup.15 and t.sub.ox =1500 A, which is suitable for the intended applications of large CCD arrays or MOS/LSI circuits.

FIG. 3a is a graph of the concentration of boron atoms in the silicon wafer as a function of distance into the substrate along a line normal to the surface before the oxidation and diffusion steps according to the present invention. The peak of the concentration is seen to be considerably below the surface, as required by the first criteria noted above.

FIG. 3b is a graph of the final concentration of boron atoms in the silicon wafer after the sequence of process steps have taken place, indicating that the process steps have resulted in the growth of an oxide region on the surface of the silicon substrate such that the maximum value of the boron concentration now lies at the silicon surface.

Turning next to FIGS. 4-11, we explicitly describe a typical fabrication process of a double polysilicon gate MOS/LSI or CCD circuit using the isoplanar process incorporating the technique according to the present invention.

The starting material is a [100] silicon wafer substrate whose initial dopant concentration is relatively low, that is, a wafer having a relatively high resistivity. To take the example of fabricating a p-channel MOS transistor, the starting material is an n-type silicon wafer having a resistivity of the order of 3-5 ohm-centimeters. In the accompanying figures this is generally designated as n material, but such a designation is only intended to specify the dopant concentration in comparison with the dopant concentration of other n-type materials in the circuit. The designations n or n+ are not designations of absolute dopant level but merely relative dopant level.

The preferred processing sequence begins by first growing on the silicon wafer with a thin silicon dioxide film about 600 Angstroms in thickness by exposing the wafer to steam for 30 minutes at a temperature of 875.degree. C. A silicon nitride film about 600 Angstroms in thickness is then deposited over the oxide placing the slice in a reactor containing silane and ammonia gas. A photoresist is then applied to the wafer in a pattern to define the active circuit components, and the nitride is removed by a RF plasma etching process which does not attack the oxide layer. This step is known as field masking, and is illustrated in FIG. 4, which is a cross-sectional view of the silicon wafer. In the exposed areas a field oxide is grown by placing the wafer in a furnace at about 1000.degree. C. in steam atmosphere for several hours until the oxide grows to a thickness of about 1 micron. As the silicon oxide grows, it extends into the face or surface of the exposed silicon layer to a depth of about 5,000 A in the exposed areas, as shown in FIG. 5. In the areas where the nitride was not removed, the nitride film masks the growth of oxide beneath it, and both the nitride and thin oxide film remain at a thickness of 600 A each.

The next step is to remove both the nitride and oxide films by etching, thereby exposing a layer of silicon with regions or patches of field oxide surrounding them.

FIG. 6a shows the p+ mask and implantation step in which about 3,000 Angstroms of oxide are grown in the active area of the chip. This step is similar to the field oxidation step in which the wafer is placed in a furnace at 1,000.degree. C. in steam for about one hour. After the oxidation, photoresist is applied to form the window pattern for where the p+ diffusion in the active area of the chip is desired. Windows in the oxide are etched with hydrofluoric acid to form the oxide pattern. The resist, which is about a micron thick, and the oxide pattern together form a mask for ion implantation.

A dopant species, such as boron, is then ion implanted into the silicon according to the present invention so that the peak of the concentration distribution of the boron is about 4,000 Angstroms below the surface of the wafer. The particular depth is chosen to meet the ultimate dopant species surface concentration, sheet resistance, and other properties required at the end of the fabrication process. In the present example, the p+ peak concentration is about 1.7.times.10.sup.20 atoms/cm.sup.3, although the maximum could be about 5.times.10.sup.20 atoms/cm.sup.3.

FIG. 6b shows a graph of the concentration as a function of distance into the substrate along a line normal to the silicon surface through the p+ region, according to the present invention. After the ion implant step has been completed, the resist is stripped and about 2,000 Angstroms of silox is deposited and densified in a nitrogen or oxygen atmosphere for about 10 minutes at 1,000.degree. C.

FIG. 7a is a cross-sectional view of the silicon wafer during the next in the process steps known as n+ mask and implant. Again using photoresist technology windows are formed where n+ regions are wanted in the active area of the chip. Windows are formed in the resist, holes are etched in the oxide, around 4,000 Angstroms thick in these regions. With the resist and the oxide as a mask, the n+ pattern is ion implanted with a dopant species such as phosphorous. In this particular circuit, the peak of the concentration distribution of the phosphorous dopant is about 2500 Angstroms below the surface, and the peak concentration is around 5.times.10.sup.19 atoms/cm.sup.3. Such values are chosen in order to meet the ultimate dopant species surface concentration, sheet resistance, contact and channel stop parameters required for this particular circuit, although the peak concentration may go as high as 1.times.10.sup.20 atoms/cm.sup.3 in other applications. After the ion implant is actually done, one then strips the resist and goes on to the next step.

FIG. 7b is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the n+ region in the cross-section shown in FIG. 7a.

The next step shown in FIG. 8a, a cross-sectional view of the surface of the silicon during gate impant, is probably the most critical in the process. At this time all the oxide in the active circuit area of the chip is stripped so there is bare silicon in the active region and around one micron of field oxide. At this time the p+ and n+ regions are therefore also bare. If a furnace was used for deposition of the n+ and p+ regions, instead of ion implantation, the surface concentration would be above 10.sup.20 atoms/cm.sup.3 in the p+ and n+ regions. With such heavy surface concentration, once the wafer was heated up there would be significant outgasing from the n+ or p+ regions because of the high concentration there. However, in the method according to the present invention, which uses ion implantation instead, the peak is below the surface and the surface concentration is below 10.sup.18 atoms/cm.sup.3. The potential for outgasing has been reduced by a factor of 10.sup.2. With this in mind, one can then do a shallow ion implant for threshold adjustment in the gate regions of the device, and then perform the gate oxidation.

FIG. 8b is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the p+ region in the cross-section shown in FIG. 8c.

FIG. 8c is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the channel region between the p+ and n+ implants in the cross-section shown in FIG. 8c.

FIG. 8d is a graph of the concentration of dopant atoms as a function of distance into the substrate along a line normal to the silicon surface through the n+ region in the cross-section shown in FIG. 8c.

The next step shown in FIG. 9 is the fabrication of the first polysilicon gates which are composed of about 0.5 .mu. of n+ polysilicon having a sheet resistance of about 25 ohms per square. The gates are defined with photoresist technology, and plasma etching or chemical etching is used to etch the polysilicon. Subsequently the photoresist is stripped. If one needs a polysilicon to polysilicon contact, the first polysilicon layer is oxidized and windows etched in that oxide to make contacts to the poly for the next step.

The next step shown in FIG. 10 is the upper level gate fabrication. After the wafer has been oxidized and the first polysilicon pattern defined, another n+ polysilicon layer half a micron thick 25 ohms per square is deposited on the wafer. Photoresist technology is again used to define the second layer of polysilicon. The polysilicon is etched and the photoresist stripped as in the previous step.

Following this the wafers are oxidized to about 3000 Angstroms over the upper polysilicon. There is also an oxide thickness of about 4,000 Angstroms over the p+ silicon and about 4,000 Angstroms over the n+ silicon. Thickness of oxide between the polysilicon layers is about 3,000 Angstroms for this particular process. Photoresist technology is again used to etch windows in the oxides to make contact to the appropriate upper and lower polysilicon gates and the appropriate n+ and p+ diffusions as shown in FIG. 11. At this point in time all the high temperature processing on the wafer is done. There must be a certain surface concentration for p+, a certain junction depth, and a certain sheet resistance. In the particular example considered here, the requirements are a 60 ohms per square sheet resistance for p+, 8.times.10.sup.18 atoms/cm.sup.3 surface concentration, and junction depth about 1.5 microns.

In the n+ region there is a channel stop slightly over 1.0 micron deep and having a surface concentration of 6 or 7.times.10.sup.18 atoms/cm.sup.3, and a sheet resistance of around 80 to 90 ohms-square. The aluminum interconnect pattern is then formed using state of the art vacuum and photoresist technology.

In order to quantitatively demonstrate the improvement in threshold voltage variation using the process according to the present invention, we consider an example.

We first assume that variations in N.sub.D, t.sub.ox, N.sub.G are gradual across the wafer, and if such variables have periodicity the period is on the order of the wafer diameter.

We next assume that we use the best substrate material presently commercially available (with respect to dopant concentration uniformity), and that the wafer has had a "channel" implant to further enhance the dopant concentration uniformity. The dopant concentration (in atoms) is: ##EQU2## The gate oxide thickness is ##EQU3## The polysilicon gate (N+) dopant concentration is ##EQU4##

If, according to the prior art, the N+ and P+ diffusions were done with a furnace tube deposition and the surface concentration, C.sub.s (>10.sup.19 cm.sup.-3), of these diffusions would vary according to ##EQU5##

For a given C.sub.S of N.sup.30 (P.sup.+) a MOS gate adjacent to this diffusion could suffer a variation in N.sub.D due to autodoping that would occur during the first few moments of the MOS gate oxidation. This is a local effect (to an individual gate) and would be uniform across a wafer or chip if the .DELTA.C.sub.S of N.sup.+ (P.sup.+) were zero. For example, a CCD transfer gate could have a nonuniform depletion layer width as a result of this effect or the MOSFET threshold voltage would be shifted. This local effect could have a further asymmetrically based variation across the chip due to variations in the chip's circuit layout, e.g. more n+ or p+ adjacent to gates in certain regions of the circuit such as the case where one region has n+ channel stops (p channel) while another does not, etc. However, this additional effect cannot be predicted in general terms.

For example, the local effect could have a range of 1%, 5%, 10%, 30% variation in N.sub.D from the autodoping depending on the magnitude of C.sub.S (10.sup.19- 10.sup.21 cm.sup.-3) used in the particular process. Based on the .+-.20% .DELTA.C.sub.S of the wafer and .+-.4% .DELTA.C.sub.S across a chip, these percent .DELTA.N.sub.D in the local effect would represent the following .DELTA.N.sub.D 's due to the autodoping alone.

Since the autodoping variations and the native wafer variations in N.sub.D are statistically independent, their total is found through quadratures.

Taking the total .DELTA.N.sub.D, the .DELTA.t.sub.ox, and the .DELTA.N.sub.G, for this range of .DELTA.N.sub.D (gate), we have the following range of variation in threshold voltage (N.sub.SS= 5.times.10.sup.10 cm.sup.-2) according to the prior art:

Values of percent local autodoping of 20-30% are quite probable for the heavy p+ and n+ diffusions used, especially for large chips where one needs low sheet resistance.

Now, let us calculate the threshold voltage variation using the process according to the present invention. The .DELTA.N.sub.D (gate autodoping) is reduced drastically, as well as the .DELTA.C.sub.S of N.sup.+ (P.sup.+). This would give: ##EQU6## So, combining these we have the .DELTA.N.sub.D due to the reduced autodoping: .+-.0.015% wafer, .+-.0.003% chip, .+-.0.5% gate. Adding these variations in quadratures to the .+-.2.5%, .+-.0.5%, .+-.0.1% variation of the wafer across the wafer, chip and gate we get: ##EQU7## For the same variations in t.sub.ox and N.sub.G as assumed in the prior art this gives for the threshold voltage variation ##EQU8## As a comparison, these values represent the following % improvements in .DELTA.V.sub.TH over a wafer, chip, and gate, for the various percent autodoping that one had in the prior art.

It should also be noted that if after the previous result, t.sub.ox were reduced to 1,000 Angstroms we would have a 35.2% W, 35.0% C, 32.6% G improvement in a .DELTA.V.sub.TH. If N.sub.SS were reduced to 2.times.10.sup.9 cm.sup.-2, we would have a further 20.2% W, 20.2% C, 7.9% G improvement in .DELTA.V.sub.TH.

The above table which indicates an improvement in threshold voltage variation up to 20% over a wafer, and up to 97% over a gate area, demonstrates the considerable improvement over the prior art provided by the present invention.