Manufacturing Process of Semiconductor Devices

The present invention relates to a process of manufacturing semiconductor devices, and more particularly to the method of manufacturing an isolated PN junction of a semiconductor mesa diode.

The manufacture of diodes by employing the conventional planar process, especially the contacting and encapsulating, is entailed by difficulties which are due to the PN-junction positioned on the surface. This PN-junction is protected by an SiO.sub.2 -layer, but owing to pressures exerted during the encapsulation, cracks are likely to result in the SiO.sub.2 -layer so that reverse currents are likely to develop.

As is known, a considerable disadvantage of the planar process is seen in the forming of bent diffusion fronts at the masking edges. It is known that this is not the case with the mesa process, but instead the mesa process is known to have other disadvantages, such as that the devices produced thereby have a non-protected PN-junction, and that the passivation is entailed by difficulties in the case of genuine mesa devices.

The German published patent application (DT-OS) No. 24 42 398 discloses a process of manufacturing a plurality of mesa semiconductor devices in which one side of a semiconductor substrate is provided on its entire surface with a PN-junction area which then, by employing a photolithographic etching process, is divided into mesas in accordance with the number of semiconductor devices, whereupon the substrate surface containing the mesas is provided with an oxidation layer. In this conventional process, the substrate is first readily diffused and the covering masking is applied after the mesas have been etched out. The position of the PN-junction and its angle in relation to the mesa surface is determined in this process, above all by the etching depth, with it being naturally difficult to reach the ideal value of 90.degree. for the angle.

Considering that the masking is effected by thermal oxidation, the diffusion-out at the PN-junction lying at the edge of the mesas may cause a surface depletion at the marginal area. In consequence of this, it may happen that the angle already deviating from the ideal value is still changed more strongly. This increases the danger of a break-down of the loading of the diode.

Accordingly, it is the object of the invention to provide a process for manufacturing semiconductor devices not having the aforementioned disadvantages.

The present invention relates to a process in which on the surface of the semiconductor substrate of one conductivity type there is first only provided a coating with a doping agent resulting in the surface layer being of the other conductivity type, with the defining of the PN-junction being carried out by way of diffusion following the photolithographic process and the building of the mesas. A SiO.sub.2 -layer is produced simultaneously by way of thermal oxidation by working in an oxidizing atmosphere while the doping agent is diffused-in at the edges of the mesas. From this there will result a device which may be referred to as a quasi-mesa device combining the advantages of the electrical properties of a mesa device with the advantages of the planar technology. It is of particular advantage that the passivation in the process according to the invention is carried out with a thermally formed oxide which is produced in one step of the process together with the diffusion.

The devices manufactured in accordance with the process of the invention show to have a number of advantages. Thus, for example, it is possible to achieve high inverse voltages, and by utilizing the entire surface, it is possible to achieve a high current-carrying capacity, and the devices are insensitive to peak voltages, so that no destruction will occur during operation as a result of breakdown.

FIGS. 1-6 are sectional views taken through a semiconductor substrate during successive process steps according to the method of the present invention.

The invention will now be explained in detail with reference to an example of embodiment shown in the accompanying drawings, in which silicon nitride is used as the diffusion masking.

Following the usual cleaning process, the surface of the n-conductive silicon substrate 1 is coated throughout the entire surface with a doping agent, such as boron, resulting in a p-conductive surface layer 2 (FIG. 1). Both the temperature and the time of deposition depend on the later practical application of the devices to be manufactured. The doping is carried out in accordance with one of the conventional processes, such as by using boron nitride planar diffusion sources, or with the aid of PH.sub.3. A coating with the aid of the hydrogen injection process is likewise possible.

As a next step there is carried out, in accordance with FIG. 2, the deposition of a layer 3 of Si.sub.3 N.sub.4 on the doped substrate 1, whereupon the layer 3 is covered with a SiO.sub.2 -layer 4. The latter serves as a masking for the Si.sub.3 N.sub.4 -layer 3 lying therebeneath, so that it is possible to work with phosphoric acid as the etching agent.

In the course of the next step of the process, the etching pattern is produced with the aid of the photolithographic process. The SiO.sub.2 -layer is first removed with the aid of a photomask, at those points where the silicon nitride layer 3 and, consequently, the p-doped substrate surface is to be exposed. The etching of the silicon dioxide masking is carried out with the conventional etching solutions, and the removal of the silicon nitride at the exposed points is carried out with the aid of phosphoric acid. The finished step of the process is shown in FIG. 3.

As a next step there is effected the structure etching of the silicon substrate material, with the silicon nitride layer 3 serving as the etching mask. In so doing, there is utilized the different reactivity of the etching solution with silicon and silicon nitride. Depending on what type of diode is desired, i.e. low-blocking, medium-blocking or high-blocking diodes, the depth of the etching groups can be controlled by employing three different etching times.

FIG. 4 shows the completed step of the process, and it is recognizable that in the course of the etching process there has also been removed the SiO.sub.2 -layer 4 as positioned over the silicon nitride layer 3. The geometry of the future device is now laid down, and the outlined mesa structure thereof becomes distinguishable.

In the course of the hitherto performed process steps, the depth of the PN-junction 2' has not yet been fixed. This is carried out now in the following step, with the doped surface layer 2 as deposited in the course of the first step of the process, serving as a source. The diffusion is carried out in an oxidizing atmosohere, so that simultaneously, besides diffusing-in the doping agent, the oxide layer 5 as resulting at the edges of the mesa, will prevent a diffusion-out of the doping atoms. In the course of this, there results an almost flat diffusion front, and the angle in relation to the surface at the PN-junction 2' is close to the ideal value; even in the case of a relatively small diffusion depth, there will be obtained an almost rectangular profile (FIG. 5).

In the course of the last step of the process (FIG. 6), and subsequently to the removal of the silicon nitride layer 3 by way of etching out, there is produced an electric contact by evaporating various thin metal layers. In the course of this, there is first deposited a thin layer of titanium 6 over which there is then evaporated the silver layer 7. This step of the process is followed by a photoprocess with the aid of which there is enabled the growing of the contacts 8 on the mesa and surfaces in the contact bath. Prior to cutting (breaking) the semiconductor substrate into the individual devices, the titanium-silver layer is etched away between the contact surfaces.

In the present example of embodiment the etching of the Si.sub.3 N.sub.4 -layer was carried out with the aid of phosphoric acid, so that a SiO.sub.2 -layer was required as an etching mask. In cases where the work is carried out in accordance with the plasma etching process, the SiO.sub.2 -layer may be omitted, and the photoresist layer is deposited directly over the Si.sub.3 N.sub.4 -layer.

While we have described above the principles of our invention in connection with specific apparatus it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of our invention as set forth in the objects thereof and in the accompanying claims.