Jsit-Type Field Effect Transistor With Deep Level Channel Doping

(a) Field of the invention:

The present invention is related to a transistor, and in particular it pertains to a field effect transistor of the type wherein the channel is conductivity-modulated in accordance with the amount of minority carriers injected from the gate into the channel of the field effect transistor.

(b) Description of the prior art:

Field effect transistors of the type wherein the impedance between the source and the drain is controlled according to the amount of minority carriers injected from the gate into the channel located between the source and the drain have been proposed. As an example of the field effect transistors of the type described above, a junction field effect transistor of vertical type has been proposed by Jun-ichi Nishizawa. This junction field effect transistor is designed so that depletion layers extending from the gate into the channel may substantially pinch-off the channel when the gate p-n junction is zero-biased, and that the depletion layers may shrink to render the channel conductive when the gate p-n junction is forwardly biased, i.e. when sufficient amount of minority carriers are injected from the gate into the channel.

The aforementioned junction field effect transistor has many excellent features, and finds wide use in its electronic applications. However, this junction field effect transistor is accompanied by the drawback that the switching speed, particularly the turn-off speed thereof is inherently somewhat limited due to the minority carrier storage effect at the gate p-n junction.

It is, therefore, an object of the present invention to provide a field effect transistor of the type wherein the channel is conductivity-modulated according to whether or not minority carriers are injected from the gate into the channel, and which is capable of making rapid turning on and off actions.

Another object of the present invention is to provide a junction field effect transistor of the type described above, which is substantially free from the minority carrier storage effect at the gate p-n junction.

Yet another object of the present invention is to provide a junction field effect transistor of the type described above, which is suitable for use as a switching element in a logic circuit.

A further object of the present invention is to provide an integrated injection logic (IIL) circuit employing a junction field effect transistor as the driver or inverter transistor thereof.

A feature of the present invention resides in that the life time of the injected minority carriers in the channel is shortened by the inclusion of a sufficient amount of recombination centers for the injected minority carriers in the channel region. The recombination centers may, for instance, comprise lattice defects formed in the channel region lattices by the application of high-energized rays onto the channel region. Alternatively, the recombination centers may comprise substitutional impurities, i.e. one or more life time killer elements, such as gold, iron, copper or other heavy metallic elements, introduced in the lattices of the channel region.

It should be understood that the presence of such lattice defect in the channel region does not adversely affect the essential characteristics of the field effect transistor, because the field effect transistor inherently operates on the basis of majority carrier behavior.

These and other objects as well as the features and the advantages of the present invention will become apparent by reading the following detailed description of the preferred embodiment when taken in conjunction with the accompanying drawings.

FIG. 1 is a diagrammatic top plan view of an example of the IIL circuit device employing junction field effect transistors according to the present invention as the driver or inverter transistors thereof.

FIG. 2 is a sectional view taken substantially along the line A--A of the device of FIG. 1.

FIG. 3 is an equivalent circuit diagram of the device shown in FIGS. 1 and 2.

Like portions are indicated by like reference numerals and symbols throughout the drawings.

An example of IIL Circuit device employing junction field effect transistors embodying the present invention (hereinafter referred to as SITL which is an abbreviation of a Static Induction Transistor Logic) is illustrated in top plan view in FIG. 1, and in section in FIG. 2.

The SITL circuit device includes an N-type semiconductor substrate 10 of a low resistivity, which may be a mono-crystalline or poly-crystalline silicon. On the top surface of the substrate 11 is deposited an N-type semiconductor layer 12 of a relatively high resistivity as compared with that of the substrate 11, to constitute a monolithic semiconductor wafer 10 together with the semiconductor layer 12. The layer 12 may be formed by relying on the conventional vapor deposition technique or diffusion technique. In the semiconductor layer 12, individual highly-doped P-type semiconductor regions 13, 14 and 15 extending from the top surface of the layer 12 to the inside thereof are formed, by the selective diffusion technique, for instance. The respective regions 13, 14 and 15 have a low resistivity. On the upper surfaces of the regions 13 is deposited a continuous electrode 22, establishing ohmic contacts with these surfaces. Also, on the upper surface of the region 14 is deposited an ohmic-contacting electrode 23. Another continuous electrode 24 is deposited on the upper surfaces of the regions 15. Those electrodes 22, 23 and 24 may be deposited by relying on the masking or evaporation techniques. Alternatively, the electrodes may be deposited by a paste containing metallic particles which may be painted or silk-screened on the desired portions. On the upper surfaces of those portions of the layer 12 which are located between the semiconductor regions 13, discrete electrodes 25, 26 and 27 are deposited, respectively. Furthermore, on the upper surfaces of those portions of the layer 12 which are located between the respective regions 15, individual electrodes 28, 29 and 30 are deposited, respectively. These electrodes 25, 26, 27, 28, 29 and 30 are adapted to establish ohmic contacts with respctive highly-doped N-type semiconductor regions 16, 17, 18, 19, 20 and 21 of a low resistivity provided at the upper parts of the portions of the layer 12 sandwiched between the adjacent regions 13 and 15. These low-resistivity regions may be formed by relying on the selective diffusion techniques, for example. On the bottom surface of the substrate 11, an ohmic-contacting electrode 31 is provided. Reference numeral 32 indicates a passivation film of insulating material such as silicon dioxide, which covers the exposed portions of the upper surface of the layer 12.

In the embodiment of FIG. 2, the N-type semiconductor layer 11 has a impurity concentration of 10.sup.24 -10.sup.27 atoms/m.sup.3. The other N-type layer 12 has an impurity concentration of 10.sup.18 -10.sup.21 atoms/m.sup.3 and a depth of 2-10 .mu.m. Each of the P-type regions 13, 14 and 15 has an impurity concentration of 10.sup.24 -10.sup.26 atoms/m.sup.3 and a depth of 1-3 .mu.m. Each of the N-type regions 16 through 21 has an impurity concentration of 10.sup.24 -10.sup.27 atoms/m.sup.3 and a depth of 1 .mu.m or less. The portion of the layer 12 sandwiched between the regions 14 and 15 has a thickness of 5 .mu.m or less in the horizontal direction viewed in FIG. 2. Each adjacent pair of the regions 13 and 15 are separated by a distance of 2-10 .mu.m which is occupied by a portion of the layer 12 of the impurity concentration of 10.sup.18 -10.sup.21 atoms/m.sup.3.

The equivalent circuit of the embodiment described above is illustrated in FIG. 3, wherein reference symbol Q.sub.i represents an injector transistor of bipolar type, and symbols Q.sub.d1 and Q.sub.d2 represent driver or inverter transistors each comprising a junction field effect transistor of vertical type embodying the present invention.

Description will now be made on the co-relationship between FIG. 3 and FIG. 2. The driver transistor Q.sub.d1 comprises the semiconductor layer 12, and the semiconductor regions 13, 16, 17 and 18. More particularly, the p-type semiconductor regions 13, the substrate 11 and the n-type semiconductor layer portions 12 located adjacent to the upper portion of the substrate 11, the portions of the n-type semiconductor layer 12 sandwiched between the adjacent pair of the regions 13, and the n-type regions 16, 17 and 18 including those portions of the layer 12 which are located adjacent to the regions 16, 17 and 18, constitute the gates G, the sources S, the channels and the drains D.sub.1, D.sub.2 and D.sub.3 of the N-channel junction field effect transistor Q.sub.d1 of the vertical type, respectively. Similarly, the p-type semiconductor regions 15, the substrate 11 and the n-type semiconductor layer portions 12 located near the upper surface of the substrate 11, the portions of the layer 12 sandwiched between the adjacent pair of the regions 15, and the n-type regions 19, 20 and 21 including those portions of the layer 12 which are located adjacent to these regions constitute the gates G, the sources S, the channels and the drains D.sub.1, D.sub.2 and D.sub.3 of the driver transistor Q.sub.d2 which is an N-channel junction field effect transistor of vertical type, respectively. On the other hand, the p-type semiconductor region 14, one of the regions 15 which is located nearest to the region 14, and that portion of the n-type semiconductor layer 12 which is sandwiched between these regions constitute the emitter I, the collector C, and the base B of the injector transistor Q.sub.i of bipolar type, respectively.

As shown in FIG. 1, the respective gates of the driver transistor Q.sub.d1 are connected together by the continuous electrode 22, i.e. held at a same potential. Similarly thereto, the respective gates of the driver transistor Q.sub.d2 are connected together by the continuous electrode 24, i.e. maintained at a same potential. The collector of the injector transistor Q.sub.i or the gate G of the driver transistor Q.sub.d2 is coupled to the drain D.sub.3 of the driver transistor Q.sub.d1 by a conductive line L. Moreover, the sources of both of the driver transistors Q.sub.d1 and Q.sub.d2 are connected together by the continuous electrode 31 at the bottom side of the substrate 11, as illustrated in FIG. 2.

Each of the driver transistors Q.sub.d1 and Q.sub.d2 is designed to operate so that the channels are substantially pinched off by the depletion layers growing from the gates into the channels when the gate p-n junctions are nearly zero-biased, and that the depletion layers shrink to render the channels conductive when the gate potential is raised to about the built-in barrier voltage of 0.3-0.6 volt of the gate p-n junctions. In other words, the dimensions and the carrier concentrations of the respective regions are determined so as to satisfy the aforementioned requirements. Needless to say, the above-mentioned channels of the driver transistor Q.sub.d1 (or Q.sub.d2) are those portions of the semiconductor layer which are surrounded by the gates 13 (or 15), the drains 16, 17 and 18 (or 19, 20 and 21) and the continuous source.

Furthermore, in accordance with the present invention, the channels of the driver transistors Q.sub.d1 and Q.sub.d2 include recombination centers for the minority carriers injected thereinto from the gates to such an amount that the life time of the injected minority carriers is sufficiently shortened in order to reduce the minority carrier storage effect, so that the increased switching speed, particularly the turning-off speed, of the transistors Q.sub.d1 and Q.sub.d2 is attained. Such recombination centers may comprise the lattice defects in the channel regions. The lattice defects may be formed, for instance, either by doping any suitable substitutional impurities, i.e. so-called life time killer elements such as gold, iron, copper or other heavy metallic elements, into the channels, or by applying any high-energy rays, such as electron rays, to the channel.

In this embodiment, an element such as gold as the substitutional impurity, is doped in the entire range of the semiconductor layer 12 including the channels, and the concentration of this element gold is selected in the range of about 10.sup.18 -10.sup.21 atoms/m.sup.3. It should be noted that it is sufficient that only in the channel regions is selectively doped the element gold. In the arrangement of this embodiment, however, there can be obtained the advantage that the doping of the element gold is performed simultaneously with the formation of the semiconductor layer 11. The doped gold provides such recombination centers at energy levels which are relatively low as compared with those of the conduction energy bands in the channel region crystal. Excessive minority carriers and the majority carriers in the channels are trapped by the energy levels of the doped gold in the channels, and the they are recombined with each other, with the result represented by a reduced life time of the minority carriers. As a result, the driver transistors Q.sub.d1 and Q.sub.d2 embodying the present invention are hardly subject to the minority carrier storage effect, and thus can effect a rapid turn-off.

The operation of the aforementioned embodiment of the present invention is explained hereunder with reference to the respective Figures.

Let us now suppose that the injector transistor Q.sub.i is in the non-conducting state, and also the driver transistor Q.sub.d1 is turned off. In this condition, the subsequent stage driver transistor Q.sub.d2 is in its "off" state, because the gate depletion layers are pinching off the channels. When the injector transistor Q.sub.i is forward-biased with a positive voltage applied to the emitter electrode 23, i.e. the injection electrode I, holes are injected into the gates of the driver transistor Q.sub.d2 from the injector transistor Q.sub.i to raise the potential of the gate of the transistor Q.sub.d2 to a level at about the built-in barrier voltage of the gate p-n junctions. As a result, a sufficient amount of holes are injected from the gates into the channels of the transistor Q.sub.d2 so that the gate p-n junctions are forward biased. Accordingly, the gate depletion layers will shrink to render the channels conductive, with the result that the driver transistor Q.sub.d2 is turned on.

Thereafter, if a positive voltage of approximately the gate built-in voltage is applied to the gate electrode 22 of the transistor Q.sub.d1 to forward-bias transistor Q.sub.d1, the holes from the injector transistor Q.sub.i are drawn into the conducting driver transistor Q.sub.d1 via the connecting line L. As a result, the gate potential of the driver transistor Q.sub.d2 is pulled down to a substantially low level at which the driver transistor Q.sub.d2 is turned off. As described previously, the channels of the transistor Q.sub.d2 include minority carrier recombination centers, and the life time of the minority carriers, i.e. holes in the channel regions, is considerably shortened. Therefore, the excessive holes in the channel regions will rapidly disappear due to these recombinations, so that the turning-off of the transistor is accomplished at a high speed.

It should be understood that the driver transistor (Q.sub.d1, Q.sub.d2) has such a drain-to-source resistance in the conducting state thereof that it is effective for pulling down the potential of the gates of the connected driver transistor to a low level at which the latter driver transistor is turned off.

It will be understood by those skilled in the art, that changes and modifications may be made to the aforementioned embodiment of the present invention without departing from the spirit and scope of the invention as set forth in the claims appended hereto. Furthermore, the present invention can be applied to any junction field effect transistor of the type which exhibits operation characteristics resembling those of pentode vacuum tubes, as well as to a junction field effect transistor of the vertical type like the afore-mentioned embodiment transistors which exhibits operation characteristics resembling those of triode vacuum tubes.