Word Recognizing System

1. Field of the Invention

This invention relates to a digital word recognizing system, and more particularly to a real time system for recognizing variable length words serially transmitted in a data stream.

2. Description of the Prior Art

Word recognizing systems for identifying known words in a data stream are in conventional use. However, these prior art systems are generally of limited value principally because of their inability to handle large, variable length words as well as their inability to perform the word recognizing function in real time. The capacity of conventional systems has generally been limited to words of only a few hundred bits, and it usually has been necessary to know the location of the work in the incoming data stream. Also, these systems rely on mathematical analysis to perform the word recognizing function. Consequently, they are incapable of operating in real time and thus they are fairly slow because of the computing and data processing required. Furthermore, propagation delays have been experienced through all the stages between each step in entering data in serial or parallel form.

It is an object of the invention to provide a real time word recognizing system having a recognition rate which is equal to the data clock rate.

It is another object of the invention to provide a real time work recognizing system which is easily expandable to handle virtually any length word and accuracy.

It is still another object of the invention to provide a system which is capable of recognizing words in a data stream without prior knowledge of the location of the word in the data stream.

It is a further object of the invention to provide a word recognizing system that is capable of operating with correlation errors approaching zero regardless of word length.

These and other objects of the invention are accomplished by comparing the incoming data stream bit for bit against a known word stored in a register. The results of the comparisons are summed so that either a maximum positive comparison or a minimum negative comparison identifies the known word in the data stream. Since the system operates in real time, the word is detected by the time it has serially clocked through the system so that the speed limitation is that of the clock data rate and word length rather than the throughput capacity of the system. In a first embodiment the location of the word in the data stream is not known, and the data stream is clocked along a shift register in one direction while the known word is recirculating clocked through another shift register in the opposite direction. In a second embodiment the location of the word in the data stream is not known and the bit by bit comparison is made with the known data word remaining stationary in internal registers. The comparison is then made between corresponding registers in the respective shift registers.

FIG. 1 is a schematic illustrating the concept of the first embodiment of the invention.

FIG. 2 is a schematic illustrating the concept of the second embodiment of the invention.

FIG. 3 is a block diagram illustrating a system for implementing the concept of FIG. 1.

FIG. 4 is a block diagram illustrating a system for implementing the concept of FIG. 2.

FIG. 5 is an electrical schematic of one system corresponding to the block diagram of FIG. 3.

FIG. 6 is an electrical schematic of one system corresponding to the block diagram of FIG. 4.

Referring to FIG. 1, the first bit of a know word B circulating in a shift register clocked to the left, meets the first bit of an unknown word A in a comparator G. FIG. 1 shows how the two words meet bit for bit from bit 1 to bit 4 from time T1 to time T4. As explained hereinafter, the output of the comparator is connected to a counter which counts the number of positive comparisons between bits (i.e. matching bits) or the number of negative comparisons between bits (i.e. non-matching bits). In FIG. 1, the incoming word in the data stream meets the stored word at the comparator G. However, the first bits of the two words could have met at any of the comparators and the result would have been the same. Therefore, a word can be recognized from a stream of data by summing the positive or negative bit for bit comparisons to determine how well the incoming word matches the stored word.

A block diagram of a system for implementing the concept explained above and shown in FIG. 1 is illustrated in FIG. 3. The known word is clocked to the left and recirculated through shift registers C1, C2, C3 - - - CN. The incoming data is clocked to the right through shift registers A1, A2, A3 - - - AN. The outputs of corresonding registers AN and BN are compared by respective comparators B1, B2, B3 - - - BN. The bit by bit comparison of the two words from the comparators B1, B2 - - - BN are counted by respective counters D1, D2, D3 - - - DN, each counter being able to count to N. Outputs from shift registers F1, F2, F3 - - - FN are connected to the reset inputs of respective counters D1, D2, D3 - - - DN. The shift registers F1, F2, F3 - - - FN are connected in recirculating fashion, and all but one of the register contain a logic "0". One of the registers contains a "1" which is shifted through the registers F1, F2, F3 - - - FN in synchronism with the first bit of the known word in the registers C1, C2, C3 - - - CN. The "1" sequentially resets respective counters D1, D2, D3 - - - DN and loads the outputs of the counters into respective output registers E1, E2, E3 - - - EN. Thus, just before the first bit of the word reaches each register C1, C2, C3 - - - CN the corresponding counter D1, D2, D3 - - - DN is reset and its contents are loaded into its respective register E1, E2, E3 - - - EN. The information in the output registers E1, E2, E3 - - - EN is transferred to an external processor (not shown) which examines the contents of each of the registers E1, E2, E3 - - - EN to determine if they indicate a word match. Utilizing the example of FIG. 1 and assuming that the G comparator (FIG. 1) corresponds to comparator B2 (FIG. 3), the number of register E2 would be 4 (to indicate 4 matching bits). Since the word is 4 bits in length a 4 output from register E2 indicates that the known word has been received in the incoming data stream.

A schematic illustrating one embodiment of a circuit for the block diagram of FIG. 3 is illustrated in FIG. 5. The data stream is received on a line 100 and is sequentially shifted through a plurality of cascaded flip-flops 102, 104, 106 in accordance with clock pulses on line 108. The flip-flops 102, 104, 106 correspond to the A registers of FIG. 3. Similarly, the known word recirculates through flip-flops 110, 112, 114 in accordance with the clock pulses so that the data stream is shifted to the right through flip-flops 102-106 in synchronism with the recirculation of the known word through flip-flops 110-114 to the left. The outputs of corresponding data stream flip-flops 102-106 and known word flip-flops 110-114 are received by respective exclusive-OR gates 116, 118, 120 which produce a logic "1" whenever both of their inputs are identical. The exclusive-OR gates 116-120 increment respective cascaded counters 122, 124, 126. The counters 122-126 are incremented once each time the exclusive-OR gates 116-120 detect a bit match.

A second recirculating shift register formed by flip-flops 128, 130, 132 is utilized to sequentially reset each of the counters 122-126 as the first bit of the known word reaches the corresponding known word flip-flops as explained above. Accordingly, only one of the flip-flops 128-132 contains a "1" while the remainder of the flip-flops 128-132 contain zero. The one is sequentially clocked through the flip-flops 128-132 by the clock pulse on line 156. For example, a "1" at the Q output of flip-flop 130 resets counter 124 through AND gate 134 between clock pulses. The "1" is then shifted to flip-flop 128 to reset counter 122 between the next two clock pulses. Thus, for example, when the "1" is shifted from flip-flop 130 to flip-flop 128 just after counter 124 has been reset, the first bit of the known word is shifted into flip-flop 112. As the counters 122-126 are reset, their contents are loaded into respective registers 136, 138, 140 which corresponds to the registers E of FIG. 3. The comparison count in registers 136-140 are then serially transferred to an external device by clock pulses on line 156.

As an alternative to loading data from the counters 122, 124, 126 into the registers 136, 138, 140, the data can be loaded onto a tri-state bus connected to one set of inputs of comparators 150, 152. The other set of inputs to the comparators 150, 152 receives the output of a register 154 containing a number corresponding to the number of bits in the known word which has been entered into the register by conventional means. A match between the number in the register 154 and the number on the tri-state bus indicates that the known word has been received.

In a second embodiment the bits of the known word remain stationarily stored in respective registers while the unknown word is clocked through a shift register. Referring to FIG. 2, the first bit of a known word B stationary in a register, matches the first bit of an unknown word A in a comparator C at time T1. At time T2 we see that no bit in the incoming data matches any bit of the stationary, knwon word. At time T3, bit 2 of the stationary matches word bit 2 of the incoming word at comparitor D. As the clocking of the incoming data continues, a bit of the incoming word matches a bit of the stationary word in one of the registers during times T1, T3, T5 and T7. At times T2, T4 and T6 none of the bits of the incoming word match any bit of the stationary word. In order to detect incoming words which first reach the first register C during even times an additional set of comparitors and counters is required. The additional set compares and counts while the first set transfers data to the next register. As in the example of FIG. 1, when the matching bits are counted and the maximum output identifies the known word. When non-matching bits are counted the minimum output identifies the known word.

A block diagram of a system for implementing the concept shown in FIG. 2 and explained above is illustrated in FIG. 4. The incoming stream of unknown data is clocked to the right through shift register A1, A2, A3 - - - AN, and the known word is stored in registers C1, C2, C3 - - - CN. The bit by bit comparison is done by respective comparitors B1, B2, B3 - - - BN. The comparitors B1, B2, B3 - - - BN increment respective counters D1, D3, D5 - - - DN and D2, D4, D6 - - - D(N+1). One set of counters D2, D4, D6 - - - D(N+1) is enabled during even time periods T2, T4, T6 - - - T(N+1). When the even set of counters D2, D4, D6 - - - D(N+1) is enabled the counts stored in the odd set of counters D1, D3, D5 - - - DN are shifted to the right. Similarly, when the odd set of counters D1, D3, D5 - - - DN is enabled the counts stored in the even set of counters D2, D4, D6 - - - D(N+1) are shifted to the right. When the count initially stored in the first counter of each set D1, D2 is shifted out of the last counter for each set DN, D(N+1), respectively, a count from either of the counters DN, D(N+1) equal to the number of bits in the known word indicates the known word has been received in the incoming data stream.

One embodiment for implementing the system of FIG. 4 is illustrated in FIG. 6. The incoming data is shifted to the right through a shift register formed by flip-flops 200, 202 204, 206 in accordance with clock pulses received on line 208. The known word is stored in a register composed of flip-flops 210, 212, 214, 216. The outputs of corresponding flip-flops 200, 210; 202, 212; 204, 214; 206, 216; are compared by exclusive-OR gates 218, 220, 222, 224, respectively. The outputs of the exclusive-OR gates 218-224 are applied to respective counters 226, 228, 230, 232, respectively, through inverter 234 and NAND gates 236, 238, 240. The inputs to NAND gates 236, 238, 240 are disabled by inverters 242, 244, 246, respectively when the counters have incremented to their maximum value. The CLK pulses toggle a flip-flop 260 which alternately enables NAND gates 262, 264 to provide alternate clock pulses at their respective outputs. The counters 226-232 are enabled during the alternate clock pulses from NAND gate 262 so that matching bits indicated by the exclusive-OR gates 218-224 can increment the counters 226-232 during those times. During alternate clock pulses from NAND gate 262 the contents of the counters 226-232 are shifted one step to the right from respective temporary storage latches 248, 250, 252, 254 by the alternate clock pulses at the output of NAND gate 264 in order to accomplish the data transfer. A second set of counters and latches 266 operates out of phase with the first set. The first set of counters and latches corresponds to the odd counters D1, D3, D5 - - - DN of FIG. 4 while the second set of counters and latches 266 corresponds to the even counter D2, D4, D6 - - - D(N+1) of FIG. 4.

It will be understood that either embodiment of the invention may be stacked, i.e., several word recognizing systems may be placed in parallel to receive data transmitted over a number of lines in parallel.

A large word can be from 100 to 1,000 bits, and up to 10,000,000 bits, and a special purpose TV picture may have 3,000,000 bits of analog data. For detecting a 10,000 bit item from a 300,000 bit TV picture, quick reading and tracking of a 1,000 to 2,000 bit of good contrast data may be adequate to quickly locate the item and then the 10,000 bit item can be detected.