Dual Mode Read Preamplifier With Electrical Short Detector

This invention relates to monitoring the performance of recording channels and electrical components therein.

An object of this invention is to provide a monitor for testing write channels by use of available read circuitry.

Another object of this invention is to provide a circuit for sensing electrical shorts in magnetic heads.

In prior art storage systems, write channel circuitry operation including the magnetic heads were monitored by providing additional test circuits across the heads to determine whether the write channel was operating satisfactorily. The additional electronics would load the head and contribute noise signal so that monitoring was subject to error.

When more than one recording channel is employed in a system, and each channel has its own test circuits coupled across the magnetic heads, the probability of error increases as well as the cost and maintenance of the additional test circuits. Further problems arise when thin film heads are used as the read/write elements. In such event, the inductance of the wire leads attached to the thin film is greater than the relatively low inductance of the thin film head itself. Thus, inductive measurements for checking operability of the multiplicity of thin film heads that may be used in data storage systems do not provide accurate testing results. Apparently, it would be desirable to provide accurate means for checking operability of write channels and magnetic heads of the thin film type in a simplified and inexpensive way.

The invention will be described in detail with reference to the drawing in which:

FIG. 1 is a block and schematic diagram illustrating the test circuit used for testing the write channels and magnetic heads, according to this invention;

FIG. 2 is a block diagram of the head short detector employed in the network of FIG. 1;

FIG. 3 is a schematic circuit diagram of the gain amplifier employed in the head short detector of FIG. 2;

FIG. 4 is a schematic circuit diagram of the threshold detector employed in the head short detector;

FIG. 5 is a schematic circuit diagram of the rectifier employed in the head short detector;

FIG. 6 is a schematic circuit diagram of the level detector employed in the head short detector;

FIG. 7 is a schematic circuit diagram of the integrator employed in the head short detector; and

FIG. 8 illustrates two waveforms to aid in the explanation of the invention .

With reference to FIG. 1, a dual mode preamplifier, according to the invention, includes a series of recording channels 1 through N and a monitor channel M forming part of a data recording and readout system. Only circuit elements of channels 1 and N and the write monitor channel M are shown, the other channels between 1 and N which are similarly constructed not being shown for convenience and simplicity of explanation.

During the read mode, the read preamplifier operates conventionally and substantially in the same manner as in the prior art. In operation, one of the data channels 1 through N is selected for activation by the application of a select signal to the base of one of the gate transistors 10A-10N. For the purpose of explanation, channel 1 containing elements identified as the A group will be selected and described as exemplary of the other data channels 2 through N. The selected transistor 10A, when activated, steers current through a current source 22, and biases the selected channel on while the other channels are biased off. As a result, a selected magnetic head 16A, which may be a thin film head or a non-center-tapped head, associated with the selected data channel 1 is energized for transducing relation with a storage medium, such as a magnetic disk in a well known manner. A balanced differential signal is derived across the head 16A, which is a relatively low level signal of about 0.5 millivolts peak to peak, by way of example. This signal is amplified by gain transistors 12A and 14A, which convert the input voltage across the head to a differential current appearing at the respective collectors of the gain transistors.

The bases of the gain transistors are connected to relatively high resistances 18A and 20A, which may be in the order of 750 ohms, by way of example. The resistors 18A and 20A are coupled to relatively low resistances 30 and 32, which may be about 2 ohms for example, in the monitor stage M. The resistance network provides a 375:1 attenuation, which appears at the input of each of the channels, and which effectively isolates the channels from each other so that there is no transfer of noise signals between the channels.

During the write mode, in accordance with this invention, the write monitor channel M is energized by the application of a select signal to the base of the gate transistor 10M. A write driver and head selection circuit 28 transmits a write signal to the selected data channel and head. The write signal that is applied to the selected magnetic head, say 16A, is processed through the gain transistors 12M and 14M of the write monitor channel. The amplified signal at the collectors of the transistors 12M and 14M is passed through the amplifier 24, that provides a differential voltage signal V1 and V2 which, in turn, is applied to the input of the head short detector 26.

Since the read preamplifier is designed for processing a relatively low voltage read signal, such as 0.5 millivolt, it is necessary to attenuate the relatively high write signal, which may be in the order of 800-1000 millivolts. The circuit configuration disclosed herein provides a high attenuation factor, which is derived from the interconnection of the 750 ohm resistors 18 and 20 in the selected data channel and the 2 ohm resistors 30 and 32 in the monitor channel. In this manner, the relatively high write signal is reduced to a level which can be processed by the dual mode read preamplifier.

The head short detector 36 of FIG. 1 is shown in block diagram form in FIG. 2. The gain amplifier 34 receives differential voltage input signals V1 and V2 from the amplifier 24. The gain amplifier 34 isolates the head short detector from the data recording channel, and amplifies the input signal by a factor of 2, by way of example.

The amplified differential signal A' and B' is fed to a threshold detector 36. The threshold detector 36 determines whether the differential signal A', B' is greater than a specified threshold voltage V.sub.T, illustrated in FIG. 8. If the signal appearing at A' or B' is greater than the threshold voltage V.sub.T, then the respective voltage outputs F or C will rise. If the signals A' or B' are less than V.sub.T, then F and C output signals do not vary. If the signal appearing at A' or B' is greater than the threshold voltage V.sub.T most of the time, the system is writing into a normal operative head. If the signals A' or B' are less than V.sub.T most of the time, this is an indication of a shorted head.

A rectifier 38 rectifies the signals F and C, and whenever either F or C is high, an output signal D from the rectifier appears as high. Signal D remains high most of the time when writing into a normal head.

The level detector 40 senses whether the signal at D is high or low relative to a detecting reference voltage V.sub.DET, and controls the level of the output signal E. An integrator stage 42 integrates the current supplied by the level detector 40, and provides a clamping function to prevent saturation. The integrated signal E.sub.I provides an indication whether the selected head is functioning normally or if the head is shorted.

The specific circuits are illustrated in FIGS. 3-7. In the detailed circuit of FIG. 3, the gain amplifier 34 includes a symmetrical voltage gain stage including NPN transistors 44 and 46 having their emitters coupled through resistors 48 and 50 of equal value. The collectors of the transistors 44, 46 are coupled through load resistors 54 and 56 of equal value. The differential signal V.sub.1 and V.sub.2 is applied to the bases of gain transistors 44 and 46, and an amplified differential output signal A', B' is produced. The gain is determined by the ratio of resistor 54 to resistor 48, or similarly resistor 56 to resistor 50. A capacitor 52 connected between resistors 48 and 50 serves to eliminate DC offsets, so that the DC voltage level of the output signals A' and B' is the same. Current sources 58 and 60 tied to a negative voltage supply act to bias the gain stage.

In FIG. 4, the differential threshold detector 36 employs emitter coupled NPN transistors 62, 64, 66 and 68. A current source 74 is tied to the emitter circuits of the coupled transistors. A resistor 70 is connected to the collectors of transistors 62 and 64, and a resistor 72 is connected across the collectors of transistors 66 and 68. The resistors 70 and 72 convert the current signal seen at the collector outputs to a voltage signal.

A source of voltage 76 supplies a predetermined threshold voltage V.sub.T or reference voltage at the bases of transistors 64 and 66. The reference voltage V.sub.T is compared to the incoming differential signal A' and B'. If A' and B' is less than the threshold voltage, then there is no signal at the output terminals 78 and 80. However, if A' or B' is greater than the threshold voltage, then a differential signal F and C will appear at the output terminals.

The differential signal F and C from the threshold detector 36 is applied to the bases of transistors 82 and 84 of the rectifier illustrated in FIG. 5. The transistors 82 and 84, which have their emitters and collectors connected, form a rectifying junction. The common emitter circuit of transistors 82 and 84 are connected to the input of a transistor 86 which supplies a rectified signal D that is a reproduction of the highest amplitude signal of the inputs F and C. Current sources 88 and 90 provide the necessary current bias.

The level detector of FIG. 6 includes a pair of emitter coupled transistors 92 and 94, and current sources 96 and 100. The rectified signal D from the rectifier 38 is fed to transistor 92, and the level detector senses whether the signal D is higher or lower than a predetermined detection level voltage V.sub.DET.

If the signal D is higher than V.sub.DET, then transistor 92 conducts with a collector current of magnitude 2I, equal to twice the current I through current source 96, and as a result a current signal E of magnitude I is drawn from terminal 98 towards the current source 96. However, if the signal D is lower than V.sub.DET, the transistor 92 cuts off, and transistor 94 conducts so that a current of magnitude I flows to the terminal 98 from current source 96.

The signal E at terminal 98 appears at the input of the integrator 42, depicted in FIG. 7. The integrator circuit consists of emitter coupled transistors 102 and 104 having a resistor 106 connected between the emitter circuit and ground potential. A clamp transistor 108 has its emitter electrode connected to the base-collector circuit of transistor 102, and to the input terminal 98, as well as to a capacitor 110 that integrates the input current.

When the signal D in FIG. 6 is higher than V.sub.DET, the voltage at terminal 98 ramps down until limited by transistor 108. If the signal D is lower than V.sub.DET, the voltage at terminal 98 ramps up until limited by transistor 104. Transistor 108 which serves as a down level clamp prevents saturation in the negative direction, whereas transistor 104 which serves as an up level clamp prevents saturation in the positive direction. Transistor 102 adjusts the level of the signal when the up level clamp transistor 104 is on and operative. By means of this circuit, the voltage at the junction 112 remains at a level between the clamp voltages V.sub.DLL and V.sub.ULL, the upper limit and lower limit clamp voltages.

The level of the integrated output signal E provides an indication of whether the selected magnetic head operating in the write mode is functioning normally or is a shorted head.

If a short or fault is present in the recording channel, the DC level of the signal (FIG. 8) disappears, but the spikes remain. In such case the voltage A', B' is below the threshold voltage most of the time, and differential signal F and C, and signal D remain at a low level. In such case, current is forced into terminal 98, and the voltage across the integrating capacitor 110 ramps in the positive direction until the upper limit clamp (ULL) prevents further positive excursion. In this condition, an error is shown to exist.

There has been disclosed a dual mode preamplifier that is useful for conventional read preamplifier functions, and for monitoring the write channel and write heads during the write mode, in a simple and inexpensive manner, without the need of additional complex circuitry. The head short detector may be used to detect the absence of write current transitions. The absence of transitions would be interpreted as a head short by the threshold detector portion of the head short detecting circuit.