Electronic Calculator Implemented in Semiconductor LSI Chips With Scanned Keyboard and Display

Electronic desk top calculators have been changed in design due to the availability of MOS/LSI chips which allow the entire system to be embodied in only one or a small number of semiconductor devices. The term MOS/LSI refers to Metal Oxide Semiconductor Large Scale Integrated Circuits; "MOS" is used interchangably with MIS or Metal Insulator Semiconductor, both terms referring generally to insulated gate field effect transistors. This technology permits large savings in manufacturing, labor and material costs and allows calculators to have operating functions not possible at reasonable cost in machines built from discrete devices or from large numbers of integrated circuits. A calculator system adapted to be implemented using only one MOS/LSI chip is set forth in co-pending application Ser. No. 163,565, assigned to the assignee of this invention, now abandoned. A feature of the calculator disclosed in application Ser. No. 163,565 is the use of a random access memory array which is sequentially addressed to operate as a plurality of shift registers; this unit provides the main data registers in a space on the chip much less than needed for shift registers of conventional design. Another feature of said application was the keyboard scanning technique.

It is a principal feature of this present invention to provide an improved electronic calculator system adapted to be implemented in MOS/LSI technology, in a minimum of semiconductor chips or wafers. Another feature is to provide an expandable system which may include optional program memory arrays and data registers. Other features include use of the sequentially addressed memory of Ser. No. 163,565 with a timing arrangement in such a manner that auxilliary timing generators are not needed, and the provision of a keyboard interface register which provides keyboard and timing information encoded for entering into the data registers or for selecting an address for the program memory. A further feature is an arithmetic logic unit which operates fast enough so that bits in the data registers may be shifted in parallel out of cells in the sequentially addressed memory array through the ALU and back into the same cells.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as further objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrative embodiment, when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a pictorial view of an electronic desk top calculator which may employ the invention;

FIG. 2 is a simplified block diagram of the calculator system of the invention;

FIG. 3 is a more detailed block diagram of the registers and part of the logic of the electronic calculator of the invention;

FIGS. 4A and 4B are representations and tables showing the make-up of the instruction word used in the system of the invention;

FIGS. 5A and 5B are timing diagrams showing the timing of various parts of the system of the invention;

FIG.6 is a representation of the keyboard layout used for the calculator of the invention;

FIG. 7 is a representation of the keyboard input matrix;

FIG. 8A represents the coding of the K information and D times in the keyboard register;

FIG. 8B is a table of the keyboard code; and

FIG. 8C is a specific encoding of one keyboard entry.

FIG. 9 is a diagram of the layout of FIGS. 9A-9W;

FIGS. 9A to 9W is a composite schematic diagram of the circuit of the "data chip" part of the system of the invention;

FIG. 10 is a diagram of the layout of FIGS. 10A-10E;

FIGS. 10A to 10E is a composite schematic diagram of the circuit of the "ROM chip" part of the system of the invention;

FIGS. 11A to 11R are detail views of certain circuits used in the system of FIGS. 9 and 10;

FIG. 12 is a detail view of a programmable logic array as used in the system of FIGS. 9 and 10.

FIGS. 13A-13D show input and output signs, cell layout, and electrical diagram for a specific programmable logic array featured in the invention.

FIGS. 14A-14B show the layout of the semiconductor wafer for the "data chip" and "ROM chip", respectively.

Referring to FIG. 1, an electronic desk-top calculator 10 of the type which may employ features of this invention is shown in pictorial form. The calculator 10 comprises a housing 11 having a keyboard 12 and a display 13. The display, in one embodiment, consists of thirteen or fourteen digits or characters, each provided by a Nixie tube, a liquid crystal display unit, an array of light emitting diodes or other display means. Ordinarily, the display would be of the so-called seven-segment or eight-segment variety, with provision for indicating a decimal point for each digit. The keyboard 12 includes the usual set 14 of number keys one through nine plus a zero key 15 and a decimal point key 16, along with twenty or so function keys 17, and twelve decimal point set keys or switches 18. A fixed decimal point position for the display 13 may be set by a thumb wheel, or a lever switch, in place of the switches 18. The function keys 17 include functions such as plus equal , minus equal , multiply.times., divide .div., clear all CA, along with a number of unique functions as will be described. Data or numbers are entered by the keys 14, 15, 16, and instructions are entered by the function keys which serve to call sub-routines from an internal stored program to execute the desired operations. Intermediate and final results of calculations are indicated on the display 13. Generally, the construction and operation of the calculator may be explained according to the block diagram of FIG. 2, but this diagram is not intended to be structurally definitive. The calculator includes a program memory 20 for storing the control program, this memory being a read only memory (ROM) comprised of several hundred or more, of multibit word storage locations. Instruction words are read out of the ROM 20 one word at a time into an instruction register 21, and are decoded and excuted by control logic 22. The control logic 22 is responsive to the fixed instruction words from the ROM 20, to the instructions entered from the keyboard 12, particularly the function keys 17, and also to the internal conditions of the calculator system. Data is stored in registers 23 which include basically a sequentially addressed random access memory organized as four data registers of sixteen digits each. The registers 23 also include two flag registers and a keyboard interface or special purpose register. All operations on the data entered into the registers 23 is carryed out in an arithmetic logic unit 24, which is of the bit parallel, serial digit type. Control logic 22 also operates a program counter 25, which is capable of addressing each of the addressable locations in the ROM 20, whereby the instruction stored in each location is read out into the instruction register. Usually the program counter is incremented by one for each instruction cycle, as controlled by timing means, so the instructions of a particular sub-routine stored in the ROM are read out in sequence. However, branch instructions appearing at the instruction register 21 are recognized by the control logic 22 and modify the sequencing of the program counter 25. Also seen in the block diagram of FIG. 2 is the visual display 13, which displays the contents of a register. Both the keyboard 12 and the display are scanned rather than continuously connected into the control logic, according to a feature of the invention.

Referring to FIG. 3, the data storage registers 23 are shown in more detail along with part of the arithmetic logic unit 24 are interconnecting data paths. No attempt is made to show the control logic, timing, or other features in FIG. 3. The calculator has four registers, 30, 31, 32, 33, for basic data storage, named the A, B, C and D registers. Each of these registers contains sixteen digits or characters, four bits per character, in binary coded decimal or hexidecimal format. Instead of the usual shift registers employed in most electronic desk-top calculators for data storage, these registers 30-33 are implemented by a sequentially addressed read-write memory of the type set forth in co-pending U.S. patent application 163,683, now abandoned, assigned to the assignee of this invention, as described below. Two groups of sixteen flags are also available with flag registers 34 and 35, also referred to as FLGA and FIGB. An eight bit special purpose register 36, or REG8, is available for keyboard interface or flag transfer in groups.

The ALU24 of FIG. 3 is a four bit parallel binary or BCD adder. Outputs 37 and 38 from A and C registers 30 and 32 are connected to "X" bus 39, and outputs 40 and 41 from B and D registers to "Y" bus 42. Although shown as one line, the outputs 37, 38, 40 and 41, as well as the X and Y buses, are acually four parallel lines representing one, two, four and eight in BCD fashion; this is true of most of the data connections of FIG. 3. A predefined constant "N" can be logical "OR'ed" with the Y bus 42 at an input 43, or four least significant bits from REG8 register 36 may be likewise OR'ed with the Y bus at input 44. The inputs to the ALU24 at the X and Y buses thus may include the outputs of any of the main A, B, C or D registers, and REG8 contents, and a constant N. The ALU24 generates a carry/borrow signal which can be used to set a COND flip flip 45 to zero, and also for the arithmetic operation.

The output 46 of the ALU 24 is a T register which may be connected directly back through an S bus 47 by a line 48 with no shift or connected through a one bit delay 49 to the S bus 47 to produce left shift. Right shift is provided by taking the logical OR in a gate 50 from inputs 51 and 52 from the X and Y buses. The left and right shifted inputs 53 and 54 are applied to the S bus 47, the output 55 of which is connected as inputs of selector gates 56, 57, 58 and 59 for the A, B, C and D registers. Other inputs to the selector gates 56-59 include a recirculate path for each register; the recirculate paths include a one bit time or one state time delay 60 for each register. As will be described, the A, B, C and D registers do not "shift" in the usual sense of shift registers while recirculating, but instead a bit is taken out of one location in the SAM and returned to the same location. Also, the output is not just at one end as would appear in the block diagram of FIG. 3, but instead is from both ends. Recirculate and exchange are done at one end and ALU operations and shifting is done from the output at the other end. The selector gates 56-59 are thus actually several gates. The contents of the A and B registers may be exchanged, and likewise the contents of the C and D registers may be exchanged; for this purpose, the delayed output of the A register 30 is connected by a line 61 to the selector gate 57, and the output of the B register 31 is connected by a line 62 to the input of the A register 30. Similar cross connections 63 and 64 are provided for the C and D registers.

The A and B flag registers are each sixteen bit binary registers located in the SAM; the flags are one bit binary values which are used by the ROM program to store status information which can be examined or changed at a later time, typical flags being minus sign, error, overflow, etc. Addresses of zero through fifteen are used to access the flags. The A and B flags which have the same address are said to be adjacent, and can be exchanged, as indicated by a connection 70 in FIG. 3. Flag logic 71 permits flags to be recirculated by paths 72 and 73, and also permits entering information from the 8 bit register 36 into the flag registers 34, 35 by a line 74. Further, information in the flag registers may be entered into the 8 bit register 36 by a connection 75 from flag logic 71 to a selector gate 76 for the register 36. Other inputs to the selector gate 76 include a connection 77 from the T register output 46 of the ALU 24, an encoded keyboard K-D entry 78, and a digit time entry 79. The 8 bit register may also be recirculated by a path 80.

Each instruction word stored in the ROM 20 and read into the instruction register 21 consists of thirteen bits, I.sub.0 thru I.sub.12. If the word is for an operation, the left most bit I.sub.12 will always be a 1; if the word is for a branch, I.sub.12 will always be a 0. The formats for operation or branch are different, and are seen in FIG. 4A. The format for instructions includes: a three bit S or .SIGMA. field, I.sub.0 thru I.sub.2 ; a four bit R field, I.sub.3 to I.sub.6 ; a subtract field, I.sub.7 ; a four bit M field or mask field, I.sub.8 to I.sub.11 ; and the instruction/branch indication I.sub.12. The format for branches includes: an eleven bit address field I.sub.0 to I.sub.10 (two bits being chip select and nine being a ROM address); a one bit condition field I.sub.11 ; and a one bit instruction/branch indication I.sub.12. The table of FIG. 4B gives the binary words used for S, R and M fields, for each possible value of S, R and M; thus, M5 would be 0101, M15 would be 1111, etc.

If I.sub.12 is zero, the instruction word is for a branch, and the branch is conditional depending upon the value of bit I.sub.11. If I.sub.11 is zero, a branch will be executed if a condition code, COND, is zero; if I.sub.11 is one in the instruction word, a branch is executed if COND is one. The address field I.sub.0 to I.sub.10, contains the ROM location or address, which is stored in the program counter 25 if the branch is taken. A branch will set the condition code COND to "1" if the next instruction to be executed is not a branch.

If I.sub.12 is one, the instruction word is for an operation. Arithmetic and shift instructions are defined for an M field of Mo to M12, or binary 0000 to 1100 appearing on M.sub.a to M.sub.d as seen in FIG. 4B. This MO to M12 field defines thirteen digit masks as shown in Table I at the end of the specification, where the masks are described by state times S0 to S15 which will be explained later. A constant N, also seen at 43 in FIG. 3, is generated at a certain state time along with the digit mask. The inputs and operation of the ALU 24 are specified by the R field and SUB. The input paths to the A, B, C and D registers, selection gates 56-59, are specified by the .SIGMA. field. Again for the digit masks MO to M12, Table I, the X and Y inputs to the ALU 24 and the operation performed are set forth in Table II for the various possible R fields. The capital letters, A, B, C, D in the Table indicate the main registers. Table III shows the operations performed for various .SIGMA. fields. As may be seen, the hardware or control logic 22 responds to predetermined combinations of 0's and 1's in the instruction word to interconnect the system as desired and to perform the needed operations.

The entire system operates on two externally provided clocks .phi..sub.1 and .phi..sub.2 as seen in FIG. 5A, and two internally generated clocks P1 and P2. The frequency used in 250 KHz for .phi..sub.1, .phi..sub.2. The clock generators may be conventional and are not shown herein.

One set of clocks .phi..sub.1, P.sub.1, .phi..sub.2, P.sub.2 is referred to as a state time, and represents the time for one bit from each of the main registers A, B, C, D to be operated on in parallel by the ALU, etc. The BCD arithmetic used in the invention requires one full set of clock pulses for each digit, so sixteen sets or state times are needed to perform arithmetic operations on all sixteen digits in a register. Sixteen state times represent one D-time or instruction cycle, as seen in FIG. 5B.

Individual address lines in the registers 23 are energized only for three of the clocks .phi..sub.1, P.sub.1, .phi..sub.2, rather than all four; these groups of three are also referred to as state times S0 to S15 as seen in FIG. 5A. A feature of the invention is the use of the same state times as generated to operate the address lines of the SAM register 23 to operate or time the remainder of the system.

D times generated directly from state times S0-S15 are used to scan the keyboard and the display. As seen in FIG. 5B, the D times count down, D15, D14, D13 . . . D1, while the state times count up, S0, S1, S2 . . . S15; this feature aids in the zero suppression technique since leading zeros to be suppressed are on the left or MSD first while the ALU must operate from right to left or LSD first. There are fifteen D times and sixteen state times.

One embodiment of the invention uses a keyboard as seen in FIG. 6. This keyboard includes natural number keys 14 for one thru nine, a zero key 15 and a decimal point key 16. Twenty function keys 17 are included, as will be described; these are all push-bottons which stay closed only so long as depressed by the operator. In addition, a number of switches are included, such as mode switches 19 and rounding switches 90. The decimal point position is set by switches 18 which may be individual buttons as seen, or a thumbwheel; a floating point switch is also included.

A natural number key 14-15 enters the number punched into a register and displays it. The decimal point key 16 enters a decimal point. Only the first decimal point is protected.

The function keys 17 cause an internal change in the calculator such as performing an arithmetic operation, remembering an arithmetic operation, clearing registers, or changing the contents of registers. The specific operations caused by the function keys is set out in Table IV at the end of the specification.

The switches 18-19 are functional controls, like the function keys 17, but once they are closed they remain closed until manually opened. The decimal switches 18 enter a desired number of decimal places for the display at the end of a addition or subtraction calculation; multiplication and division is done in floating mode. A separate floating switch will override any decimal switch that is down. If no decimal switch 18 is set, the machine will always default to the floating mode.

The mode switches 19 include a .SIGMA. or summation switch which causes memory accumulation to occur when or key is pushed. A constant switch K designates a constant multiplicand, i.e., the number entered or the result acquired (product or quotient) before the last multiply command is stored. In the case of division, the number entered immediately after the last divide command, is the constant divisor.

The rounding switches 90 permit selection of the rounding operation in three modes. Round up, RU or an arrow pointing up, means if the quantity to be discarded is non-zero, a one is added to the LSD retained. Round off, or 5/4, means if the quantity to be discarded is half or more than half, a one is added to the LSD retained, otherwise the LSD retained is unmodified. Round down, RD or or an arrow pointing down, means that the number is merely truncated below the LSD to be retained, and any quantity is discarded.

An overflow lamp near the display is turned on when the interger part of the result contains more than twelve digits. If the number of decimal places cannot be displayed in full, but the integer part of the result is less than twelve digits, this is not truly overflow, but is referred to as pseudo-overflow. For example, if the decimal point is selected at 5, and the calculated result is thirteen digits, or 123456789.1234, then the display drops the last "4" and shows 123456789.123 which should be 123456789.12340 according to the DPT setting; this is pseudo-overflow.

An intermediate result, as the term is used later, means the result of an intermediate calculation performed, not from a += or -= key, i.e., not from any "equality" function key. For example, if the following is punched--a.times.b.times.c.div.d.div.e+=; then an intermediate result of ab will be obtained after the second "X", an intermediate result of abc after the first .div., and an intermediate result of abc/d after the second .div.. A final result is obtained after +=, or abc/de in the example.

The decimal point mode (fixed point) and floating mode determine the size of the display (i.e., the number of decimal places displayed). They do not affect the integer part of the number. Insignificant zeros (trailing zeros) may be added or deleted to satisfy the number of decimal places displayed. For example, if the result is 12.411733410 and the round down switch is depressed, DPT 5 on switches 18 will cause 12.41173 to be shown, DPT 7 will show 12.4117334, DPT 10 will show 12.4117334100 or padded with one insignificant zero, DPT 11 will show the same as for DPT 10 and will be in pseudo-overflow since the decimal point will be at ten instead of eleven, and F or floating will show 12.41173341 losing one trailing zero.

Rounding the number determines only the value of the LSD displayed depending upon the value of the MSD deleted. DPT mode and rounding are independent of one another but bear a certain relationship. "Rounding" means doing what the rounding switch says; "no rounding" means truncation of the insignificant decimal places. In F or floating mode, no rounding occurs for intermediate or final results; in fixed point mode, no rounding occurs for intermediate results, but the final result is rounded according to the switch 90. An intermediate result is always in floating mode, and floating mode is always no rounding.

Table V gives operation examples for the calculator to be described, with the ROM program to be set forth. Other operating sequences are possible with different programs in the ROM. In the examples, E means lighting an entry overflow indicator lamp near the display on the calculator face. A letter or number within a rectangle means this is a final result.

In FIG. 7 there is seen a fifteen by seven matrix showing the keys from the keyboard arranged as scanned by the fifteen digit timing D1 to D15 signals, and as sensed on the seven outputs at KN to KT, from which keyboard information is entered into the system. If a "1" voltage appears on KQ at D7 time, then the X key is depressed, etc. The combination of a digit time and a sense line identifies a key, and these fifteen and seven line items are binary encoded within the machine to appear as four and three bits respectively; FIG. 8A shows the format for loading keyboard and digit time information into the register 36, with the code of FIG. 8B being used for K information. If a key at D10, KP is down after a keyboard scan, the register 36 will contain the word of FIG. 8C.

The system will now be described in detail with reference to FIGS. 9 and 10. The system was designed to be implemented with two MOS/LSI chips, one being the data chip of FIG. 9 and the other being the ROM chip of FIG. 10. All of the system is in the data chip except the ROM 20 and the program counter 25 which are in the ROM chip. The instruction register 21 is duplicated, in both chips.

Referring to FIG. 9U, the instruction register 21 is seen to include a pair of inputs 200 and 201, also labeled PIN 27 and PIN 28, which receive the instruction word serially in two parts from the ROM chip. The instruction word of 13 bits is broken up into seven bits coming in on the input 200 and six bits coming in on the line 201; this is merely to save time in transferring the words serially, and has no other significance in the logic of operation of the system. The instruction word is fed from the inputs 200 and 201 through two selection gates 202 and 203, which are controlled by several inputs. One pair of inputs 204, called CONA and CONA, mean that an "inhibit increment" command is or is not present. When present, a new word is not accepted, but instead the one in the register 21 is recirculated. Another input 205, when present, causes the instruction word to be blocked from reaching the instruction register so that all zeros will be produced in the register; this is when a P-REG or program register instruction is sent to the ROM chip. The input on line 205 is obtained from a P register output circuit, FIG. 9 "0", to be described below. Other inputs 206 and 207 are for recirculation from the instruction register 21, so the instruction word in the register will continue to recirculate when other conditions are met. The outputs of the gates 202 and 203 are fed by lines 208 and 209 serially into inputs of a thirteen stage recirculating shift register which is actually broken up into two separate registers of seven and six bits. The register is of conventional form, employing two inverters and .phi..sub.1 -.phi..sub.2 switches in each stage. A fourteenth stage 210 is added at the end to introduce a delay so both parts of the register will be operating in synchronization. The thirteen outputs 211 of the instruction register 21 are labeled, as described elsewhere: Inst., M field, Sub, R field and .SIGMA. field. The complements of these thirteen items are also included, so a total of twenty-six lines go into a control matrix 212, FIGS. 9R and 9S. The instruction word is being read in or is recirculating serially in two parts, so it is only at a particular time that the word in the register will have any meaning; thus, the contents of the register 21 are applied to the control matrix only when an output appears at a gate 213. One input to the gate 213 is a time signal S14 or state time 14 on a line 214. The time S0 to S13 is used for the register 21 to be filled in an instruction cycle. The state time S15 is occupied by the delay in decoding in the matrix 212. A new instruction word is thus presented for operation at the end of an instruction cycle, i.e., one instruction cycle is used to load a new word, then the operation commanded by that word can be carried out while another word is being loaded.

The output of the instruction register goes to a control matrix 212 and also to a sigma and flat matrix 220, an R decode matrix 221, and M or mask decode matrix 222, as well as to other places as will appear. Each matrix is a programmable logic array of well known construction, described later with reference to FIG. 12. A vertical line such as a line 225 at the lower edge of the control matrix 212 represents a P diffusion, a horizontal line 226 (one of the .SIGMA. lines) represents a metal stripe, and a circle 227 at an intersection represents a gate or thin oxide so that an MOS transistor is created. The other P diffusion line for drains is not shown. In some of the matrixes of FIG. 9, the P diffusion lines are horizontal and the metallizaion lines are vertical, of course. As an example, the transistor 227 formed at the intersection of lines 225 and 226 is part of a NOR gate, with the other inputs for the vertical line 225 being at .SIGMA..sub.b, .SIGMA..sub.c, Ma, Mb, Mc, Md and Inst.; the presence of any of these changes the output on line 228, which incidentally is one of the inputs to the inhibit increment logic.

The R field of the instruction word is connected directly to inputs 230 of R decode matrix 221, FIG. 9M. That is, even though the Ra, Rb, Rc and Rd lines pass through the control matrix 212 at this point, the R field appears unaltered at the inputs 230. In addition, the Ra-Rd lines are inverted so that Ra-Rd inputs 231 are also applied to the decode matrix 221. The four output lines 232 from the R decode matrix go to a set of sixteen gates 233, FIGS. 9K, L, M, which determine what main register output goes to the ALU. Thus, in order for the outputs 37 of A register 30 to pass through the gates 233, a line 234 in the R decode output 233 must be on. This would be true for various combinations of presence and absence of the signals in the R field of the instruction word, depending on how the decode matrix 221 is programmed.

The .SIGMA. field lines 240 are applied from the output of instruction register 21 to inputs of sigma and flag matrix 220, FIG. 9c, along with subtract or Sub line 241, and their complements. This matrix 220 receives the outputs from the flag registers 34 and 35 which appear at inputs 242 and 243 to the matrix 220, and also these inputs are inverted as are other inputs to the matrix. Another input 244 to the flag matrix is from a line 244 on which the complement of M15 appears. M15 is decoded at a logic gate 245, FIG. 9M, which receives as inputs the mask or M field, Ma-Md, from the instruction register 21. M15 is an indication that a flag operation is commanded, and is used in several places. Other inputs to the flag matrix include a flag mask indication on a line 246 which is generated at logic gates 247 as will be described. An input 74 to the flag matrix 220 is from an output of the recirculating special register 36 or REG8. Also, the lines 240, the Sub line 241, and the complement of M15, on line 244, all are connected as inputs to gate 248, the output of which is an input 249 to the flag matrix.

The function of the sigma and flag matrix 220 includes decoding the .SIGMA. field from the instruction register 21, and also controlling recirculation of the flags in the flag registers 34 and 35. The decoded .SIGMA. outputs from the matrix 220 appear on groups of lines 255 and 256, FIG. 9B, after going through logic gates 257. One input 258 to these gates 257 is an output from the mask decoder 222, and functions as a digit mask to specify what part of the data word is operated on, i.e., mantissa or what.

The decoded .SIGMA. outputs 255 represent an instruction (or its complement) to transfer data between A and B registers or between C and D registers. The decoded .SIGMA. outputs 256 represent a recirculation command for A, B, C or D registers. The outputs 255 and 256 are connected to the sets of selector gates 56, 57, 58 and 59 on the left-hand side of the SAM, FIG. 9A, to control recirculation or exchange of data in the main registers. These outputs 255 and 256 are further connected to a .SIGMA. decode array 259 which is another programmable logic array (with saturated loads) that produces four outputs 260 to control further sets of selector gates 56, 57, 58 and 59 for the A, B, C and D registers on the right-hand side of the SAM, FIGS. 9K, L, M; these selector gates control which one of the main registers receives the output 55 from the T register 46 in the ALU 24.

Other outputs from the flag matrix 220 include an output 260 which is inverted and connected back to a condition circuit 261, FIG. 9u, as one of the inputs to a gate 262 to indicate that two flags are the same. The condition circuit will be described later. Another output 263 goes to a gate at the chip output PIN 6, FIG. 9A, for comma indication and also to a set of gates 264 which control flag recirculate or exchange. An output 265 goes to the gates 264 and to selector gates for PIN 11 for flag A or FLGA output from the chip. The gates 264 also receive an output 261A from the matrix. The outputs of flag A and flag B registers, from the complements of lines 242 and 243, are connected through the flag matrix 220 and logic gates 266, FIG. 9H, to provide the connection 75 to the selector gate 76 for the 8 bit register 36, FIG. 9V; this input provides the flag register input to the register 36 or REG8. One or the other of flag A or flag B registers is selected by the Sub line 241, since Sub and its complement are inputs to gates 266.

The mask decoder or M decode matrix 222, FIG. 9M, receives the M field and its complements from lines 270 at the output of the instruction register 21, and also the Inst. bit on line 271. If the Inst. bit is a zero, the instruction is a branch rather than an operation so no output commands are to be given by the mask decoder and to accomplish this circles are seen at every intersection for this input line 271 in the matrix 222. Mask outputs include a set of four lines 272 which provide a constant or N input to the ALU 24, or the input 43 to the Y bus of FIG. 3. Other outputs include the digit mask 258 going to the .SIGMA. selector gates 257 as mentioned above, and the other end of this output is also connected by a line 273 to a logic group 274 which controls in part right shift, left shift, carry/borrow, reset, as will be explained; this permits the part of the word to be right shifted to be controlled by a mask. Further inputs to the mask decoder 222 are outputs 275 and their complements, from a push-pull matrix 280, FIG. 9G; these comprise encoded state times, or S0 to S15 encoded on four lines. Further, inputs to the mask decoder 222 from the push-pull matrix 280 include a decimal point or DPT indicator on line 276 which shows the line to be activated at S15, meaning S0 will be the programmed DPT time since the voltage on line 276 is gated into the matrix 222 on .phi..sub.2 and lasts until the next .phi..sub.2. Line 277 likewise defines the position of the exponent, here S0 or actually S1 time. And, line 278 defines the mantissa as S2 through S14 by circles at address lines S1 to S13.

The main A, B, C and D registers are contained within a random access memory arrangement 23 which is operated in a manner similar to a set of shift registers, as set forth in co-pending application Ser. No. 163,683. The SAM 23 includes an A register 30 which is comprised of four separate rows A.sub.1, A.sub.2, A.sub.4 and A.sub.8, in BCD format. Likewise, the B, C and D registers each comprise four rows B.sub.1, B.sub.2, etc; these are interleaved to save space in interconnecting the registers on the chip. Each row includes sixteen cells 300 or one for each digit or character, with each cell being a conventional three-transistor RAM memory cell. All of the memory cells 300 in the SAM are exactly the same, and there are a total of 16.times.16 or 256 cells in the main A, B, C and D registers. The SAM also includes two flag registers 34 and 35, which are sixteen bit rows, or thirty-two more cells, for a total of 288 cells in the SAM. Vertical lines in the SAM are address lines 301 of which there are seventeen, these bit lines being driven by a commutator 302, FIG. 9E, made up of a seventeen stage (or sixteen and one half stage) ring counter which circulates a zero in synch with state times. Indeed, the commutator 302 generates the state times S0-S15 for use throughout the system. Only one of the address lines 301 is energized at any one time, and the energized line shifts from right to left in the order S0, S1, S2 . . . S15, S0, one at a time, producing the signals seen in FIG. 5A. Each stage of the commutator comprises two inverters 303 and 304, and two switches 305 and 306 driven by .phi..sub.2 and .phi..sub.1. The outputs of the commutator stages are coupled thru inverting gates 307 to the bit lines and to an OR gate line 308 in a push-pull matrix 310. A recirculate signal is coupled back to the beginning by line 308 when the zero propagating thru the commutator passes S14; thus, the S0 line of both edges of the SAM will be energized at the same time.

On top and on bottom of the SAM 23 are located a pair of push-pull matrixes 310 and 280 which function to generate a number of timing signals, as mentioned above. The combination of the SAM with the push-pull matrixes is an important feature of the invention. Four lines 312 as outputs of the matrix 310 provide an encoded indication of the sixteen state times S0-S15 for conveying to the ROM chip thru outputs SA, SB, SC, SD. Non-inverting buffers, not described in detail herein, are in series with these outputs. The lower push-pull matrix 280 includes seven output 275-278 to the mask decoder 222, as mentioned above, and also an output line 320 which generates an S14 indication which is gated at .phi..sub.2 and then used to generate an S15-.phi..sub.1 time indication in a gate 321. S15-.phi..sub.1 is used to indicate the beginning of an instruction cycle in generating digit or D times; this indication is used to open a set of gates 322 which are in series with a set of four lines 323 connected to the lower four output lines of the push-pull matrix 280 on which appears S0-S15, the sixteen state times encoded on four lines. These encoded state times are strobed at gates 324 by the output of a gate 325 which receives .phi..sub.2 and a strobe signal as inputs. The strobe signal on line 326 is obtained from an output 327 from a programmable strobe counter as will be described. A strobe signal appears on line 326 every fifteen state times; so the encoded S time number allowed through the gate 324 will count backwards. Two inverters are in series with each of the lines 323; the inverted output of three of the lines and twice inverted output of the forth produces a D1 indication at a gate 328, the output 329 from this gate being used to initiate a set of display scans in a display scanner as will be described. Encoded digit timing is provided on the lines 330 which are the state times from lines 323 as allowed through by the strobe .phi..sub.2 gate 324 and S15-.phi..sub.1 at gate 321. Encoded state times are available at this point on lines 331. The state and digit times are used in several places as will be described.

The lines 330 or D time output will never read zero. Fifteen D times as seen in FIG. 5B, while the S time cycle through sixteen states. A strobe occurs every fifteenth S time. The lines 275 in matrix 280 are programmed to read out a number in binary which is one ahead of where the "0" is on the address lines; so, when the S0 line is actuated, the lines 323 are reading out a one instead of zero. This is seen in FIG. 5C, which is a table of when the gate 324 opens, when the gate 322 opens, and what appears on the lines 323, 319 and 330. No zero will be read out on lines 330; a zero will appear on lines 319 at S15-.phi..sub.2 and will stay there until S14-.phi..sub.2, but during this time S15-.phi..sub.1 will not have occured to open the gates 322, thus the zero will not reach lines 330.

Another output from the matrix 280 is a line 332 which provides an input DBLK or digit blank to the output NAND gates of the display scan. The timing signal DBLK on line 332 begins at S1 and ends after S14, for each instruction cycle. This functions to blank the display during S0 and S15, i.e., the display is activated only S1 to S14. This is needed for some types of displays.

The operation of the SAM will now be described. When an energizing voltage or "0", a negative voltage, appears on the S0 address line, all of the MOS transistors 340 (looking now at the S0 cell for the B4 row in the B register) which act as the output switches for the memory cells 300 in the S0 vertical column will be made conductive, so the gate storage capacitor of a cell will, if it is charged negative, cause the transistor 341 of the cell to be also conductive, and the output line 342 will be grounded. Thus, if an "0" is stored, a "1" will appear on output line 342; "1" is ground or V.sub.ss, "0" is a negative voltage or V.sub.DD. This output line 342 is inverted at 339 so the output line 40 will be in "false" rather than "true" logic; bits are stored in false or complementary logic. The output from the left-hand end of the line 342 goes into a one-bit delay circuit 60. Each one-bit delay includes two inverters and .phi..sub.1, .phi..sub.2 switches. Depending upon the settings of the .SIGMA. select gates 57, etc., this bit can be either recirculated, or passed through the ALU, left-shifted, right-shifted, etc. If the bit is to be merely recirculated the gates 57 are set by the then-present instruction word so it will pass through a complex gate 343, 344 to appear inverted on line 345, delayed by one and one half state times; that is, the bit leaves its storage capacitor on .phi..sub.1 of a given state time, that state time proceeds through .phi..sub.1 -P.sub.1 -.phi..sub.2 -P.sub.2 as in FIG. 5A as the bit propogates through the delay 60; the S0 address line becomes de-energized or goes to ground at the end of .phi..sub.2, and S1 goes negative on .phi..sub.1 of the next state time as the commutator 302 switches to the next stage to the left. On .phi..sub.2 of this next state time, gate 343 is enabled by .phi..sub.2 which is one of its inputs, so the bit can proceed to line 345. Back at the cell; the transistor 346 is now conductive, and the bit will be re-entered into the same cell it came out of. All bits in all cells 300 of this first vertical column S0 will be recirculated or refreshed during S0-S1 time, during every cycle, unless they are being transferred or operated on in the ALU, or shifted. If the bits in B register are being transferred to the A register, the gates 56 and 57 are activated by the decoded .SIGMA. field appearing on lines 255 and 256 in such manner that the bit on output line 342 will not go through gate 343 but instead will go by line 347 through gates 348 and 349 to A4 input lines 350. As before, when line S1 comes on in the next state time, the bit will go back into a memory cell, but this time it will go into cell 351 in A4. In this manner during one instruction cycle or digit time, all of the sixteen bits in the B register may be transferred one at a time into the A register. The bit may instead go through the ALU; if the B line of the output lines 232 from the R decode matrix 221 is on, the bit will go through a complex NOR/NAND/INVERT gate 352, 353 to Y4 bus 42. The gate 353 can also pass a bit on line 354 if a constant N is to be entered into the ALU from lines 272, as described elsewhere; in such case the gate 352 would not pass the bit from B4. The bit on Y4, line 42 goes through the bit 4 path of the ALU 24 and the bit 4 path of the carry/borrow circuit, to appear on an output 355. Also, the bit could go into the T register 46. The output line 355 goes into the F4 input of a BCD corrector matrix FIG. 9Q, as will be described, from which it appears as an output 356 which goes into a left shift circuit 49. If neither right or left shifted, it appears on T4 line 357 and then back through one of the .SIGMA. selector gates, the B4 gate 57 as controlled by decoded .SIGMA. lines 260, and through a right shift control gate 358 to reappear on line 345 and be re-entered into the same cell via the transistor 346, since S1 line is now on. The time required for this path is again one and a half state times. The gates labeled 57 and 358 are actually part of a complex open-drain NOR/NAND/INVERT gate, rather than being separate.

The flag registers 34 and 35 operate in a manner similar to the A, B, C, D registers, except that the data in these registers cannot go through the ALU. Output from flag register A on a line 290, and output from flag register B on line 291, go into the flag matrix 220 via 242, 243 and inverted lines. Gates 292 to horizontal lines 293 provide a recirculation path to matrix outputs 263 and 265 as mentioned above. To swap or exchange a bit in flag A with a bit in Flag register B, lines have gates on the matrix output which are reversed, so exchange of flags is accomplished within the matrix, meaning that a proper combination of .SIGMA., Sub, and FMSK inputs will determine to the matrix whether bits are recirculated or exchanged. Other inputs to gates 264 are the outputs 295 and 296 which function to clear all A flags or clear all B flags when a certain combination of .SIGMA. and Sub fields exists, along with inverted M15 on line 244.

All of the input and output lines for the SAM are precharged to V.sub.DD for each state time. All output lines such as line 342 are precharged at P2 by switches 297, FIG. 9E. During P2, all address lines are off, as seen from FIG. 5A. All input lines are precharged at P1 by switches 298. Significant input information does not have to be present until .phi..sub.2 of each state time, so precharging at P1 does not interfere with the data. Precharging provides a DC power saving.

The left shift circuit 49 functions to add a one state time or one bit delay to produce left shift. The control for left shift is a pair of lines 360 going to comples NOR/NAND/INVERT gates 361. When not energized for left-shift, the path of the bit on line 356 is via line 362, on which it appears at .phi..sub.1, and no delay occurs; but where energized for left-shift, the path via line 362 is closed, and the bit is delayed until P2 before reaching line 363 then is allowed to pass through the lower part of the complex gate 361 at the next state time. The bit will then follow the same path as before, i.e., T4 line 357, .SIGMA. select gate 57 and gate 358 to B4 input line 345; however, the S0 and S1 bit lines have by now both gone off, and S2 is on, so the bit will be entered into memory cell 364, or the next one to the left.

Right shift occurs when a right shift command appears on a line 365, which goes to a right shift selector gate 366 which a NOR part of a complex gate. The bit described above, read out from B4, at the beginning of S0, goes through the path 342, 40, 352 and appears at the output of gate 353, from which it appears as an input 367 to gate 366. This gate is enabled. So, rather than being delayed one and a half state times, the bit appears immediately on B4 input line via gate 358; since S0 is still on, rather than S1, the bit cannot be re-entered into the same cell. Instead, the bit will be right shifted, and in this case, lost or discarded, because there are no cells to the right. If the bit had come out of one of the centrally located cells, it would go back into the one on its right during the same state time.

The shift commands are generated on a line 370 at the output of R decode matrix 221 when a predetermined combination of R inputs exists, in combination with the subtract command on line 371 which is derived via line 241 from the instruction register 21. Also, the digit mask on line 273 is an input to logic 274, and state 0 time from address line So in the SAM, via line 369. The logic arrangement 274 produces the right shift enable on line 365 and the left shift commands on lines 360, and also disenables the subtract command at a gate 372 via a line 373. The subtract instruction from the instruction register cannot be used directly because it also determines left shift and right shift.

The special purpose register 36, FIGS. 9T, V, W, operates as a recirculating shift register. It is comprised of seven conventional shift register stages 380, and one bit is provided in the output of selection gating arrangement 76. The upper four of the stages 380 can recirculate internally via paths 381, as determined by SCAN and SCAN control inputs 382. The lower three stages 380, which are the first three stages of the register, cannot recirculate internally, but the entire register can recirculate. Data from selection logic 76 may be entered into the lower three stages, serially, via a line 383 when the entire register is recirculating via a path 384, and an add-1 command can be inserted at this path in the appropriate time slot by add-one logic 385. The add-one logic receives an input 386 from control matrix 212 upon the occurrence of the appropriate instruction word, and also receives a timing signal via line 387 derived from S14 line 214. The input 386 from matrix 212 is also time related due to SC and SD inputs 376 and 377 which are applied to the matrix along with their complements. These are obtained from push-pull matrix 280; only SC and SD are needed since the time-related outputs of the control matrix 212 are all in quarters of a D time, i.e., four or eight S times.

Other possible inputs to the register 36 include the T register output from the ALU appearing serially on line 388 and going into the selection gates 76 via a line 389. Also, the serial output of D register or digit register 390 may be applied to the gate 76 via a line 391. The command for entering the D register into the 8 bit register 36 is applied to selection gate 76 via a line 392 which is an output from the control matrix 212. This output 392 occurs upon a selected instruction word, and is time related due to the SC and SD inputs to the matrix. External imputs may also be entered into the register 36 via input line 393, and the register outputed serially via line 394, but these connections are not used for the particular system described herein; external input would be controlled via line 935 from the control matrix 212. Data from the flag registers is entered at an input 396 which is the same as line 76 of FIG. 3.

Keyboard "K" information is entered into the register 36 in parallel to the lower three bits or stages via lines 397 from a keyboard encode matrix 400. The seven parallel K or keyboard inputs to the chip are provided by PIN 18 to PIN 25, which are applied to latch circuits 401 that function to hold a given key input for one D time or instruction cycle. The seven latch circuit outputs are encoded to three lines by the matrix 400, which is a programmed logic array. The keyboard is strobed, or the latches 401 set, by a timing signal on line 402 which is connected thru a delay arrangment 403 to the timing line 387, as was derived from S14 at line 214. In this manner, once every instruction cycle the K lines will be looked at and whatever they read will be entered into the latches 401 and a three line encoding of this is available on lines 397 to be entered into the lower three bits of special register 36.

A direct output from the keyboard KQ input latch 401 via line 404 provides hardware clear; the "clear all" key is thus connected by this path to by-pass everything so if the machine is stuck in a program loop and cannot scan the keyboard then the unconditional clear operation will still work. The line 404 along with D15 time on line 405 provide this function as inputs to a gate 406 in the P or program register output circuit as will be described.

When encoded keyboard data is coming into the lower three bits of register 36 in parallel via lines 397, the upper four bits recirculate upon themselves via 381 under control of commands on lines 382 from the control matrix. The four bits in the upper stages would be encoded D times from line 391, so a seven bit word is provided in the register which defines the keyboard input by D's and K's.

Four bits may be conveyed in parallel from the register 36 to the Y bus of the ALU 24 via lines 410, at S15-.phi..sub.2 under control of gate 411, the lines 410 go into selector gates 412 which are controlled by an output 413 from the control matrix 212 and another command on line 414 from the left-right shift logic 274. The other output from register 36 is the line 74 going to flag logic 220 and thus to the flag registers.

The register 36 is used mainly for interfacing with the keyboard, but it also may be loaded from the flag registers, from the ALU, or from the digit time register, and it may be incremented by one. The contents of the register may be sent to the flag registers or the Y input of the ALU.

The D register 390, FIG. 9I, receives the fifteen encoded D times or digit times in parallel on input lines 330 encoded in binary, and a delayed S14 time on input line 415, to drive a four stage shift register 416, from which D times are read out serially in four bits, on the line 391. The recirculation in the four bit register is under control of .phi..sub.1 and .phi..sub.2 ; a complete read out occurs four times within an instruction cycle, once very four state times, then a new D time is entered by lines 330.

One use made of the serial D time output is in a decimal point comparator 420, which has the D time output line 391 as one of its inputs and an adjusted decimal point or DPT value on line 421 as another input, and functions to compare the four bit number appearing serially on one line to the four bit number appearing serially on the other. The remaining input to the DPT comparator is an S15 time signal on a line 422. The comparator circuit includes a latch 423 which latches on when the DPT value and the D time is the same, and this produces an output via 424 which goes to PIN 5, DPT. This output is used by the display to energize a decimal point indicator at the selected digit.

The adjusted decimal point indication on line 421 going into the comparator 420 is generated in DPT adjustor circuit 430, which receives one input 431 from the push-pull matrix 280 and another input 388 from the T register. The line 431 has a recurring four bit number appearing serially on it, as programmed in the push-pull matrix; in the embodiment shown, this four bit number is a three, or 0011 in binary, and it is repeated four times every instruction cycle. The circles on address lines (intersections of line 432) S0, S1, S4, S5, S8, S9, S12 and S13 indicate that a 1 of produced on the line 432 at these S times, thus reading out "1-1-0-0-1-1-0-0 . . ." This part of the matrix is thus programmed to generate a constant binary number 0011, and this constant is added to a binary number received a line 388 from the T register 46. The T register output is also a four bit serial number, as derived in the ALU, and in this case would be the position of the decimal point. The number "3" is added because the first two places are used for exponent and DPT in the main registers, and the DPT indicator on line 424 should appear before the digit for which the DPT is reached in the MSD to LSD display scan of D scan. So, if the number in the T register says the DPT should appear in the fifth place, as to display 1234.56789, a constant "3" added to this makes the DPT indicator to appear at output 424 at D8 rather than D5.

A comparator 440, in FIG. 9N receives, as one set of inputs, the R field on lines 441 from the instruction register; a flag operation occurs only when M15 occurs and this is present on line 244 as one input to logic arrangement 442, the output of which also appears as input lines 443 to the comparator 440. The complex logic gates 442 receive state times from lines 331 as one set of inputs, and receives D times from lines 330 as the other set of inputs. The output 443 of logic 442 is encoded state times when M15 is present, i.e., a flag operation is commanded, and is D times at all other time. The output 445 of comparator 440 will be a comparison of a particular flag from R field and a particular state time, and this goes into logic gate 247, the output 246 of which is the flag mask input to the flag matrix 220. The other input 444 to the gates 247 is an indication from control matrix 212 which means data from register 36 is being put into the flag registers. Flag indication M15 from line 244 is also applied to gates 247. The output of the comparator 440 is also applied by a line 446 to gate 447 going to the "inhibit increment" logic.

A connection from PIN 30, FIG. 9U, to the ROM chip functions to prevent or inhibit the program counter 25 from being incremented--this is referred to as CONA or inhibit increment. This command is generated by a complex gate 435 which receives one input via line 448 from gate 447 just mentioned above, another input 449 from a comparator 450 to be described below, and a third input via line 436 inverted from the D15 line 405 in FIG. 9-O. A fourth input via a line 437 from the M field and Sub in the control matrix 212 indicates M13-SUB. A busy signal from PIN 29 could be another input via line 438; this would be used if a printer were attached, and would indicate, for example, that the printer was still busy and the program counter should not be incremented until printing of previous data is completed.

The comparator 450 specifies a particular keyboard input and produces outputs to inhibit increment and also to the condition circuit 261 which produces COND, PIN 32. Inputs to the comparator 450 include the three bit .SIGMA. field on lines 240, the seven K inputs on lines 451 from the keyboard matrix 400, and the four bit R field on lines 452 from the instruction register output. When the K field is the same as that specified by .SIGMA. and R fields, the comparator 450 output on line 451 appears as an input to the gate 262 in the condition circuit 261.

The condition circuit 261, FIG. 9U, further receives a carry/borrow input on line 455 from the BCD decoder, as well as a busy condition indication on line 456 (not used in this embodiment). The flag input 260 means that two flags are the same. A "condition" or COND output is used for branch instructions; the output is through a latch 457 operated by an Inst. output from the instruction register 21 appearing through a NAND gate on line 458. Inverted digit mask is applied to the C/B part of the condition circuit via line 459, and S0 is applied via line 460.

An idle latch circuit 462 produces an output on a line 463 which goes to PIN 11, FLGA output to the display. During a software loop which scans the keyboard for a key to be depressed, the A flags are displayed, thus the latch output to the flag display output. Also, this latch output goes to a latch 464, FIG. 9D, in the control for the display scan of FIG. 9J. During the idle loop, the A register is displayed, so idle latch enables the display. A "set idle latch" input 465 from the control matrix 212 sets the latch when specified by the program, and the latch is reset by an input 466 from the matrix. This "idle reset" command on line 466 is also applied to a NAND gate 467, FIG. 9T, which receives S15 as its other input (from 214); the NAND output is applied via line 468 to a power up clear circuit 470, FIG. 9D.

The power up clear circuit 470 assures that the machine is initiallized correctly. The program counter 25 is forced to zero. A "reset idle latch" at location "0" forces the machine out of location "0". The circuit 470, upon receiving the reset command on line 468, generates "0" on line 469 going to P register output circuit 471, FIG. 9-O. When power is turned on, all the register contents, values of flags, etc., are unknown and should be cleared or set to known values.

An output to the program register 25 in the ROM chip is provided at PIN 17. This output is controlled by circuit 471. When an address is to be sent to the ROM chip, a command is made to appear at output 472 from the control matrix 212. The address to be sent out is coupled from special register 36 via line 473 as an inverted input to NAND gate 474. When an address is sent, it always is eight bits long and starts with "0"; when the ROM chip sees a "0" at S4, it knows that the data chip is sending an address. The next seven bits are the address. A latch 475 is provided to keep putting out zeros to the end of the instruction cycle. The latch is set by an input 476 from the command input, and reset by an input 477 from delayed S14 line 387.

The ALU 24 comprises a binary adder made up of four sets of complex gates 480 and 481. The 480 sequence is a complex logic gate having SUB, SUB, X, Y.sub.1, Y.sub.1 inputs. The 481 sequence is NOR/NAND with the same five inputs. These function to add or subtract a binary number appearing on X.sub.1 and Y.sub.1 lines 39 and 42, and to produce a carry/borrow input to C/B circuit 482. The logic arrangement chosen was to provide fast operation, i.e., to allow the ALU operation to occur within one state time. The X.sub.2 -Y.sub.2, X.sub.4 -Y.sub.4 and X.sub.8 -Y.sub.8 parts of the ALU are the same as X.sub.1 -Y.sub.1. The data into the ALU is BCD, yet it is operated on as if it were binary, so to convert back to BCD a corrector matrix 485 is used. The "1" output, F1 on line 486, need not be corrected and so it bypasses the corrector. The F2, F4, F8 and C/B lines go through the corrector 485 which is a programmable logic array. Other inputs are SUB on line 487, and CKILL or corrector kill on line 488 which prevents the corrector from operating on SO which is the decimal point location. So, DPT is carried in straight binary rather than BCD. CKILL on line 488 is generated in push-pull matrix 280, by a gate at SO. Outputs from the corrector 485 include 2, 4 and 8 inputs to the left shift selector 49, and C/B, C/B outputs on lines 455 and 499. The carry/borrow output goes to a C/B gate circuit 500 which keeps C/B from propagating over from prior bit. Inputs are SUB from line 487, and C/B reset on line 501 which is generated from a digit mask edge by shift control circuit 274. The output 502 from C/B gate circuit 500 is connected to a transistor 503 in the first bit of C/B circuit 482. The carry circuit operates as explained in co-pending applications Ser. No. 176,667 (TI 4658, TI-4660) C/B output is provided at 504, from which it is connected for BCD correction.

The contents of the A register 30 may be read out to PINS 7, 8, 9, 10, FIG. 9A, to a suitable display arrangement. The output lines of A.sub.1, A.sub.2, A.sub.4 and A.sub.8 appear on lines 510. These outputs are strobed into a zero suppress circuit 511 by a strobe line 512 which is energized once every fifteenth state time by a programmable strobe circuit as will be described, the same source as produced the strobe input 326 to D time generator gate 324. The time of occurrence of the strobe will thus count backwards, like S15, S14, S13 . . . S1, S0; this provides zero suppress from MSD first. The A.sub.1 -A.sub.8 bits strobed out are held and allowed into zero suppress upon S0-.phi..sub.1 as determined by the output of gate 513 which is activated from a line 514 in the push-pull matrix 310, so all read-outs will start at the same state time. The zero suppress arrangement comprises an eight input NAND gate 515 which receives all of the A.sub.1 -A.sub.8 inputs from lines 516 as four inputs as well as begin and end signals on lines 517 and 518 which are generated in matrix 310. Zero suppress is unconditionally ended by these signals so that the last digit will be displayed even if it is a zero; if the result is all zeros, the last one will be displayed. The lines 517, 518 can be programmed to begin and end at any desired points. The begin line goes through a gate 519 which operates as a latch with the gate 515. DPT indication on line 424 is also an input to gate 515. The first non-zero or decimal point reached sets the 515-519 latch, and the output of the latch is applied to four output NAND gates 520 via line 521, allowing everthing that follows to pass thru. The output NAND gates receive the A.sub.1 -A.sub.8 data on lines 516, and also the line 463 idle set output as well as a blanking signal on line 522, derived from matrix 310, which controls which digits can be displayed, i.g., S1 to S14. The outputs from gates 520 are applied thru suitable non-inverting output buffers to PIN 7 to PIN 10 going to the display.

Commas may be generated by an algorithm and stored in B.sub.2, from which they are outputed at PIN 6, upon the occurrence of a proper instruction word.

A strobe generator circuit 530 of FIG. 9D produces a strobe signal on line 327 and on PIN 16 once every fifteen S times. Depending upon the type of display elements used in the calculator, and how often they should be strobed, the circuit 520 may be programmed to produce a strobe at longer intervals, such as every thirty-one, or sixty-three, or one hundred twenty-seven S times. These are all one less than a multiple of sixteen so that the D times are counted backwards. The strobe circuit 530 comprises an eight stage recirculating shift register 531 of conventional form, along with a matrix 532 programmed in this case to count to fifteen along with an output matrix 533. The arrangement operates as a serial shifting counter that will count to (2N-1); only four stages are used so the embodiment shown counts to fifteen.

Turning now to the second chip, referred to as the ROM chip, FIG. 10, this device includes a ROM 20 made up of a 64.times.8.times.13 or 6656 bit read only memory for storing 512 thirteen bit instruction words. The ROM is programmed as set forth in U.S. Pat. No. 3,541,343, by thinning the oxide where a gate is needed. Sixty-four X address lines 550 are provided (only two are illustrated) and 104 Y lines 551. The X lines 550 are metal stripes and the Y lines 551 are P diffusions. The X lines are precharged to V.sub.DD at S4-.phi..sub.1 via line 552. The Y lines are arranged in groups 553 of eight to provide thirteen outputs 554 (only three are shown); these output lines are precharged at S5-.phi..sub.1 via line 555. Only one of the lines 551 in each group 553 is selected by means of Y address select arrangements 556, of which there are eight (only two are shown). These selector matrixes are driven from three Y address lines 557. The matrixes 556 change three line encoded to eight line unitary. Likewise, selector matrixes 558 select only one of the sixty-four X lines 550 for energization, based on the encoded six bit X address appearing on lines 559. Gates 560 save DC power by gating the X and Y addresses on for only a state time, rather than being on all the time.

The program counter 25 comprises an eleven stage shift register from which the six address lines 559 and the three Y address lines 557 are outputed in parallel. The program counter operates by either being incremented by one for each instruction cycle, in which case it would cause the instruction words to be read out of the ROM 20 in numerical sequence, or secondly an instruction word can be forced into the counter from input lines 561, as for a branch. The lines 561 are connected into the program counter 25 and address lines 557, 559 via transistors gated by a line 562, which is controlled by gates 563 and 564. These gates receive inputs 565 from bits I.sub.11 and I.sub.12 which are used for branch/operation, and condition. An address would be forced in via lines 561 only for branch indicated on I.sub.12, and if it is a conditional branch this would be indicated on the I.sub.11 line. The condition is met or not met as indicated on the COND input 566, which is received from COND output of the data chip. So, line 562 goes negative only if a branch is ordered, and, if conditional, when the condition is met. An add-one operation is accomplished by a selector circuit 567, which receives the output of upper stage 568 in the program counter 25 via line 569, and CONA or inhibit increment on line 570. A time signal S3-.phi..sub.2 is applied via line 571. The output 572 from this selector circuit is applied to the input of the lower stage 573A of the program counter. The program counter 25 recirculates through the Add-1 selector 567 least significant digit first, and at the time the LSD is going into the selector a one is added at a time controlled by the 8 input 571, if CONA or inhibit increment is not on. If a carry is generated, it is coupled back via line 573 to be added to the next bit. The system is designed to use more than one ROM chip if more than 512 words of stored instructions are needed, so that I.sub.9 and I.sub.10 lines are for chip select. These lines are applied to a logic array 576, the output of which is applied to a select gate 577. The other inputs to this gate are as S1 to S7 timing signal on line 578, and a "1" input which is expanded embodiment would be a CON-B input.

The output of gate 577 enables a set of output buffers 579 which are in series with the thirteen ROM output lines 554, also labeled B.sub.0 to B.sub.12. The outputs of the buffers 579 are applied via lines 580 to a thirteen bit instruction register 581. This is a two part shift register which shifts the instruction word out via suitable buffers and two lines 582 and 583 going to IRGA and IRGB pins, and thus to the data chip inputs 200 and 201. If more than ROM chip is used, instruction words may be conveyed from one to the other, as for branching, via input/output pins I.sub.0 to I.sub.12 (these are not used in the embodiment described).

State times are conveyed from the data chip to the ROM chip via inputs SA,SB,SC,SD, which are applied along with their complements to a timing decoder 585 to regenerate state times S0 to S15. These are applied to a maxtix 586 which generates several time signals. One output 587 provides S3 to the gating generator 588 for input buffers 560 in the X and Y address inputs. An output 589 produces time inputs to the Add-1 selector and the gate 563. An S5 to S15 is generated on a line 590 for producing an eleven bit timing signal for operating the eleven stage shift register of the program counter 25. An S7 output 591 is used to gate the word on lines 580 into the instruction register 581. And, S1-S4 on line 578 is an input to gate 577 as mentioned above. An S4 signal is applied directly from timing decoder output 585 via line 592 to gate the P-REG input 593 into the selector circuit 567. The 7 bit word in the special register 36 of the data chip may be read into the program register 25 via the selector circuit 567; when the P-REG signal is present, Add-1 is ineffective.

Merely for convenience in placement of pins for the integrated circuit packages, the embodiment of FIGS. 9 and 10 has the display scan split up into two sections, with D2 to D12 on the ROM chip and D13-D15 and D1 on the data chip. In FIG. 10E, the display scan outputs D12 to D2 are generated in an eleven stage shift register 600 which receives an input 601 generated in a latch 602 operated by a strobe input 603, S0 input 604, and S11 input 605. This latch operates with another latch 606 and gate 607 having an S15 input 608, to select a specific D time, e.g., D11, which is then shifted through the register to actuate D12 to D2 in sequence.

The display scan on the data chip, FIGS. 9D and 9J, uses for four stage shift register 610 which is started by a D1 signal on line 329. A latch 464 receives a delayed strobe input from 327 on line 611. S15 is applied to a NAND gate 612 via line 613, and the latched strobe signal is the other input. The register 610 is started by D1 and counts D15, D14, D13, then at this point the display scan of FIG. 10E takes over.

In both FIG. 9J and FIG. 10E, the outputs are blanked by lines 332 and 615 on S0 and S15, so that a gap will exist between D outputs; this is needed for some displays.

Referring now to FIGS. 11A-11R, detailed views of the inverters. NAND and NOR gates, and complex gates used in FIGS. 9 and 10 are shown. FIGS. 11A and 11B are static and dynamic NAND gates, FIG. 11C is a "bootstrap" NAND gate, and FIG. 11D is an open drain, no load NAND. FIG. 11E is a unique bootstrap type gate which is the subject of another patent application. FIGS. 11F, G, H are static, dynamic and open drain NOR gates. FIGS. 11I, J, K, L are inverters of the static, dynamic, bootstrap and open drain types, respectively. FIGS. 11M to 11R are complex gates using only one load.

An example of a programmable logic array like those used in the decode matrixes of FIGS. 9 and 10, is shown in FIG. 12. A and B inputs are presented to the first half (decoder) of the PLA in both true and complemented polarties. In this example, four product terms, or decode outputs 620 are presented as inputs to a second (encoder) array. The circuits for the decoder gates and encoder gates are identical shunt gates; that is NAND gates. However, since NAND-NAND logic reduces to AND-OR logic, it is convenient to use sum-of-product notation to describe the PLA circuit implementation where the dependence of a particular product term on a particular input is indicated by a circle at that junction. The circles also correspond physical placement of MOS gates by a programmable gate mask used in fabrication of the MOS embodiment. PLA's are known in the art and need not be detailed herein.

FIG. 13 shows a push-pull matrix such as the matrix 280 or 310 in FIG. 9. This differs from a PLA in that it has no loads and uses no DC power. Output lines 630 for the PLA are P diffusions, represented by dashed lines. Input lines 631 are metallization, represented by solid lines. Gates are provided by thin oxide at locations 632, represented by rectangles. When an input line 631 goes to "0" or minus voltage, and a gate 632 is present, the output line 630 goes to V.sub.DD as a channel will be created. This output line will stay at V.sub.DD until another gate appears between 630 and V.sub.SS, when it will go to ground. It is assumed that the lines 631 are being driven one at a time to a "0" voltage, from right to left, just as the matrix 280. The notation used in FIG. 9 for push-pull matrixes is that whenever an output line is to be at a logical "1", there is a circle; this is different from the physical embodiment. FIG. 13A shows the notation used for the embodiment of FIG. 13.

Table VI is a listing of the instruction words stored in the ROM 20 for a standard revision of the calculator of the invention, to produce the operation functions according to the examples of Table V. The first three digit column in Table VI counts the ROM locations (program counter outputs in hexadecimal code from 0.000.sub.16 (.sub.10)through 1FE.sub.16 (511.sub.10). The next eleven digit column reflects the binary code contents of the ROM at each of the locations of the first column; this is the word read into the instruction register including the I.sub.0 to I.sub.12 fields, and is executed by the system. The third column beginning with 0005 is merely line numbers for the printout. The remaining columns give programming labels by which some rountines are known, and instruction mnemonics, and comments relating to the operational meaning of the instructions, as appropriate.

Table VII is another listing of the program instruction words stored in the ROM, listed by ROM address. The words are in hexadecimal. Table VIII is a similar listing in binary instead of hexadecimal. Table IX is a layout of the ROM to produce the instruction words of Tables VI, VII and VIII, wherein each X is a gate in the MOS embodiment of the ROM.

FIGS. 14A and 14B are top views of actual chip layouts for the data chip and ROM chip, respectively, as embodied in MOS/LSI. Various parts of the system, such as the main register 23, the ROM 20, and others, are labeled with the same reference numerals as in FIGS. 2, 3, 9 or 10.

Although the invention has been described with reference to a specific embodiment, various modifications of this embodiment as well as other embodiments of the invention will become apparent to persons skilled in the art. It is therefore contemplated that the appended claims will be construed in a limiting sense and will cover any such modifications or embodiments as fall within the true scope of the invention.