Current Limiter

1. Field of the Invention

The present invention relates to current limiting circuits, and more particularly to an FET bipolar current limiter for an a.c. circuit.

2. Description of Prior Art

Prior current limiting devices used fuses, circuit breakers, discrete current limiting circuits requiring a custom current transformer, and FET current limiting circuits for low voltages having FET's connected in opposition with the gate and source electrodes connected together. The prior art FET circuit, shown in FIG. 1, has the disadvantage that it is very difficult to design FET current limiters with low resistances which are relatively independent of transistor characteristics, and at the same time have high breakdown voltages. The voltage rating is limited to that of a single FET since the saturation current (I.sub.DSS) ratings are not matched.

Accordingly, the present invention provides a current limiter for an a.c. circuit to protect the power source from the effects of a failure, or short, in the load. Two FET's with I.sub.DSS ratings in excess of the desired peak short circuit current are connected in cascode, source to drain, with the opposite terminals connected via self-biasing resistors between the load and the power source, respectively. The FET's are biased via a series resistor network to which the gates are connected, with diodes connecting the gates to the load side and power source side, respectively, of the self-biasing resistors. In operation one FET operates as a source follower and the other as a current source.

Therefore, it is an object of the present invention to provide a current limiter for an a.c. circuit to protect a power source from a failure, or short, in the load.

Another object of the present invention is to provide a current limiter using FET's which can withstand high voltage levels without breakdown.

Other objects, advantages and novel features of the present invention will be apparent from the following detailed description when read in view of the appended claims and attached drawing.

FIG. 1 is a schematic diagram of a prior art FET current limiter for low voltages.

FIG. 2 is a schematic diagram of a current limiter according to the present invention.

FIG. 3 is a graph of the performance characteristic of the circuit of FIG. 2.

FIG. 4 is a schematic diagram of another embodiment of the current limiter according to the present invention.

Referring now to FIG. 2 two FET's Q1 and Q2, are connected in cascode by connecting terminal 2 of Q1 to terminal 1 of Q2. Terminal 1 of transistor Q1 is connected to resistor R.sub.S1, and terminal 2 of transistor Q2 is connected to resistor R.sub.S2. The other ends of resistors R.sub.S1 and R.sub.S2 are serially connected to the line at L1 and L2, respectively, between the load and the power source. A resistive voltage divider network of R.sub.B1, R.sub.B2 and R.sub.B3 is also connected between L1 and L2, R.sub.B resistors being much larger than R.sub.S resistors. The gate of Q1 is connected at the junction of R.sub.B1 and R.sub.B2, and the gate of Q2 is connected at the junction of R.sub.B2 and R.sub.B3. Low current diodes D1 and D2 connect the gates of Q1 and Q2 to L1 and L2, respectively, with the anodes connected to the gates and the cathodes to the line, and act as switches to bypass resistors R.sub.B1 and R.sub.B3, respectively, to make the circuit appear symmetrical to either applied voltage polarity.

If L1 is positive, Q2 acts as a current source because the gate is held at approximately 0.6 volts, the forward bias voltage drop across D2, with respect to L2. Terminal 2 of Q2 acts as the source since the source and drain leads of FET's are essentially interchangeable. Q1 acts as a source follower, or unity gain buffer, and the voltage drop across Q1 is approximately equal to the voltage across R.sub.B1, i.e., approximately one-half of the line voltage. Since the circuit is symmetrical, when L2 is positive Q1 becomes the current source with D1 forward biased and Q2 becomes the source follower, or unity gain buffer.

As long as the a.c. circuit is operating properly the current limiter circuit acts as a small resistance and its characteristic is shown by the linear portion 10 of the curve of FIG. 3. If a short occurs in the load, the entire power source voltage appears across the current limiting circuit which limits the total current to I.sub.LIM as shown by the level portion 12 of the curve. The value of L.sub.LIM is determined by the value of resistors R.sub.S. Since the FET's are not matched, I.sub.LIM must be less than the lowest I.sub.DSS of either FET.

For an a.c. power source of 28 volts rms, peak voltage approximately 41.5 volts, the current source gate is held at 0.6 volts and the voltage across R.sub.S cannot be greater than V.sub.p, the cutoff voltage for the FET, plus the gate voltage. With R.sub.S of 2 ohms, R.sub.B of 10 K .OMEGA., and a desired limiting current of 425 ma, V.sub.RS is 0.85 volts. The voltage at the source follower gate is (41.5-0.6)/2, or 20.45 volts, and the total voltage maximum across either FET is 22.15 volts, well within the breakdown voltage of 30 volts for a Siliconix FN 3392 FET.

With matched FET's, i.e., the I.sub.DSS of each being equal such as can be obtained in integrated circuits as opposed to discrete components, R.sub.S could be reduced to virtually zero. However, if one FET cannot supply sufficient current to the other due to unmatched I.sub.DSS, that FET becomes forward biased and starts to develop greater voltage across it until breakdown occurs. Thus, the value of R.sub.S is a trade-off between the desire for a small impedance circuit and the necessity for self-biasing with unmatched FETs.

FIG. 4 shows that for higher voltage applications groups of resistors and FETs, such as Group A (R.sub.B4 and Q3) and Group B (R.sub.B5 and Q4), can be strung together until the parasitic capacitance to ground starts to interfere with the circuit operation at the particular a.c. frequency. Therefore, with a peak voltage of 100 volts and Q2 as the current source each FET would drop approximately 25 volts, less than the individual breakdown voltages.

Thus, the present invention provides a current limiter for an a.c. circuit to protect a power source from a short in the load which can operate at voltages greater than the breakdown voltage of an individual FET.