Electroflash Controlling Circuit Including a Delay Circuit for Electrically Controlled Focal Plane Shutters

(a) Field of the Invention

This invention relates to an electroflash controlling circuit for electrically controlled focal plane shutters.

(b) Description of the Prior Art

A type of electroflash controlling circuit for electric shutters wherein an electric signal for closing a shutter is utilized directly for an electroflash triggering signal has been already suggested. However, this type has such defect as is mentioned below. Now, an electrically controlled focal plane shutter provided with a front blade group and rear blade group in the case that the shutter speed is set at 1/125 second (the rear blade group will begin to run after the lapse of 7.8 m.s. after the front blade group begins to run) shall be exemplified and explained. In such case, as shown in FIG. 4, due to mechanical and magnetic operation delays, it will take a time of 5 m.s. before both front blade group and rear blade group actually begin to run after respective running starting electric signals or release signals are issued. The time required for the front blade group to reach the fully opened position from the position in which it perfectly covers the exposure aperture and the time required for the rear blade group to reach the perfectly covering position from the position in which it fully opens the exposure aperture are both about 6 m.s. Therefore, if the electric signal for starting the running of the rear blade group is utilized directly for the electroflash triggering signal, it will be issued as a result while the front blade group is running to open the exposure aperture and the flash lamp will flash before the front blade group reaches the fully opened position. Such defect will occur also in a type of focal plane shutter wherein the front blade group is mechanically started to run by the operation of a release button.

A primary object of the present invention is to provide an electroflash controlling circuit for electrically controlled focal plane shutters wherein, in order to eliminate the above described defect, a delaying circuit is operated by an electric signal for starting the running of the front blade group or rear blade group and, when the time determined by said delaying circuit has elapsed, the electroflashing circuit will be triggered to make the full opening of the shutter and the flashing of the flash coincide with each other.

This and other objects of the present invention will become more apparent during the course of the following detailed description and appended claims.

FIG. 1 is a wiring diagram showing an embodiment of the controlling circuit according to the present invention;

FIG. 2 is a wiring diagram showing another embodiment of the controlling circuit according to the present invention;

FIG. 3 is a wiring diagram showing still another embodiment of the controlling circuit according to the present invention;

FIG. 4 is a characteristic diagram for explaining the relation between the shutter operation and the flashing.

FIG. 1 shows a controlling circuit adapted to an electric shutter of a type wherein front blades are mechanically released by a manual operation. In the drawing, symbol S indicates an exposure controlling circuit part and X indicates an electroflashing circuit part. R.sub.1 indicates a variable resistor for setting an exposure time, C.sub.1 indicates a capacitor forming the first delaying circuit together with the variable resistor R.sub.1 and S.sub.1 indicates a normally closed switch used to start the operation of the first delaying circuit and opened in relation to the releasing operation of the front blades. Symbol COM.sub.1 indicates a comparator, R.sub.2 indicates a potentiometer used to give an input voltage on one side of the comparator circuit COM.sub.1, T.sub.2 indicates a transistor connected to the output side of the comparator circuit COM.sub.1 and L.sub.2 indicates an electromagnet coil used to start the rear blades or the rear blade closing motion. Symbols R.sub.3 and C.sub.2 indicate respectively a resistor and capacitor forming the second delaying circuit to delay the electroflashing time by a predetermined time, T.sub.3 indicates a transistor used to start the operation of the second delaying circuit and connected to the output side of the comparator circuit COM.sub.1 and COM.sub.2 indicates a comparator circuit. Symbol R.sub.4 indicates a potentiometer used to give an input voltage on one side of the comparator circuit COM.sub.2, FP indicates an electroflash lamp, SCR indicates a rectifying element provided with controlling electrodes of a well known trigger circuit (which shall be described merely as SCR hereinafter), C.sub.3 indicates a main capacitor, DC indicates a DC-DC converter, E.sub.1 indicates a current source of an electronic flash circuit and C.sub.4 indicates a coupling capacitor connected between the output side of the comparator circuit COM.sub.2 and a gate of SCR.

The operation of the above mentioned circuit shall be explained in the following.

First of all, when the release button of the camera is pushed down, a current source switch not illustrated of the exposure controlling circuit part S will be closed in the initial step and a voltage will be fed to each part of the circuit. In this state, the output of the comparator circuit COM.sub.1 will be placed on the "H" level and, on the other hand, the output of the comparator circuit COM.sub.2 will be placed on the "L" level. When the release button is further pushed down, the front blades will be mechanically released and the switch S.sub.1 will be opened. When about 5 m.s. have elapsed after this time point, the front blades will begin to run and, after about 6 m.s., the exposure aperture will be fully opened. On the other hand, if the delay time of the first delaying circuit determined by the variable resistor R.sub.1 and capacitor C.sub.1, that is, the exposure time is set at 1/125 second, after 7.8 m.s. after the front blades are released, in the comparator circuit COM.sub.1, the potential of the input terminal (-) will become higher than the potential of the input terminal (+) and its output will turn to the "L" level. As a result, the transistor T.sub.2 will become off and the current fed to the coil L.sub.2 will be interrupted. Therefore, when about 5 m.s. have elapsed after this time point, the rear blades will actually begin to run and then, after about 6 m.s., the exposure aperture will be fully closed. On the other hand, by the turning of the output of the comparator circuit COM.sub.1 to the "L" level, the transistor T.sub.3 will become off and the operation of the second delaying circuit consisting of the resistor R.sub.3 and capacitor C.sub.2 will be started. If this delay time is set at 3 m.s., after 3 m.s. after the beginning of the operation of the second delaying circuit, the output of the comparator circuit COM.sub.2 will turn to the "H" level and a positive pulse will be given to the gate of SCR through the capacitor C.sub.4. Therefore, the flash lamp FP will be triggered and will be flashed by the discharge of the main capacitor C.sub.3. In such case, the flash continuing time of the flash lamp FP will be about 2 m.s. Therefore, as shown by the solid line in FIG. 4, the flash of the flash lamp FP will reach the maximum brightness while the front blades reach the substantially fully opened position and then the rear blades begin to run.

FIG. 2 shows a controlling circuit adapted to an electric shutter of a type wherein front blades are also electrically released. Here only exposure controlling circuit parts are shown. In the drawing, symbol S.sub.2 indicates a release switch, CP indicates a clock pulse generating circuit, CO.sub.1 indicates a counter for setting the exposure time, CO.sub.2 indicates a counter controlling the time of passing a current to the coil L.sub.2, CO.sub.3 indicates a counter for delaying the flashing time of the electroflash, T.sub.1 and L.sub.1 indicate respectively a transistor and coil used to release the front blades, FF.sub.1 to FF.sub.4 indicate flip-flop circuits (which shall be described merely only by the symbols hereinafter), AG.sub.1 to AG.sub.6 indicate AND gates and I indicates an inverter.

The operation of the above mentioned circuit shall be explained in the following. When the release button of the camera is pushed in the illustrated state and the current source switch not illustrated is closed, a voltage will be fed to each part of the circuit and, when the switch S.sub.2 is connected to the terminal a side, FF.sub.1 to FF.sub.4 will be reset and the counters CO.sub.1 to CO.sub.3 will be cleared. If the release button is further pushed in and the switch S.sub.2 is switched from the terminal a to the terminal b, FF.sub.1 to FF.sub.4 will be released from their reset states and the counters CO.sub.1 to CO.sub.3 will become active on the clock input. As a result, in FF.sub.1, the set input S will be set on the "H" level and the output Q will turn to the "H" level. Therefore, the AND gate AG.sub.1 will open its gate and will send a clock pulse into the counter CO.sub.1. The counter CO.sub.1 will be triggered by the fall of the clock pulse, an output signal will appear in the output Q in the first step and, after T.sub.n seconds determined by the following formula, a signal will appear in the output Q.sub.n of the nth step.

where T is a clock period.

Here, first, when the output Q.sub.1 of the counter CO.sub.1 turns to the "H" level, FF.sub.2 will be set and its output Q will turn to the "H" level. At this time, FF.sub.3 will not yet be set and its output Q will be placed on the "H" level. Therefore, the AND gate AG.sub.2 will open the gate and the output will turn to the "H" level, will switch the transistor T.sub.1 on and will pass a current to the coil L.sub.1. As a result, the front blades will begin to actually run about 5 m.s. later than this time point. As the set input S is connected to the output Q.sub.11 of the counter CO.sub.1, if the clock frequency of the clock pulse generating circuit CP is made 131 KH.sub.z, FF.sub.3 will be set when the output Q.sub.11 turns to the "H" level after 7.8 m.s. from the above formula. Thereby, the AND gate AG.sub.2 will close the gate and will stop the passing of the current to the coil L.sub.1. On the other hand, after the lapse of 7.8 m.s., the output Q.sub.11 of the counter CO.sub.1 will turn to the "H" level and will set FF.sub.4. As a result, the output Q of FF.sub.4 will turn to the "H" level, therefore the output Q.sub.11 of the counter CO.sub.2 will be on the "L" level, the output of the inverter I will be on the "H" level, therefore the AND gate AG.sub.4 will open the gate and its out put will turn to the "H" level, will switch the transistor T.sub.2 on and will pass a current to the coil L.sub.2. As a result, after a delay of about 5 m.s. after the release signal is generated, the rear blades will begin to actually run. Also, when the output Q of FF.sub.4 turns to the "H" level, the AND gate AG.sub.3 will open its gate and will have a clock pulse sent into the counter CO.sub.2. As the inverter I is connected to the output of the counter CO.sub.2, after 7.8 m.s., its output will turn to the "L" level, will close the gates of the AND gates AG.sub.3 and AG.sub.4, will stop the feed of the clock pulse to the counter CO.sub.2, and will also stop the passing of the current to the coil L.sub.2. Further, when the output Q of FF.sub.4 turns to the "H" level, the AND gate AG.sub.5 will open its gate and will have a clock pulse sent into the counter CO.sub.3. As the output of the AND gate AG.sub.6 having the outputs Q.sub.8 and Q.sub.9 of the counter CO.sub.3 as both inputs is connected to electroflashing circuit X, 3 m.s. before the time point at which the rear blades actually run, the outputs Q.sub.8 and Q.sub.9 will turn to the "H" level, the output of the AND gate AG.sub.6 will be on the "H" level and, the same as in the preceding embodiment, the flash lamp FP will flash.

When the switch S.sub.2 is returned to the terminal a with the end of the exposing operation, FF.sub.1 to FF.sub.4 will be reset, the counters CO.sub.1 to CO.sub.3 will be cleared to be ready for the next exposure.

By the way, in the above mentioned embodiment, the clock pulse generating circuit CP is used in common. However, for example, a clock pulse generating circuit for the counter CO.sub.3 may be separately provided.

Further, the counting of the counter CO.sub.3 for delaying the flashing time of the flash lamp FP can be started by the release signal of the front blades. In such case, as shown in FIG. 3, an AND gate AG.sub.7 having the outputs Q.sub.8, Q.sub.9 and Q.sub.11 of the counter CO.sub.1 as inputs may be provided to connect its output to the electroflash circuit X. According to the embodiment in FIG. 3, when 10.8 m.s. have elapsed after the release signal of the front blades is generated, the outputs Q.sub.8, Q.sub.9 and Q.sub.11 of the counter CO.sub.1 will all turn to the "H" level, the output of the AND gate AG.sub.7 will be on the "H" level and the flash lamp FP will flash.