Safety Circuits for Coupling Laddics in Cascade

This invention relates to safety circuits and the like which make use of multi aperture ferrite components such as those known as laddics. Laddics in common with other like devices exploit the square or, more accurately, the trapezoidal shape of their magnetisation characteristic by the application of alternate mmf pulses of opposite sign to windings embracing spaced legs of the laddic so that magnetic flux changes induced in the ferrite may be detected by an output winding in terms of an emf. Further control windings may be employed on the ferrite legs between the input and output windings so that the laddic may act as a logic gate in which a flux reversal in ferrite beneath the output winding is inhibited unless the required control winding inputs are present. Because the existence of an output signal may be made dependent upon the maintenance of separate pulsed inputs on the other windings the device is normally failsafe and finds application in safety circuits, for the output, which itself is a pulse train, will not appear if any one input or control signal fails to switch the magnetic flux in its underlying portion of the ferrite.

Should there be a failure and the ferrite which is beneath the output winding fail to be switched from a certain saturation point, the magnetic flux will fall from saturation to remnance by natural decay. Although the flux change over this part of the B-H loop is very small indeed compared to a full flux reversal, it can occur at a very much faster rate. Unless precautions are taken the amplitude of the voltage induced in the output winding as a result of this small but fast flux change can be quite comparable to a full flux change. Such a possibility cannot be tolerated in a circuit of high reliability as in a safety circuit and in these circuits laddics are coupled in cascade with the object that an output pulse from the output winding of the first laddic serves to reset the flux in the second laddic. In this context a spurious output pulse is termed reset noise for the amplitude of the noise may be sufficient for the signal to reset the next laddic. This weakness has in the past been compensated for by the use of a coupling circuit between cascaded laddics which includes a transistor having a low cut off frequency. However these transistors are becoming obsolete and the present tendency is for the trade to market planar transistors with high cut off frequencies.

An object of the present invention is to produce a means whereby the risk of spurious output signals from the output winding of a laddic is reduced and allowes a planar transistor to be employed to couple laddic devices in cascade.

According to the present invention there is provided an electric circuit including a laddic component, an output winding on the laddic component, the output winding forming part of an emitter follower transistor circuit arranged so that the output impedance of the transistor restricts the rise and fall times of the mmf in the output winding.

Preferably the laddic leg next to that carrying the output winding bears a further winding in series opposition with the output winding so as to generate a compensating emf to limit noise signals in the output winding when the flux in the ferrite drops from saturation to remnance.

The invention will now be described in its application to laddics connected in cascade with reference to the accompanying drawings in which

FIG. 1 is a circuit diagram of a preferred embodiment of the present invention wherein compensation is provided for reset noise generated in the coupling circuit between two laddics connected in cascade; and

FIGS. 2A and 2B are explanatory diagrams and show prior art.

Referring to the drawings there is shown the elements of a coupling circuit between two laddics L1 and L2 connected in cascade. The laddics each comprise a ferrite strip having a single row of similar apertures separated by legs or rungs. The legs or some of them carry windings which are shown as single loops and these include an input, or set, winding Wl, a reset winding WR and an output winding WO the latter being applied to a leg remote from the input winding Wl. Between windings W.sub.l and WR are a number of control, or hold windings WC but these are not directly the concern of the present invention which as previously stated is directed to the reduction of reset noise generated in output winding WO. There are two aspects to the means for compensating for reset noise, namely, the use of an opposition winding WX on the penultimate leg of the laddic L1 in series with winding WO and the use of an emitter follower planar transistor T2 in the coupling circuit.

As will be known in normal operation of a laddic L1 the input winding W1 and the reset WR receive pulses of opposite sign and these are phased to set up alternate mm f's in the underlying ferrite and a consequential continuous switching of the direction of the saturated magnetic flux in the ferrite from positive to negative side of the B H loop results. This flux change is detected in the ferrite beneath the output winding Wo as an emf and can be used to produce a reset current in the next laddic L2. The conventional way of detecting these flux reversals, as indicated by FIGS. 2A and 2B in which the flux reversals are indicated by arrows, is by the winding WO embracing the ultimate legs of the laddic. The singular winding WO was connected into a coupling circuit which included a grounded emitter transistor amplifier having a low cut off frequency. See for example British Communications and Electronics, March 1962, page 181, FIG. 4(a). It will be observed that the flux in the penultimate leg appears to preserve a constant direction and does not contribute to reset noise. By extending the winding WO so that it embraces the penultimate leg as an additional winding WX in series opposition to the winding WO, then if and when the magnetic flux falls from saturation to remnance an emf will be generated in the WX which opposes that generated in the winding WO and a partial cancellation of reset noise will be obtained.

A further measure which enhances immunity from reset noise appearing in the coupling between laddics is the provision of an emitter follower transistor coupling circuit. This coupling circuit includes a contemporary planar npn transistor T2 used in the emitter follower configuration; when positive pulses are supplied to the base the transistor conducts and current flows to the reset winding of the second laddic L2 with in-phase pulses. These current pulses generate a reset mmf and the rise and fall times of which are governed by the output impedance of the emitter-follower coupling transistor and the reset winding inductance in L2 unlike the case of the common emitter transistor coupling used hitherto. With a common emitter transistor the mmf rise time was governed by the transistor turn-on time and by the time constant of the Reset-current-defining resistance and the Reset winding inductance; the mmf fall time of the Reset mmf being extremely short at transistor switch off and the fall of mmf being limited only by the natural rate of decay of the magnetic flux from saturation to remnance. In contrast when the emitter follower transistor turns off its base-emitter junction is forward biased and begins to conduct so limiting the back emf generated across the driven Reset winding in L2. Hence the rate of fall of Reset mmf is controlled and on the trailing edge of the Reset mmf pulse, the resulting rate of change of flux is small, too small to generate a spurious Reset noise emf. Also the compensated output winding provides partial cancellation of any noise emf generated as the flux decays from saturation to remnance due to opposite senses of the flux changes in the penultimate and final rungs of the laddic L1.