Sampled Error Phaselock or Frequencylock Systems

This invention relates to electronic systems and in the preferred embodiment to phaselock systems and to preventing coincidental phase modulation in the output of pulsed RF transmitters.

As recognized in U.S. Pat. No. 3,831,094, assigned to the assignee hereof, many broadcast type AM transmitters can produce coincidental and undersirable phase modulation of the transmitted carrier. Similarly, coincidental phase modulation can arise in the output of pulse radar or other pulsed RF transmitters due to such things as electrical and thermal transients in transmitter components including pulse amplifiers, gates, switches, etc. This coincidental phase modulation causes spreading and/or smearing of the frequency spectrum energy distribution and can thus necessitate a wider receiver bandwidth than might be disired. However the phase-lock apparatus described in said patent for preventing coincidental phase modulation can often prove less than ideal in pulsed RF type transmitters because the time lag in achieving phase correction may exceed approximately (1/f.sub.loop) where f.sub.loop is the bandwidth of the corrector loop.

In accordance with the preferred application of the present invention there is provided a system which prevents the above described coincidental phase modulation on transmitted RF pulses.

These and other objects, advantages and features of the present invention, including applications thereof to modulators and demodulators, will become more apparent upon reference to the following specification, claims, and appended drawings in which:

FIG. 1 is a block diagram schematic illustrating the presently preferred inventive embodiment;

FIG. 2 shows waveforms useful in explaining the operation of the FIG. 1 apparatus;

FIGS. 3 and 4 are block diagram schematics illustrating two possible variations of the FIG. 1 apparatus; and

FIGS. 5 and 6 are block diagram schematics of additional variations, namely, a modulator and a demodulator respectively, embodied in accordance with the principles of the present invention.

In the preferred embodiment illustrated in FIG. 1, a reference CW signal source 11 supplies a carrier signal S.sub.REF of stable phase and frequency to an angularly modulatable element 13 which provides a PAM carrier signal (RF pulse train) S.sub.F whose phase, due to adjustments effected by S.sub.C, is eventually caused to track the phase of carrier signal S.sub.RM. Phase detector 15 receives at separate inputs S.sub.RM and an attenuated version of S.sub.F and outputs a signal S.sub..DELTA. indicative of difference in phase between S.sub.RM and S.sub.F. Comparator 17 receives S.sub..DELTA. and e.sub.R (a constant voltage, usually ground in the FIG. 1 embodiment) and outputs a signal S.sub..epsilon. indicative of the difference in amplitude between S.sub..DELTA. and e.sub.R. To briefly preface a more detailed description hereinbelow, each part of S.sub..epsilon. which is time coincident with an S.sub.F pulse is sampled at regular intervals, the individual samples causing updating or further correcting of corresponding digital words stored in RAM 19. While said updating is being effected the words in RAM 19 which are not yet updated are being outputted and converted into a series of control signals which together constitute the signal S.sub.C and which control phase shifter 21. When lock is attained, phase shifter 21 is caused by S.sub.C to introduce phase modulation complementary to that coincidentally caused by the networks in items 23 and 25 such that the phase of S.sub.F tracks the phase of S.sub.RM. For the FIG. 1 apparatus, the phase .psi..sub.R (t) of S.sub.RM is, except for long term drift, essentially equal to .omega..sub.c t+.alpha., where .omega..sub.c is the radian frequency of the carrier and .alpha. is a non-time-varying, or constant, phase angle. When lock is attained the phase .psi..sub.F (t) of S.sub.F tracks .psi..sub.R (t) such that .psi..sub.F (t)=.psi..sub.R (t)+.beta., where .beta. is a constant phase angle which depends on the constant value K used for e.sub.R.

In the presently preferred implementation, S.sub.RM is a frequency multiple of S.sub.REF and is produced from S.sub.REF by a frequency multiplier 24 as shown in FIG. 1. Multiplier 24 presently comprises a varactor diode multiplier such that the frequency multiple N is twelve. A second frequency multiplier 25, also a varactor diode multiplier whose N=12, is employed as shown in FIG. 1 following item 23.

Also in the presently preferred implementation, comparator 17 comprises a non-hysteretic op-amp comparator having its non-inverting input connected to ground and its inverting input tied to S.sub..DELTA.. Sampling circuit 26 presently comprises a D type flip-flop having its D input connected to S.sub..epsilon., its C or clock input tied to S.sub.2, and its Q output tied to the up/down control input of counter 27. Thus for positive S.sub..DELTA., S.sub..epsilon. is a low logic state, and following an S.sub.2 clock pulse, the Q output is forced low. With its control input low, counter 27 counts up from the count at which it was initialized. Analogously, for negative S.sub..DELTA., S.sub..epsilon. is a high logic state, and, following an S.sub.2 clock pulse the Q output is forced high. With its control input high, counter 27 counts down from the count at which it was initialized. RAM 19 supplies each of these initial counts or digital words to counter 27 and afterward writes the updated count or digital word into the storage location previously occupied by the initializing word. RAM 19 also supplies each of these initial words to latch 29 which, for a predetermined time as determined by S.sub.1, holds each word and outputs same to D/A converter 31. Thus is effected a series of control words, or more generally a series of control signals, which together constitute a composite control voltage or control signal S.sub.C. Adjustments in phase are effected by S.sub.C controlling a varactor in a variable RC network in item 21.

Simultaneous reference will now be made to FIG. 1 and the waveforms of FIG. 2 for a more detailed description of the FIG. 1 apparatus and its operation. As noted hereinabove, in the preferred implementation, S.sub.F is an RF pulse train effected by amplitude modulating S.sub.REF with the pulse waveform S.sub.G. Timing signals S.sub.1 through S.sub.5 are coordinate with one another and with S.sub.G as shown in FIG. 2, all being synchronized by the master clock signal S.sub.CK. As seen in FIG. 2 the time axis of S.sub.G is, for purposes of clarity in illustration, compressed relative to the other illustrated waveforms, the time relationship therebetween being indicated by the vertical dashed lines. More particularly, each S.sub.G or S.sub.F pulse is divided into M sample intervals and each sample interval covers eight master clock or S.sub.CK intervals. The S.sub.G pulses are variable in width and the value of M changes according to said width, the maximum value of M presently being 16.

Looking for example at what happens during the second sample interval (SI.sub.2) of the ith S.sub.G or S.sub.F pulse (P.sub.i), S.sub.5 at the outset effects a new RAM address via address counter 33 and causes the stored word for SI.sub.2 of the preceding S.sub.F pulse, namely P.sub.(i-l), to appear at the RAM 19 output. One S.sub.CK interval later, S.sub.1 causes this word, namely W.sub.SI.sbsb.2.sub.P.sbsb.(i-l), to become loaded into up/down counter 27, thereby initializing 27, and also to become loaded into latch 29. Latch 29 then provides this word (until the next S.sub.1 pulse) to D/A converter 31 which converts same to a control signal and effects adjustment of phase shifter 21. After sufficient time has elapsed for this adjustment to become reflected in S.sub.F and thus S.sub..epsilon. (three S.sub.CK intervals in the present implementation), S.sub.2 effects a sampling of S.sub..epsilon., causing S.sub.Q to go high or low depending on the state of S.sub..epsilon.. Counter 27, depending on the state of S.sub.Q, then adds to or substracts from its initial count the one count effected by the single S.sub.3 pulse. This updated count or word, namely W.sub.SI.sbsb.2.sub.P.sbsb.i , is then written or loaded into RAM 19 at the occurrence of the S.sub.4 pulse thereby replacing the initial word at this RAM address. At the beginning of the third sample inerval SI.sub.3, S.sub.5 effects a new RAM address, namely that for word W.sub.SI.sbsb.3.sub.P.sbsb.(i-l) and the above procedure is repeated. Similarly through the Mth sample interval. For the next S.sub.F pulse, namely P.sub.(i+l), phase adjustments are made according to the RAM words written during the ith pulse P.sub.i and each RAM word is updated to reflect need for additional phase adjustment. And so on until the phase is barely overadjusted, at which time, since the system has no hysteresis, each of the sixteen (or fewer, depending on M) control signals will alternately overadjust slightly and then underadjust slightly like a bang-bang servo. Of course hysteresis could be added by modifying the comparator circuit to include feedback and thus a steady state solution accurate to within one least significant bit could be achieved.

Additional details of the presently preferred implementation are as follows: S.sub.F carrier frequency is approximately 9.33.times.10.sup.9 Hz; S.sub.G and S.sub.F pulse width is variable from approximately 2 to 16 microseconds; PRF of S.sub.G and S.sub.F is approximately 192Hz; frequency of S.sub.CK is approximately 6.94MHz; RAM organization is sixteen 8-parallel-bit words.

To summarize the foregoing, during each S.sub.F pulse the output of the RAM 19 is applied through latch 29 and D/A converter 31 to phase shifter 21 to reduce the phase difference between S.sub.REF and S.sub.F. Also during each S.sub.F pulse, the difference in phase which still remains after the latest adjustment is sampled and used to update the RAM. The updated RAM content is not used to adjust the phase during the pulse it is sampled on but instead is applied later to a successive pulse. During any one S.sub.F pulse a fraction (M/16) of the whole memory is applied to effect phase adjustments and simultaneously (M/16) of the whole memory is updated for effecting later adjustments. The reason that presently detected errors are used to make later occurring corrections or adjustments is that the system is assumed to be pseudo-repetitive pulse to pulse. In other words, the pulse phase distortion characteristic of gate and amplifier 23 and the frequency multiplier 25 varies slowly with respect to the pulse repetition rate and loop bandwidth of the system.

It should be apparent to those skilled in the art that various modifications may be made to the FIG. 1 apparatus without departing from the principles therein involved. For example, phase shifter 21 could be replaced by a VCO (voltage controlled oscillator) controlled by signal S.sub.C. Of course no connection would be needed between reference signal source 11 and such VCO. As a second example, reference signal source 11, which is preferably CW, could be replaced with a pulsed reference source and thus the gate part of item 23 could be eliminated. Further exemplary, phase shifter 21 could be digitally controlled thereby eliminating the need for D/A converter 31; the memory could comprise an analog instead of digital memory; S.sub.3 pulses could be more frequent than one per sample interval. Moreover, a plurality of memory words needs not be updated each S.sub.F pulse. For instance the word for only one sample interval could be updated for pulse one, the word for another sample interval could be updated for pulse two, and so on.

As shown in FIG. 3, an appropriate phase shifter could be relocated at the output (instead of at the input) of item 23. As is also indicated by FIG. 3 (and also by FIGS. 4, 5, and 6), frequency multiplication, as accomplished in the FIG. 1 apparatus by multipliers 24 and 25, is not essential. Further, as shown in FIG. 4, the gate and amplifier 23 could be replaced with an RF pulse generator 41 which is completely independent of the reference signal source 11.

The principles of the present invention may also be employed to realize angle modulators and demodulators. For example, in FIG. 5, if e.sub.R is, say, a sawtooth waveform, the loop will eventually force the phase modulation of the carrier S.sub.F to follow a similar sawtooth variation so that both comparator input signals are the same. Comparator input e.sub.R may comprise other non-constant functions of time. For instance, S.sub.F can constitute a chirp type signal with an appropriate e.sub.R input waveform.

As shown in FIG. 6, a phase demodulator may be realized by setting e.sub.R to some constant value such as ground and connecting a receiver output into an appropriate controllable phase shifter. For an appropriate received signal, the loop will eventually cause S.sub.F to track S.sub.REF at least to within a constant phase angle. When lock is attained, S.sub.C will comprise a functionally related complement of the phase modulation on the receiver output signal. By connecting the receiver output directly into the phase detector and relocating the phase shifter to a position between the reference signal source and the phase detector, S.sub.C will tend to match, instead of complement, the phase modulation on the receiver output signal.

Furthermore, in all foregoing examples, the output signal of the reference signal source has been assumed to contain no angle modulation. That is, .psi..sub.R (t) has been assumed to be essentially equal to .omega..sub.c t+.alpha. where .alpha. is a constant phase angle. This condition is not essential. For instance .psi..sub.R (t) could be equal to .omega..sub.c t+.alpha.(t) where .alpha.(t) is a suitable non-constant function of time.

Furthermore, although the foregoing systems are phaselock systems and thus inherently frequencylock systems, minor modification will yield systems which are frequencylock only; i.e., locked only in frequency and not in phase. More particularly, since instantaneous radian frequency .omega.(t) is classically defined as the first derivative of phase .psi.(t) of a harmonic oscillation Ae.sup.i.psi.(t) ##EQU1## the signal S.sub.66 which is a function of phase difference is also a function of frequency difference. Thus, using FIG. 1 as an example, as signal S.sub.F locks on to signal S.sub.RM such that the phase difference therebetween approaches zero, the frequency difference between S.sub.F and S.sub.RM also approaches zero. Thusly, modification of the FIG. 1 apparatus so as to yield a frequencylock-only system could comprise the replacement of phase shifter 21 with a VCO controlled by S.sub.C and having no input from 11, and the replacement of phase detector 15 with a frequency difference detector.

Further exemplary, suitable combination of the above-described individual modifications will yield additional variations.

Thus while particular embodiments of the present invention have been shown and/or described, it is apparent that changes and modifications may be made therein without departing from the invention in its broader aspects. The aim of the appended claims, therefore, is to cover all such changes and modifications as fall within the true spirit and scope of the invention.