.Mu.-Law to Floating Point Converter

This invention relates to digital signal processing and, more particularly, to the converting of a .mu.-law code word into a floating point representation thereof.

Pulse code modulation (PCM) signals consist, in general, of a series of binary code words wherein each word represents an instantaneous value of a periodically sampled and quantized analog signal. In normal usage these code words are transmitted in the form of a serial bit stream to a receiving station where they are decoded into a reconstructed version of the original analog signal. In between, the processing of the digital signal usually involves various operations being performed on the PCM words. For example, the present inventor in "A Twelve-Channel Digital Echo Canceler", IEEE Transactions on Communications, Vol. COM-26, No. 5 (May 1978), pp. 647-653 discloses an echo canceller employing floating point multipliers. However, the typical PCM word is not in a floating point representation. Hence, a converting operation need be performed to convert the PCM code word into a floating point representation thereof. A floating point representation of a number z is a representation of the form

where S is the polarity, or sign, of the number; A is its mantissa; B is its base, which generally equals two in a binary system; and .varies. is its exponent.

Where the PCM code is linear, i.e., having no compression or expansion, a simple shifting of the binary digits can produce a multiplication or division in powers of two. A linear code is therefore readily adapted to a floating point representation. On the other hand, where the PCM code is nonlinear, e.g., a compressed code, a simple shift does not produce a uniform multiplication or division. The telecommunications art usually employs a nonlinear PCM code.

In a special issue on digital signal processing, an article by A. Kundig, "Digital Filtering in PCM Telephone Systems", IEEE Transactions on Audio and Electroacoustics, Vol. AU-18, No. 4 (December 1970), pp. 412-417 discloses a method for converting a nonlinear PCM word, encoding according to the so-called A-law, into a floating point number representation. The Kundig method succeeds, in part, because of the close relationship between A-law encodings and floating point encodings.

A second nonlinear PCM code, known as the .mu.-law, approximates the compression function: ##EQU1## Known .mu.-law to floating point converter arrangements are of two types. One type includes a memory which, responsive to the PCM word, has extended from a location therein the floating point representation. For a common 8-bit PCM word having one sign bit such arrangements typically employ a memory having at least 2.sup.7 locations, each location with an eight bit floating point representation. The second type is a two stage converter including a .mu.-law to fixed point conversion followed by a fixed point to floating point conversion. Hence, known .mu.-law to floating point converters tend to be expensive.

This and other problems are mitigated in accordance with the principles of my invention by an improved .mu.-law to floating point converter. The converter includes a translator for providing a reference mantissa in response to the segment value of the .mu.-law code word and to a prefixed quantizing step. The floating point mantissa is then obtained by adding the reference mantissa and the quantizing step of the code word. The floating point exponent is the segment value; while the floating point sign is equal to the sign of the code word.

The various features of the present invention will be readily understood from the following detailed description taken in conjunction with the drawings in which:

FIG. 1 is a diagram illustrating a .mu.-law code;

FIG. 2 is a table which shows the analog output levels for a .mu.=255, .mu.-law code;

FIG. 3 is a table which shows the value of the reference and floating point mantissas for a .mu.=255, .mu.-law code; and

FIG. 4 is a diagram illustrating apparatus for converting a .mu.-law code word into a floating point representation thereof in accordance with the principles of my invention.

In considering nonlinear PCM codes, a typical compressed PCM code X(L, V) comprises m binary digits, called "characteristic bits" for representing a segment L, and n binary digits, called "mantissa bits" for representing a quantizing step V in segment L. In addition, it is common that the compressed code include a single polarity bit S. The resultant code word is then a bit stream of length (m+n+1) bits. Also, the total number M of segments in one polarity is equal to 2.sup.m and the total number N of quantizing steps in each segment is equal to 2.sup.n.

The usual compressed digital signal is then given by

and the expanded, or linearized, signal is given by

where for the .mu.-law

where a is the segment edge parameter, i.e., the transition from one segment to the next, and c is the centering parameter, i.e., the off-set of the curve from the origin. In FIG. 1 there is shown a representation of a .mu.-law characteristic curve where c=0. Henceforth, and without loss of generality but rather for ease of description, we consider c=0 and a=0.5 . Furthermore, to simplify the discussion that follows, we assume N=16 (n=4) and M=8 (m=3). Hence, the expanded, or linearized, signal of equation (4), with the aforementioned assumptions incorporated and ignoring momentarily the sign bit, is given by

The polarity of sign, bit is the eighth bit of the PCM code word. The foregoing assumptions are common to the 8-bit, .mu.=255 PCM code word which is used by the Bell System in its digital carrier facilities and which is characterized by a bit stream of the form SL.sub.1 L.sub.2 L.sub.3 V.sub.1 V.sub.2 V.sub.3 V.sub.4 where S is the sign bit; L.sub.1 L.sub.2 L.sub.3 define the particular segment L of the code and are the (m=) three characteristic bits; and V.sub.1 V.sub.2 V.sub.3 V.sub.4 define the quantizing step V and are the (n=) four mantissa bits.

FIG. 2 is a table which shows the analog output levels Y(L, V) from equation (5). From the table it can be seen that a 13-bit linear code will represent the range of values encompassed by the magnitude of the analog signal. Equation (5) can be rewritten in floating representation as

where the exponent L is the segment value and the floating point mantissa U(L, V) is given as:

It should be noted that the mantissa of equation (7) can itself be rewritten as

where U(L, 0) is a reference mantissa having the value of the floating point mantissa for a particular quantizing step, here for V=0. FIG. 3 is a table which shows the floating point mantissa values from equation (7). It should be observed that the first row of the table in FIG. 3 provides the values of the reference mantissa U(L, 0). It is clear that equation (8) can be solved by simply adding quantizing step V to the reference mantissa shown illustratively as the first row value from FIG. 3. It should also be observed that the magnitude of the difference between U(L, V) and its closest, nearly integer (i.e., closest larger or smaller integer as the case may be) does not exceed 15/32. Using the latter observation, consider the set of consecutive integers {0, 1, 2, . . . , 31}. Let U.sub.5 (L, V) denote the integer from the set which integer is the integer closest to U(L, V). Referencing the table in FIG. 3 and the set {0, 1, 2, . . . , 31} it becomes clear that the magnitude of the observed difference between U(L, V) and U.sub.5 (L, V) is less than one-half a quantizing step, i.e.,

As a result, U(L, V) can be approximated by U.sub.5 (L, V) and yet introduce an error no larger than one-half quantizing step. Noteworthy an error of such magnitude is possible in the original quantization. Fortuitously and consistent with the principles of my invention, the expanded signal Y(L, V) can be provided by way of equation (6) using U.sub.5 (L, V) as an approximation of U(L, V) thereby obtaining the floating point representation 2.sup.L U.sub.5 (L, V). Also, U.sub.5 (L, V) can be provided using inexpensive memory or combinatorial apparatus together with simple adder apparatus. Too, only five bits are needed to specify U.sub.5 (L, V).

FIG. 4 includes illustrative apparatus incorporating the principles of my invention. A PCM code word with sign bit S; characteristic bits L.sub.1, L.sub.2, L.sub.3 for representing segment L; and mantissa bits V.sub.1, V.sub.2, V.sub.3, V.sub.4 for representing quantizing step V is provided to respective, parallel input terminals 10; 11-1, 11-2, 11-3; and 12-1, 12-2, 12-3, 12-4 of converter 100, processed thereby and provided as a floating point representation including sign bit S; characteristic bits L.sub.1, L.sub.2, L.sub.3 for representing the exponent; and five-bit floating point mantissa U.sub.5 (L, V) having bits U.sub.5 (L, V).sub.1 through U.sub.5 (L, V).sub.5 respectively to parallel output terminals 20; 21-1, 21-2, 21-3; and 22-1 through 22-5 for extension to floating point apparatus, not shown. More particularly, mantissa bits V.sub.1, V.sub.2, V.sub.3, V.sub.4 are extended in parallel from input terminals 12-1, 12-2, 12-3, 12-4 to respective first inputs of adder 90. Characteristic bits L.sub.1, L.sub.2, L.sub.3 are extended from input terminals 11-1, 11-2, 11-3 jointly to exponent output terminals 21-1, 21-2, 21-3 and to first inputs of translator 200 for providing a 5-bit approximation U.sub.5 (L, 0) of reference mantissa U(L, 0). Specifically, translator 200, responsive to input segment value L, extends an output reference mantissa U.sub.5 (L, 0) in accord with the translation set forth in Table I below:

Table I, it will be seen, reflects the values of U(L, 0) from the first row of the table in FIG. 3, rounded to the closest integer. Translator 200 may be implemented by a memory device or by relatively inexpensive combinatorial logic. Noteworthy, rather than requiring the prior art 2.sup.(m+n=)7 memory locations, converter 100, when implemented using a memory for translator 200, requires only 2.sup.(m=)3 memory locations. My illustrative embodiment of translator 200 is by way of combinatorial logic for providing an output U.sub.5 (L, 0) in accord with Table I responsive to a segment value L.

The output of translator 200 is extended in parallel to second inputs of adder 90. In accord with equation (8), the output of adder 90 is U.sub.5 (L, V) for extension to the output terminals 22-1 through 22-5 concurrently with characteristic bits L.sub.1, L.sub.2, L.sub.3 and sign bit S being extended respectively to output terminals 21-1, 21-2, 21-3 and 20. Advantageously, no clocking logic is needed to convert the .mu.-law code word into a floating point representation thereof.

To still more particularly illustrate the operation of illustrative converter 100, its operation in providing a floating point representation of an expanded signal Y(L, V) having L=5 and V=6 is described. First, turning to FIG. 2, the value of the linearized signal Y(5, 6) is 703.5 while from FIG. 3 the values of U(5, 0) and U(5, 6) are respectively 15-63/64 and 21-63/64. Clearly U(5, 6)=U(5, 0)+6 in accord with equation (8). Using a five bit approximation for U(5, 6) and from Table I above, translator 200 is to provide a value U.sub.5 (5, 0)=16 which in binary format "U.sub.5 (5, 0).sub.5, U.sub.5 (5, 0).sub.4, . . . , U.sub.5 (5, 0).sub.1 " equals the bitstream "10000". Using the .mu.-law to floating point converter of FIG. 4, a floating point representation equivalent to a value of Y(5, 6) equaling 704 is extended to the output terminals of converter 100. That is, referring to equation (1), the polarity is extended to terminal 20; the exponent is extended as a segment value L=5, which in binary is the bitstream "101", to terminals 21-1, 21-2, 21-3; and the floating point mantissa is extended as a value U.sub.5 (5, 6)=16, which in binary is the bitstream "10000", to terminals 22-5 to 22-1 respectively. To obtain U.sub.5 (5, 6), in accord with equation (8), mantissa bits V.sub.1, V.sub.2, V.sub.3, V.sub.4 are extended from terminals 12-1 through 12-4 to respective first inputs of a standard binary adder 90. Adder 90, may for example, be a conventional adder, such as the four bit Texas Instrument adder 74283 having coupled thereto overflow logic 95 including inverters 26 and 27 and NAND gate 60 for providing a logic one, as bit U.sub.5 (L, V).sub.5 to terminal 22-5, when either bit U.sub.5 (L, 0).sub.5 is a logic one or there is a carry logic one from adder 90. In order to obtain U.sub.5 (L, V), the reference mantissa U.sub.5 (L, 0) is extended from translator 200 to respective second inputs of adder 90. The reference mantissa is determined by inverters 20 and 25, NAND gates 30 and 40, included within translator 200. In particular, a segment value L=5 is extended in binary form "101" from respective inputs 11-1, 11-2 and 11-3 of converter 100. Bit L.sub.1, being a binary one, is extended to first inputs of NAND gates 30-2, 30-4 and 30-6 and, after inversion by inverter 50-1, is extended as a binary zero to a first input of NAND gate 30-1. Segment bit L.sub.2, being a binary zero, is extended to a second input of NAND gate 30-2 and a first input of NAND gates 30-3 and 30-5 and, after being inverted to a binary one by inverter 50-2, to a second input of NAND gates 30-1, 30-4 and 30-6. Segment bit L.sub.3, being a binary one, is extended to a third input of NAND gates 30-1 and 30-6 and a second input of NAND gate 30-5 and, after being inverted to a binary zero by inverter 50-3, to a third input of NAND gates 30-2 and 30-4 and a second input of NAND gate 30-3. It being well known that the output of a NAND gate is a logic one if any input is a logic zero, the outputs of NAND gates 30-1, 30-2, 30-3, 30-4, 30-5 are logic ones while the output of gate 30-6 is a logic zero. The NAND gate outputs are inverted by inverter 25 and NAND gates 40-1, 40-2, 40-3, 40-4 to provide U.sub.5 (6, 0) as the bit stream "10000", or U.sub.5 (6, 0)=16, to the second input of adder 90 as per Table I.

Although the invention has been described and illustrated in detail, it is to be understood that the same is by way of illustration only. Various modifications will occur to those skilled in the art. For example, the approximation of U(L, V) by a five bit integer U.sub.5 (L, V) taken from the set of consecutive integers {0, 1, 2, . . . , 31} is only by way of example. The value U(L, V) could be approximated by U.sub.6 (L, V), the closest number in the set {0, 1/2, 1, 11/2, . . . , 31, 311/2} to U(L, V). Only one more bit is needed to specify U.sub.6 (L, V) than to specify U.sub.5 (L, V). Still further approximations exist. Thus, the spirit and scope of the invention are limited only by the appended claims.