US 4,185,320 AGrant
Decoder Circuit
Issue Date:1980-01-22
•11 Claims
•3 Drawing Sheets
Abstract
Disclosed herein is a decoder circuit including: a charge up transistor for maintaining the content of input address signals; a power supply switching transistor for controlling a charge up current which is supplied to the charge up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge up transistor and the power supply switching transistor for selecting an output word line, and; a bootstrap transistor which is connected at an opposide side of the connection node with respect to the charge up transistor. The characteristic feature of the present invention is the provision of a charge compensation transistor which is connected at a connection node between the charge up transistor and the power supply switching transistor so as to compensate for the charges of the charge up transistor.
Metadata
Assignee
- Fujitsu Limited
Inventors
- Yoshihiro Takemae
- Masao Nakano
Application Information
Application Number:US 9641866
Filing Date:1978-11-28
Priority Date:1977-12-12
Art Unit:235
Classifications
IPC:
G11C 1140
Field of Search:
307365238182;189;202;203;204;212
Patent Drawings (3 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a decoder circuit. This decoder circuit is connected to one of a group of word lines which are arranged in a matrix form. Each word line is connected to a large number of binary cells. By using the decoder circuit according to the present invention, one of a large number of binary cells is selected randomly so as to write or read the data.
2. Description of the Prior Art
A dynamic ramdom access memory MOSFET integrated circuit which is conventionally used so as to write or read the data into or from a great number of storage cells is disclosed in U.S. Pat. No. 3,969,706. In FIG. 10 of U.S. Pat. No. 3,969,706, a decoder circuit is connected to one of a group of word lines which are arranged in a matrix form. Each word line is connected to a plurality of storage cells. The decoder circuit determines whether the decoder circuit selects the word line or not. This decoder circuit includes: a charge up transistor for maintaining the content of input address signals; a power supply switching transistor for controlling a charge up current which is supplied to the charge up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge up transistor and the power supply switching transistor for selecting an output word line, and; a bootstrap transistor which is connected at an opposite side of the connection node with respect to the charge up transistor.
In the above described conventional decoder circuit, when noise is generated in the input address signal at a time when the decoder circuit selects the word line, the selection transistor is activated, and the charges at the connection node between the charge up transistor and the power supply source switching transistor are discharged, so that the selection level of the decoder circuit is decreased and, sometimes, a malfunction is caused.
Summary of the Invention
An object of the present invention is to provide a decoder circuit which can prevent a malfunction caused by the generation of noise.
Another object of the present invention is to provide a decoder circuit which has a charge compensation transistor for compensating for the charges of the charge up transistor when the selection level of the decoder circuit is decreased by generation of noise.
For the purpose of achieving above mentioned objects, the decoder circuit according to the present invention comprises: a charge up transistor for maintaing the content of input address signals; a power supply switching transistor for controlling a charge up current which is supplied to the charge up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge up transistor and the power supply switching transistor for selecting an output word line; a bootstrap transistor which is connected at an opposite side of the connection node with respect to the charge up transistor, and; a charge compensation transistor which is connected at a connection node between the charge up transistor and the power supply switching transistor, and which is placed in an on or off state in accordance with the potential level of the output word line so as to compensate for the charges of the charge up transistor.
Further features and advantages of the present invention will be apparent from the ensuing description with reference to the accompanying drawings to which, however, the scope of the invention is in no way limited.
Brief Description of the Drawings
FIGS. 1A and 1B are connection diagrams of a conventional decoder circuit;
FIG. 2, consisting of a-d, is a graphical representations of various waveforms useful in connection with the description related to FIGS. 1A and 1B;
FIG. 3 is a connection diagram of one embodiment of the decoder circuit according to the present invention;
FIG. 4 is graphical representations of various waveforms useful in connection with the description related to FIG. 3;
FIG. 5 is a connection diagram of another embodiment of the decoder circuit according to the present invention, and;
FIG. 6, consisting of a-e, is a graphical representation of various waveforms useful in connection with the description related to FIG. 5.
Detailed Description of the Preferred Embodiment
FIG. 1A illustrates a conventional decoder circuit. This decoder circuit is one of the decoder circuits which are connected to word lines of row and column circuits of a matrix. One example of the connection between address lines for selecting the desired cell in the matrix and the decoder circuit is illustrated in FIG. 1B.
In the decoder circuit illustrated in FIG. 1A, the inputs of each decoder circuit are connected to address lines A.sub.0 or A.sub.0 ; A.sub.1 or A.sub.1 ; A.sub.2 or A.sub.2 ; . . . , and the outputs of each decoder are connected to a word line of a row or column of the matrix. Referring to FIG. 1A, EL designates a power supply line, Q.sub.1 a power supply switching transistor, Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n selection transistors and Q.sub.3 a charge up transistor; Q.sub.4 designates a bootstrap transistor, Q.sub.5 a low level clamp transistor, N.sub.1, N.sub.2 and N.sub.3 connection nodes and .phi..sub.1, .phi..sub.2 and .phi..sub.3 clock pulse signals; Ao-n, Ao-n designate address signals and GND a ground.
In the circuit shown in FIG. 1A, the nodes N.sub.1 and N.sub.2 are charged via the transistor Q.sub.1 to a potential V.sub.DD-V.sub.th, during a precharge period, by using a clock pulse signal .phi..sub.1. Here, V.sub.DD is a power supply voltage and V.sub.th is a threshold voltage of the transistor Q.sub.1. The transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n are connected between the node N.sub.1 and the ground, and gates of the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n are connected to address lines A.sub.0, A.sub.0 ; A.sub.1, A.sub.1 ; A.sub.2, A.sub.2 ; . . . , as shown in FIG. 1B. The charge up transistor Q.sub.3 is connected between the node N.sub.1 and the node N.sub.2 (that is the gate of the transistor Q.sub.4). The bootstrap transistor Q.sub.4 couples a clock pulse .phi..sub.2 to the node N.sub.3. The gate of the transistor Q.sub.3 is connected to the potential level V.sub.DD, so that the potential level at the gate of the transistor Q.sub.4 is driven to a potential higher than the power supply potential V.sub.DD.
In the circuit shown in FIG. 1B, when the transistor Q.sub.1 is placed in the on state by a first clock pulse .phi..sub.1 being applied thereto, as shown in (a) of FIG. 2, the nodes N.sub.1 and N.sub.2 are charged to the potential levels of V.sub.DD -V.sub.th. Charges of the potential levels in the nodes N.sub.1 and N.sub.2 are shown in (e) of FIG. 2.
If we assume that the address signals, A, A, as shown in (d) of FIG. 2, are supplied to the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n, and the address signal A is supplied to selected decoder circuits and the address signal A is supplied to non-selected decoder circuits, the potential levels in the nodes N.sub.1 and N.sub.2 in the selected decoder circuits are not changed, however, the electric charges in the nodes N.sub.1 and N.sub.2 in the non-selected decoder circuits are discharged. This is because at least one of the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n is placed in the on state by being applied the address signal A. These conditions are shown by N.sub.1 ', N.sub.2 ' of chain lines in (e) of FIG. 2.
When a second clock pulse signal .phi..sub.2, as shown in (b) of FIG. 2, is supplied to the transistor Q.sub.4 and the decoder circuit is selected, the second clock pulse signal .phi..sub.2 is coupled by the transistor Q.sub.4 and the level at the node N.sub.2 is increased to a potential higher than that of V.sub.DD +V.sub.th, as shown in (e) of FIG. 2. Therefore, an output signal appears at the node N.sub.3 and the potential level in the node N.sub.3 becomes the potential level V.sub.DD, as shown in (e) of FIG. 2. A third clock pulse, shown in (c) of FIG. 2, is a low level clamping pulse which is supplied to the transistor Q.sub.5.
When the potential at the node N.sub.1 is charged to the potential V.sub.DD -V.sub.th, the transistor Q.sub.3 is kept in the off state. In this state, if a noise signal, as shown in (d) of FIG. 2, is generated in the address signal A at a time the potential level in the node N.sub.3 reaches the level V.sub.DD, at least one of the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n is activated and the charges in the node N.sub.1 are discharged, so that the potential level in the node N.sub.1 is decreased. It should be noted, that such a noise signal as mentioned above is frequently caused in the address signal A. When such a noise signal is generated, the transistor Q.sub.3 is placed in the on state. Therefore, the charges in the node N.sub.2 are discharged, so that the potential level in the node N.sub.2 decreases. Therefore, the transistor Q.sub.4 is placed in the off state, and the potential level in the node N.sub. 3, which should be held at the potential V.sub.DD, is decreased.
FIG. 3 is a connection diagram of one embodiment of the decoder circuit of the present invention. In FIG. 3, the reference symbols which are the same as those of FIG. 1A designate the same components and the same nodes as in FIG. 1A.
The difference between the conventional circuit illustrated in FIG. 1A and the decoder circuit according to the present invention, illustrated in FIG. 3, is that the charge compensation transistor Q.sub.6 is provided between a charge input side of the charge up transistor Q.sub.3, that is, the node N.sub.1 and the power supply line EL, and the transistor Q.sub.6 is switched in accordance with the potential level at the node N.sub.2 between the transistor Q.sub.3 and the transistor Q.sub.4. For example, in the decoder circuit illustrated in FIG. 3, the transistor Q.sub.6 is placed in the on state when the potential level at the node N.sub.2 is increased, so that the power supply voltage V.sub.DD is supplied to the node N.sub.1.
In the decoder circuit illustrated in FIG. 3, the function before the clock signal .phi..sub.2 is supplied is the same as that of the conventional decoder circuit illustrated in FIG. 1A. Therefore, only the function of the circuit illustrated in FIG. 3 after the clock signal .phi..sub.2 is supplied will now be explained with reference to FIG. 4.
When the potential level of the node N.sub.2 is increased, the transistor Q.sub.6 is placed in the on state, so that the power supply voltage V.sub.DD is supplied to the node N.sub.1 from the power supply line. Therefore, if noise is generated in the address signal A, as illustrated in (d) of FIG. 4, at least one of the transistors Q.sub.21, Q.sub.22, Q.sub.23, . . . , Q.sub.2n is instantaneously activated. Therefore, the charges in the node N.sub.1 are discharged and the potential level of the node N.sub.1 is decreased, as shown by N.sub.1 " in (e) of FIG. 4. However, as the power supply voltage V.sub.DD is supplied from the power supply EL to the node N.sub.1 via the transistor Q.sub.6, the drop of the potential level is compensated for instantaneously. The transistor Q.sub.3 is placed in the on state only when the potential level of the node N.sub.1 decreases below the voltage level V.sub.DD -V.sub.th. However, the potential level of the node N.sub.1 does not decrease below the voltage level V.sub.DD -V.sub.th. Therefore, the potential level of the node N.sub.2 does not decrease and the output which is maintained at the potential level V.sub.DD is supplied to the node N.sub.3, as shown in (e) of FIG. 4.
FIG. 5 is a connection diagram of another embodiment of the decoder circuit of the present invention. In the circuit illustrated in FIG. 5, the gate of the charge compensation transistor Q.sub.6 is connected to the node N.sub.3. In the circuit illustrated in FIG. 5, if noise is generated in the address signal A, as illustrated in (d) of FIG. 6, and at least one of the transistor Q.sub.21 through Q.sub.2n is placed in the on state, the greater part of the current which flows via the transistors Q.sub.21 through Q.sub.2n is supplied from the power supply line EL via transistor Q.sub.6. Therefore, the decrease of the voltage in the node N.sub.2 is very small as illustrated by N.sub.2 " in (e) of FIG. 6. Even if the voltage in the node N.sub.2 decreases, the voltage in the node N.sub.3 does not decrease because the mutual conductance gm of the transistor Q.sub.4 has sufficient value.
As described above, in the decoder circuit illustrated in FIG. 5, the voltage in the node N.sub.3 can be maintained even if noise is generated in the address signals A.sub.O through A.sub.n or A.sub.O through A.sub.n and the transistors Q.sub.21 through Q.sub.2n are placed in the on state.
As described above, according to the present invention, malfunction of the decoder circuit can be prevented and the reliability of the decoder circuit can be consierably increased, by only adding one transistor to the conventional decoder circuit, even if noise is generated in the selection transistors of the decoder circuit.
Claims
What is claimed is:
1. A decoder circuit comprising: an output word line for providing input address signals; a charge up transistor, having a charge contained thereon, for maintaining the content of said input address signals; a power supply switching transistor for controlling a charge up current which is supplied to said charge up transistor; a predetermined number of selection transistors for selecting said output word line, said predetermined number of selection transistors operatively connected at a connection node between said charge up transistor and said power supply switching transistor; a bootstrap transistor operatively connected at an opposite side of said connection node with respect to said charge up transistor; a charge compensation transistor, for compensating for the charges of said charge up transistor, operatively connected at a connection node between said charge up transistor and said power supply swtiching transistor, said charge compensation transistor being placed in an on or off state depending upon the potential level of said output word line.
2. A decoder circuit according to claim 1, wherein a gate of said charge compensation transistor is connected to a connection node between said charge up transistor and said bootstrap transistor.
3. A decoder circuit according to claim 1, wherein a low level clamp transistor is connected in series with said bootstrap transistor.
4. A decoder circuit according to claim 3, wherein a gate of said charge compensation transistor is connected to a connection node between said bootstrap transistor and said low level clamp transistor.
5. A decoder circuit operatively connected to an output word line for providing input address signals, and comprising: a charge up transistor, having a charge contained thereon, for storing said input address signals; a power supply means for supplying a charge up current to said charge up transistor; a power supply switching transistor for controlling said charge up current, said power supply switching transistor being operatively connected to said charge up transistor; a predetermined number of selection transistors for selecting said output word line, said predetermined number of selection transistors being operatively connected at a first connection node between said charge up transistor and said power supply switching transistor; a bootstrap transistor operatively connected at a second connection node of said charge up transistor, and a charge compensation transistor for compensating for the charges of said charge up transistor, said compensation transistor being connected to said first connection node and operatively controlled to be in an on or off state in dependence upon the potential level of said output word line.
6. A decoder circuit according to claim 5, wherein a gate of said charge compensation transistor is operatively connected to said second connection node.
7. A decoder circuit according to claim 5, wherein a low level clamp transistor is operatively connected in series with said bootstrap transistor.
8. A decoder circuit according to claim 7, wherein a gate of said charge compensation transistor is operatively connected at a third connection node between said bootstrap transistor and said low level clamp transistor.
9. A decoder circuit operatively connected to an output word line for providing input address signals, and comprising: an FET charge transistor, having a charge contained thereon, for storing said input address signals; a power supply means for supplying a charge up current to said FET charge up transistor; an FET power supply switching transistor for controlling said charge up current; an FET charge compensation transistor for compensating for the charges of said FET charge up transistor, wherein said power supply means is operatively connected to the drains of said FET power supply transistor and said FET charge compensation transistor and to the gate of said FET charge up transistor; a predetermined number of FET selection transistors for selecting said output word line, wherein the sources of said predetermined number of FET selection transistors are operatively connected to ground, each of the gates of said predetermined number of FET selection transistors receives an input address signal, the drains of said predetermined number of FET selection transistors are operatively connected to the sources of said FET power supply switching transistor, said FET charge compensation transistor, and said FET charge up transistor; an FET bootstrap transistor having its gate connected to the drain of said FET charge up transistor, and an FET low level clamp transistor having its source connected to ground and its drain operatively connected to the source of said FET bootstrap transistor.
10. A decoder circuit according to claim 9, wherein the gate of said FET charge compensation charge transistor is operatively connected to the source of said FET bootstrap transistor and the drain of said FET low level clamp transistor.
11. A decoder circuit according to claim 9, wherein the gate of said FET charge compensation transistor is operatively connected to the drain of said FET charge-up transistor and the gate of said FET bootstrap transistor.
Patent Citations (1)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4051388 | 1977-09-01 | Inukai |