US 4,183,093 AGrant
Semiconductor Integrated Circuit Device Composed of Insulated Gate Field-Effect Transistor
Issue Date:1980-01-08
•25 Claims
•5 Drawing Sheets
Abstract
In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprises the fact that insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix. Gate input columns of the transistors are formed of polycrystalline silicon layers, and some of the transistors are enhancement type, while others are depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystalline silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.
Metadata
Assignee
- Hitachi, Ltd.
Inventor
- Hiroto Kawagoe
Application Information
Application Number:US 8922020
Filing Date:1978-03-31
Priority Date:1975-09-04
Art Unit:235
Classifications
IPC:
G11C 1700G11C 1140H03K 1908
Field of Search:
365340307104;182;188166 R205;251
Patent Drawings (5 sheets)
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integrated circuit device composed of insulated gate field-effect transistors (hereinbelow term "MOSIC") and also to a method of manufacturing the same.
2. Description of the Prior Art
In general, a MOSIC uses aluminum or silicon as the material for the gate electrode. On the other hand, there are integrated circuits (IC) in which, in one internal circuit of an inverter stage, a load MOSFET of the enhancement type is employed as the load of a driving MOSFET operative in the enhancement mode (hereinafter called "E/E type IC") and there is an IC in which a load MOSFET of the depletion type is employed (hereinafter called "E/D type IC"). Among the ICs, the silicon gate MOSIC employing the depletion load has recently been extensively adopted as a device which is of higher performance for various uses and has a higher desnity of integration than the aluminum gate MOSIC. According to experiments by the inventor, the occupying area of an Si gate MOS transistor having self-aligned gate structure is reduced by approximately 20 to 30% as compared with that of an Al gate MOS transistor.
As a result of the investigation of MOSICs commercially available as produced by several manufacturers, however, it has been found that, in a read only memory (hereinbelow abbreviated to "ROM") which occupies a considerable part of a MOSIC chip, the size of the single bit of the ROM is not always remarkably smaller in the conventional Si gate ROM structure than in the Al gate one as indicated in the following Table 1:
SUMMARY OF THE INVENTION
It is, accordingly, a principal object of this invention to provide a novel ROM structure which has a conspicuously smaller occupying area than the prior art Al gate or Si gate ROMs, and a method of manufacturing such a novel ROM structure.
Another object of this invention is to provide an IC in which the occupying area of a ROM per unit function in the prior art MOSIC of the Si gate E/D type is conspicuously diminished, and a method of manufacturing such an IC.
Brief Summary of the Invention
According to one aspect of this invention, there is provided a semiconductor integrated circuit device composed of insulated gate field-effect transistors characterized in that the insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix. Gate input columns of said transistors are formed of polycyrstalline silicon layers, and some of the transistors are enhancement type, while others are depletion type.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a fundamental circuit diagram of a prior art MOSROM;
FIGS. 2a and 2b are enlarged plan and sectional views of a part of a prior art MOSROM, respectively;
FIG. 3 is a fundamental circuit diagram of a MOSROM according to the invention;
FIGS. 4a to 4c are enlarged plan and sectional views of a part of the MOSROM according to the invention, respectively;
FIG. 5 is a diagram of an application circuit which adopts the MOSROM according to the invention;
FIGS. 6a to 6f and FIGS. 7a to 7d are enlarged sectional views and plan views of a part of the MOSROM according to the invention for explaining a manufacturing process of the MOSROM, respectively;
FIGS. 8a and 8b are top pattern diagrams of LSI chips of a MOSLSI adopting the invention and a MOSLSI fabricated by a prior art for making a comparison therebetween, respectively, and
FIG. 9b is a diagram showing an example of a circuit in the case of actually employing the MOSROM of the invention, while FIG. 9a is a graph showing the measured results of operating speeds in the circuit of FIG. 9b.
DETAILED DESCRIPTION OF THE PRIOR ART
Hereunder, the improved ROM (MOS matrix) according to the invention will be described in detail in comparison with a prior art Si gate ROM with reference to the drawing.
FIG. 1 shows a fundamental circuit which is used in the prior art Si gate ROM. FIG. 2a is a plan view showing a part of the prior art Si gate ROM on an enlarged scale, while FIG. 2b is a sectional view of the part of the prior art Si gate MOSROM taken along a line X-X' in FIG. 2a.
As is illustrated in FIG. 1, the prior art Si gate MOSROM consists of MOSFETs which are arranged in parallel. The states of the respective memory cells are segregated according to the thicknesses of their gate oxide films. A low level signal close to a supply voltage level is applied to a selected address line, whereas a high level signal close to 0 (zero) volts is applied to an unselected address line. Considering, by way of example, the case where a line IN.sub.2 is selected, the MOSFET beneath this line has a thick gate oxide film and is usually "off", so that the output level becomes low. As is shown in FIGS. 2a and 2b, such a prior art ROM is constructed of P.sup.+ -type diffused layers 2,3 and 4; polycrystalline silicon layers 7 and 8; silicon dioxide films 5 and 6; phosphosilicate glass 9; a through-hole 11; and an aluminum layer 10. The polycrystalline silicon layer is used as an address input line, while the aluminum layer is used as an output line. The through-holes between the Al layer and the P.sup.+ -type diffused layer are necessary for commonly connecting the drain electrodes of the MOSFETs which are arranged at each row. As is apparent from the figures, the states of the memory cells at the points of intersection between the input lines and the output lines are determined by the thicknesses of the gate oxide films. More specifically, where a MOSFET which affects an "on-off" operation in response to signal voltages applied to the input line, required at a certain point of intersection, the gate oxide film beneath the polycrystalline Si layer at that place is made thin, while, where the MOSFET which conducts such operation is unnecessary thereat, the oxide film beneath the polycrystalline Si layer at that place is made thick. Thus, a ROM having a predetermined bit pattern is constructed. The minimum size per unit bit of the Si gate ROM of such a construction is about 410 .mu.m.sup.2, and it is substantially equal to that of the Al gate ROM.
As is described above, a conventional ROM is characterized by the following construction:
(1) The states of the respective memory cells are distinguished by the thicknesses of the gate oxide films.
(2) Since self-aligned gate structure is used, the polycrystalline Si layer cannot cross over the P.sup.+ -type diffused layer. Therefore, an Al wiring layer is necessary, and a through-hole is required between the P.sup.+ -type diffused layer and the Al layer.
Accordingly, the occupying area per bit of the prior art Si gate ROM cannot be made small, in spite of the adoption of self-aligned structure.
DETAILED DESCRIPTION OF THE INVENTION
The Si gate MOSROM according to this invention will now be explained with reference to FIGS. 3, 4a to 4c, and 5.
FIG. 3 shows a fundamental circuit which is employed in the ROM according to this invention. It is composed of a plurality of enhancement mode and depletion mode MOSFETs which are connected in series as driving elements. A depletion mode MOSFET functions also as a resistance element. Read-out is stably executed in such a way that a high level signal close to 0 (zero) volts is impressed on a selected address line. At this time, a low level signal is impressed on an unselected address line.
By way of example, where the address line IN.sub.2 is selected, the MOSFET beneath this address line IN.sub.2 turns "on", since it is a depletion mode MOSFET. Since the MOSFETs associated with the address lines IN.sub.1, IN.sub.3, . . . and IN.sub.n are enhancement mode MOSFETs, they turn "on" by having a low level signal applied to their gates. Since the MOSFET associated with the address line IN.sub.n-1 is a depletion mode MOSFET, it is "on" even when a low level signal is applied to its gate. In this case, accordingly, all the driving elements are substantially "on", so that an output signal of a high level close to 0 (zero) volts is produced at an output terminal OUT.
On the other hand, where the address line IN.sub.3 is selected, the MOSFET associated with this line becomes nonconductive (off) in response to an input signal of high level since it operates in the enhancement mode. Therefore, an output signal of low level appears at the output terminal OUT.
As is apparent from the above explanation, in the ROM according to this invention, the output data line to be precharged is maintained at a low level or is shifted to a high level in dependence on whether an enhancement or a depletion mode MOSFET is addressed, respectively.
FIG. 5 shows a ROM circuit which is constructed by applying this invention to an actual MOSIC ROM on the basis of the fundamental circuit of the invention illustrated in FIG. 3, and which comprises a first address decoder MOS matrix and a second MOS matrix receiving an output of the first MOS matrix as its input. A flip-flop circuit 21 consists of a plurality of stages (for example, k/2 stages) connected in cascade. Outputs from the respective stages are delivered directly or through inverter circuits 22 into the first MOS matrix 23, whose outputs are delivered into the second MOS matrix 24. The second MOS matrix provides outputs OUT 1 to OUT n. The matrices 23 and 24 have one MOSFET operative in the depletion or enhancement mode in any of the places in which input lines and output lines intersect. Such FETs are connected in series between a supply voltage V.sub.DD and a reference potential source (earth) at every column. Connected to the respective matrices as loads of the driving MOSFETs are enhancement mode MOSFETs (27,28) which have clock signals applied to the gates thereof. In the figure, the driving MOSFETs with circles as indicated at 25 are those operating in the depletion mode, while the other driving MOSFETs are those operating in the enhancement mode.
Each of the plurality of inverters 22 consists of a driving MOSFET which operates in the enhancement mode, and a load MOSFET which is connected in series therewith and which operates in the depletion mode. As will be described later, all the MOSFETs in the figure have gate insulating films (for example, SiO.sub.2 films) of substantially equal thicknesses (about 500 to 1,500 angstrom) irrespective of whether they are depletion type or enhancement type. The depletion type MOSFETs in the MOS matrices are formed simultaneously with the depletion type MOSFETs in the inverters 22 by the same process. The input lines of the first and second matrices are formed of polycrystalline silicon wiring layers, while the connection from the output line of the first matrix to the input line of the second matrix is effected by the use of an aluminum wiring layer which connects a P.sup.+ -type diffused layer and the polycrystalline Si layer. When FIG. 5 is studied with reference to FIG. 3, the operation of the circuit in FIG. 5 will be self-explanatory. To be particularly mentioned is that clock pulses .phi..sub.1 and .phi..sub. 2 whose phases differ from each other are impressed on the gates of the load MOSFETs in the first and second matrices, respectively, and that the amplitudes of these pulses (for example, -12 to -16 volts) are greater than the amplitude of the supply voltage V.sub.DD (for example, -6 volts).
Referring now to FIGS. 4a to 4c, the device structure of the MOSROM according to this invention will be described. FIG. 4a is a plan view with a part of the MOSROM enlarged, while FIGS. 4b and 4c show X-X' and Y-Y' sections in FIG. 4a, respectively. In the figures, numeral 31 designates an N-type single crystal Si substrate; numerals 32 and 34 and numerals 47 to 49 are P.sup.+ -type diffused layers which are formed by being self-aligned by Si gate electrodes; numerals 35, 36, and 43 are gate insulating films of silicon dioxide which have essentially equal thicknesses (about 1,000 A); numerals 37 and 38 are input lines of polycrystalline Si; numeral 39 is an insulating film of phosphosilicate glass; numerals 41 and 42 represent P-type channel layers which are formed by implanting P-type impurity ions into selected areas of the surface of the substrate in order to form the depletion MOSFETs; and numerals 44 to 46 are field insulating films of silicon dioxide which are comparatively thick (about 1 to 2.mu.). As is apparent from the figures, one memory cell is formed in any of the places of intersection between the polycrystalline Si wiring layers (37,38) as the address input lines and the P.sup.+ -type diffused layers as the self-connected data output lines. The states of the respective memory cells are determined by the presence or absence of the P-type channel formed by the ion implantation. All the memory cells have the thin gate oxide films so as to operate as an enhancement or depletion MOSFET.
As is seen from the figures, the MOS matrix according to this invention has self-aligned gate structure and needs no through-hole. It will therefore be understood that the occupying area for a single bit is remarkably smaller in the MOS matrix of this invention than in the prior art.
FIGS. 8a and 8b show, by comparison, the semiconductor chip sizes and the occupying areas of respective circuits in the cases where MOSICs for achieving the same circuit function are formed by the technique of this invention and by the Si gate MOS manufacturing technique of the prior art, respectively. By the adoption of the MOS matrix according to this invention, in comparison with the case of simply adopting self-aligned type Si gate MOSROM, the ROM part which occupies a comparatively large area in the LSI is reduced by approximately 50%. As a result, it becomes possible to decrease the overall chip size by approximately 20%.
The operating speed of the ROM according to this invention will now be explained with reference to FIGS. 9a and 9b. Since a ratioless circuit as shown in FIG. 9b is employed, the output level of the ROM has two states, and as previously set forth, the precharged data line holds the low level or is shifted to the high level. In this case, the operating speed of the ROM is mainly dependent upon the discharge time t.sub.d in which the precharged data line is shifted to the high level. FIG. 9a illustrates the measurements of the relationship between the discharge time of the MOSROM shown in FIG. 9b (the ordinate t.sub.d) and the amplitude of the clock pulse supplied to the gate of the load MOSFET of the enhancement mode (the abscissas V.sub.cp), the MOSROM possessing 48 address lines and having 48 enhancement or depletion MOSFETs connected in series. Herein, the output capacitance of the ROM is approximately 1.5 pF. As is seen from the graph, the discharge time is smaller than 1.5 .mu. s. Especially as an IC for an electronic desk top calculator, no problem is posed in practical use because operation on the order of 100 KHz is possible.
Description will now be made of a method of manufacturing the MOSROM according to this invention as shown in FIGS. 4a to 4c and FIG. 5, reference being had to FIGS. 6a to 6f and FIGS. 7a to 7d. First, an SiO.sub.2 film about 1.4.mu. thick is formed in the surface of an N-type Si single crystal substrate 31, whose one principal surface is the (1 1 1)-face and which has a specific resistance of 5 to 8 cm. Thereafter, those parts of the SiO.sub.2 film on the principal surface of the substrate at which the MOSFETs are to be formed are moved in the shape of narrow slots. The exposed substrate surface is oxidized to form a thin SiO.sub.2 film 30 (gate oxide film) of about 1,200 A (refer to FIGS. 6a and 7a).
Subsequently, boron ions are implanted into the substrate surface through the thin SiO.sub.2 film 30 at a concentration of about 1.4.times.10.sup.11 k/cm.sup.2. Further, a photoresist material layer 50 is deposited onto that part of the thin oxide film 30 on the substrate surface at which the depletion MOSFET is not to be formed. Using the photoresist layer and the thick oxide film as a mask, boron ions are again implanted into the substrate surface through the exposed thin SiO.sub.2 film at a concentration of 6.5.times.10.sup.11 k/cm.sup.2. Thus, the P-type region 41 which constitutes the channel of the D-MOSFET is formed (refer to FIGS. 6b and 7b).
Subsequently, the photoresist layer is removed. Polycrystalline silicon is deposited on the entire oxide films to a thickness of about 5,000 A. Those parts of the polycrystalline Si layer which are other than the parts for constructing the address lines (37, 38) are removed (refer to FIG. 6c). Subsequently, using the parts 37 and 38 of the polycrystalline Si layer remaining, the thin SiO.sub.2 film 30 is removed to expose the substrate surface (refer to FIGS. 6d and 7c).
Subsequently, by employing the polycrystalline Si layer 37, 38 and the thick SiO.sub.2 film 40 as a mask, boron is diffused into the exposed substrate surface by the conventional vapor diffusion process. Thus, the P.sup.+ -type diffused regions 32,33,34,47,48 and 49 having a thickness of about 0.8.mu. are formed (refer to FIGS. 6e and 7d.
Thereafter, phosphosilicate glass (PSG film) 39 having a thickness of about 0.9 to 1.mu. is deposited from vapor phase, to complete the MOSROM as shown in FIG. 6f. In this way, there is produced a MOS matrix of the present invention which comprises the combination of enhancement mode and depletion mode MOSFETs having the gate oxide films of substantially equal thicknesses. As is described above, in the MOS matrix of this invention, the respective input lines of polycrystalline Si and the respective P.sup.+ -type diffused layers intersect substantially orthogonally, and all the insulating films beneath the polycrystalline Si layers at any place of the intersection have a thickness of about 1,200 A, so that transistor operation is positively carried out.
Which transistors are made the depletion type is determined by the implantation of the boron ions as illustrated in FIG. 6b. Such a technique of fabricating the depletion MOSFETs is not especially added, but in case of forming the circuit as shown in FIG. 5 or FIG. 9b within the surface of a single semiconductor substrate, the aforecited MOSFETs are fabricated by the same process as that of the other depletion MOSFETs, for example, the depletion load MOSFETs of the inverters.
To sum up, the ROM according to the invention has the following features:
(1) The ROM of the invention is constituted of the enhancement type and depletion type MOSFETs as the driving elements.
(2) The size of the ROM of the invention is remarkably small, and it is reduced by about 50% as compared with that of the ROM of the prior art Si gate structure.
(3) The ROM of the invention is fabricated by a process which is compatible with the Si gate MOSLSI employing the depletion loads presently being extensively used.
(4) A cascade ratioless circuit is applicable to the ROM of this inventon, and LSIs with extraordinarily excellent characteristics can be realized by paying sufficient attention to the estimation of the operating speed.
The general principle of the invention as described above can also be applied to other complicated logic circuits such as a programmable logic array and a four-phase ratioless dynamic circuit. It is accordingly to be understood that the scope of the present application is not restricted to the foregoing specific aspects of performance.
Claims
I claim:
1. A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; first and second matrices each including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and said transistors in each row are connected in series; and wherein said second matrix is connected in cascade with said first matrix.
2. A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are connected in series; a plurality of clock controlled insulated gate field effect transistors each source electrode of which is connected in series with the drain of the transistor connected at one end of each row; and wherein the clock controlled transistors are enhancement type and selected ones of the transistors in said matrix are depletion type.
3. A semiconductor integrated circuit device according to claim 2, wherein for each respective row, the source of a field effect transistor in a respective column is contiguous with the drain of a field effect transistor in an adjacent column and the gates of each transistor in a respective column of said matrix are formed of a common gate electrode layer.
4. A semiconductor integrated circuit device according to claim 3, further comprising means for applying a plurality of coded true inputs to said common gate electrode layers; and a plurality of inverter circuits for applying the complements of said coded true inputs to said common gate layers, each inverter circuit including a driving insulated gate field effect transistor operating in the enhanchement mode and a load insulated gate field effect transistor operating in the depletion mode and being connected in series with said driving transistor.
5. A semiconductor integrated circuit device according to claim 4, wherein some of said transistors in said matrix are depletion mode transistors so as to form a decoder.
6. A semiconductor integrated circuit device according to claim 5, wherein the source of the transistor connected at the other end of each row is connected to a ground terminal and the drains of the clock controlled transistors are connected to a power source terminal.
7. A semiconductor integrated circuit device according to claim 5, further comprising a read only memory matrix made up of a plurality of insulated gate field effect transistors disposed in rows and columns, the transistors in each row being connected in series, and further including a multiplicity of enhancement mode insulated gate field effect transistors the source electrode of each of which is connected in series with the drain of the transistor connected at one end of each row of said read only memory matrix, and to the gate electrode of each of which there is applied a second clock pulse, and wherein said read only memory matrix is connected in cascade with said decoder matrix.
8. A semiconductor integrated circuit device according to claim 7, wherein the source of the transistor connected at the other end of the row of each matrix is connected to a ground terminal and the drains of the transistors controlled by said first and second clock pulses are connected to a power source terminal.
9. A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns; and a plurality of logical circuits each including a driving insulated gate field effect transistor and a load insulated gate field effect transistor being arranged in and on said body; and wherein said load transistors and selected ones of said transistors in said matrix are depletion type and said driving transistors and other transistors in said matrix are enhancement type.
10. A semiconductor integrated circuit device according to claim 9, wherein said load transistors of said logical circuits and said selected transistors in said matrix are simultaneously formed as depletion type transistors by ion implantation of impurities determining a conductivity type opposite to that of said semiconductor body.
11. A semiconductor integrated circuit device according to claim 10, wherein for each respective row, the source of a field effect transistor in a respective column is contiguous with the drain of a field effect transistor in an adjacent column and the gates of each transistor in a respective column of said matrix are formed of a common gate electrode layer.
12. A semiconductor integrated circuit device according to claim 11, further comprising means for applying a plurality of coded true inputs to said common gate electrode layers, wherein said logical circuits are constructed as inverter circuits for applying the complements of said coded true inputs to said common gate layers.
13. A semiconductor integrated circuit device comprising: a plurality of field effect transistors connected between an output terminal and a reference terminal such that, when said transistors conduct in response to input signals applied to the gates thereof, the conduction paths between the source and drain thereof form a series current path between said output terminal and said reference terminal, and wherein at least one of said transistors is a depletion mode field effect transistor.
14. A semiconductor integrated circuit device according to claim 13, wherein the others of said transistors are enhancement mode field effect transistors.
15. A semiconductor integrated circuit device according to claim 14, further comprising an enhancement mode field effect transistor having a source connected to said output terminal, a drain connected to a voltage source terminal and a gate connected to a clock pulse source.
16. A semiconductor integrated circuit device according to claim 15, wherein to the gate of all of said transistors connected between said output terminal and said reference terminal, data input signals, other than clock pulse signals, are applied.
17. A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and said transistors in each row are connected in series; a plurality of clock controlled insulated gate field effect transistors each source electrode of which is connected in series with the drain of the transistor connected at one end of each row is applied.
18. A semiconductor integrated circuit comprising: a first matrix including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form, in which said transistors are located along a plurality of rows and columns and said transistors in each row are connected in series; and a plurality of first gate lines corresponding to said columns of transistors, the gates of each column being connected in common to the corresponding first gate lines.
19. A semiconductor integrated circuit according to claim 18, further comprising a second matrix including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form in which said transistors are located along a plurality of rows and columns and said transistors in each column are connected in series; a plurality of second gate lines corresponding to said rows of transistors, the gates of each row being connected in common to the corresponding second gate lines; and wherein each said second gate line is connected to the drain of the transistor connected at one end of each row in said first matrix.
20. A semiconductor integrated circuig according to claim 19, wherein each said second gate line is connected to a power source terminal through a switching insulated gate field effect transistor.
21. A semiconductor integrated circuit comprising: a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form in which said transistors are located along a plurality of rows and columns and said transistors in each row are connected in series; a plurality of input terminals corresponding to said columns of transistors, the gates of each column being connected in common to the corresponding input terminals; a plurality of output terminals in which each said output terminal is connected at one end of each row of series connected transistors; and a common reference terminal being commonly connected at the other end of each row of series connected transistors; and wherein when said transistors conduct in response to input signals applied to said input terminals, at least one of said row of series connected transistors forms a series current path between the output terminal thereof and said common reference terminal.
22. A semiconductor integrated circuit according to claim 21, further comprising a plurality of enhancement mode field effect transistors, each having a source connected to each said output terminal of said row of series connected transistors, a drain connected to a common source terminal and a gate connected to a common clock pulse source.
23. A semiconductor integrated circuit according to claim 22, wherein data input signals, other than a clock pulse signal, are applied to said input terminals.
24. A semiconductor integrated circuit comprising: a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being connected in series; a logical circuit including a driving insulated gate field effect transistor and a load insulated gate field effect transistor each having a source, a drain, and a gate; and wherein one end of said series connected transistors is connected to the gate of said driving transistor, the other end of said series connected transistors is connected to a ground terminal, said load resistor and at least one of the transistors in said series connected transistors are depletion type, and said driving transistor and the other transistor of said series connected transistors are enhancement type.
25. A semiconductor integrated circuit according to claim 24, further comprising an enhancement type insulated gate field effect transistor having a source connected to said one end of said series connected transistors, a drain connected to a source terminal, and a gate connected to a clock pulse source.