Pulse Shaping Circuit

1. Field of the Invention

This invention is directed to a pulse shaping circuit and in particular to such a circuit that shapes an input pulse signal for obtaining a trigger pulse signal synchronous with the input pulse signal.

2. Discussion of the Prior Art

Conventional circuits for achieving trigger pulses to trigger multivibrator circuits comprise a differentiation circuit 3 having a condenser C.sub.1 and a resistor R.sub.1. Specifically, when an input pulse signal as shown in FIG. 2(A) is imposed at input terminal 1, the differentiated output pulse signal as shown in FIG. 2(B) is produced at the output terminal 2. This output pulse signal is used as a trigger pulse. However, a sufficient amplitude is not produced when a trigger pulse with a small pulse width is generated by this conventional circuit. Further, the pulse width is not sufficiently small when a trigger pulse of a high amplitude is to be generated.

This invention comprises a pulse shaping circuit which can deliver a trigger pulse with a small pulse width and sufficiently high amplitude, eliminating these problems.

Other objects and advantages of this invention will be apparent from a reading of the following specification and claims taken with the drawing.

FIG. 1 is a schematic circuit diagram of a conventional pulse shaping circuit.

FIGS. 2(A) and 2(B) are pulse wave shapes illustrating the operation of FIG. 1.

FIG. 3 is a schematic circuit diagram of an illustrative embodiment of a pulse shaping circuit in accordance with this invention.

FIGS. 4A, 4B and 4C are pulse wave shapes illustrating the operation of FIG. 3.

FIG. 5 is a schematic circuit diagram of a further illustrative embodiment of a pulse shaping circuit in accordance with this invention.

FIG. 3 is a schematic circuit diagram of one illustrative embodiment of a pulse shaping circuit in accordance with this invention. In the Figure 4, is a difference amplifier comprising transistors Q.sub.1 and Q.sub.2. The base of transistor Q.sub.1 is connected to input terminal 1 through condenser C.sub.2. In addition, it is connected via resistance R.sub.4 to resistances R.sub.2 and R.sub.3 which are linked in series with a primary power source +B.sub.1. The emitter is connected to a constant current source S.sub.1. The collector is connected with a second power source +B.sub.2 via resistance R.sub.5. The base of transistor Q.sub.2 is connected to the contact point of resistances R.sub.2 and R.sub.3 via resistance R.sub.6. The emitter is connected to constant current source S.sub.1 and the collector is connected to primary power source +B.sub.1 via resistance R.sub.7. The line voltage +V.sub.B1 of primary power source B.sub.1 is set at a higher level than the line voltage +V.sub.B2 of second power source +B.sub.2. Condenser C.sub.3 is connected between the collector of transistor Q.sub.2 and the ground. This condenser C.sub.3 and resistance R.sub.7 form an integration circuit 5. 6 is a logical operation circuit which performs a logical product or AND operation. It comprises diodes D.sub.1, D.sub.2 and a difference amplifier based on transistors Q.sub.3 and Q.sub.4. The base of transistor Q.sub.3 is connected via diodes D.sub.1 and D.sub.2 to the collectors of transistors Q.sub.1 and Q.sub.2. In addition, it is connected via resistance R.sub.8 to second power source +B.sub.2. The emitter is connected to a constant current source S.sub.2. The collector is connected to second power source +B.sub.2. The base of transistor Q.sub.4 is connected to the contact point of R.sub.10 and R.sub.9 which are connected in series with second power source +B.sub.2. The collector is linked with second power source +B.sub.2 via resistance R.sub.11 and with an output terminal 2.

When an input pulse signal as shown in FIG. 4(A) is applied to input terminal 1, transistor Q.sub.1 is on and transistor Q.sub.2 is off when this input pulse signal is at a high level. Transistor Q.sub.1 is off and transistor Q.sub.2 is on when the signal is at a low level. An output pulse signal from the collector of transistor Q.sub.1 is produced as shown by curve a in FIG. 4(B). An output pulse signal with a phase opposite the collector output of transistor Q.sub.1 is produced at the collector of transistor Q.sub.2. The output pulse signal from the collector of transistor Q.sub.2 is integrated by condenser C.sub.3 of integration circuit 5 and an output signal as shown by curve b in FIG. 4(B) is produced. The output of integration circuit 5 and the collector output of transistor Q.sub.1 are applied to diodes D.sub.1 and D.sub.2 and the logical product thereof is obtained. When at least one of these output levels is lower than the threshold level determined by transistor Q.sub.4, resistance R.sub.9 and resistance R.sub.10, the transistor Q.sub.3 is off and transistor Q.sub.4 is on. When the levels of both outputs exceed the threshold level, transistor Q.sub.3 switches on while transistor Q.sub.4 switches off. At that time, an output pulse signal like the one shown in FIG. 4(C) is produced at output terminal 2. Accordingly, the output pulse signal achieved at output terminal 2 is synchronous with the input pulse signal and it has a small pulse width. It is a pulse signal appropriate for use as a trigger pulse signal.

Since the line voltage of primary power source +B.sub.1 connected to transistor Q.sub.2 and to the integration circuit 5 is higher than the line voltage of the second power source +B.sub.2, it is possible to select a small amplitude output pulse signal from the collector of transistor Q.sub.1 and prevent radiation.

FIG. 5 is a schematic circuit diagram of a further embodiment of a pulse shaping circuit in accordance with the invention. The second line voltage of FIG. 4 is implemented by a constant voltage circuit comprising resistances R.sub.12, R.sub.13 and transistor Q.sub.5 connected to primary power source +B.sub.1. Moreover, the constant current source S.sub.1 comprises resistances R.sub.14, R.sub.15, R.sub.16 and transistor Q.sub.6. The constant current source S.sub.2 comprises resistances R.sub.17, R.sub.18, R.sub.19 and transistor Q.sub.7. The diode D.sub.3 is connected between the emitter of transistor Q.sub.5 and the base of transistor Q.sub.4. The threshold level of the logical AND operation of logical operation circuit 6 is thus determined. In any case, a very stable logical AND operation can be implemented if the amplitude of the output pulse signal from the collector of transistor Q.sub.1 is about double the forward voltage drop of diode D.sub.3.

As indicated above, with the simple circuitry of this invention, a very stable trigger pulse is obtained in which the pulse width of the trigger pulse is sufficiently small and the amplitude is sufficiently large. Moreover, this pulse shaping circuit can easily be integrated.