Digital Scale

1. Field of the Invention

This invention concerns weight measuring apparatus. More particularly, the invention is concerned with a weighing scale system having an improved analog-to-digital conversion means including a microcomputer which forms an integral part thereof and to the rapid and accurate conversion from pounds to kilograms and visa versa. In accordance with this invention, the weight indication of an object to be weighed may be changed from pounds to kilograms either before or during a weighing operation. The various weight limits and the tare weight is changed. The price per unit and the total value may be either changed or the indication cleared when the change is made during a weighing operation.

2. Description of the Prior Art

Weighing and computing scales must meet several stringent requirements for performance and cost. The scales must be accurate enough to satisfy public weights and measures authorities, yet be available at a reasonably affordable price and perform their operations within a period of time which is convenient for sales transactions.

One of the important factors in digital scales upon which cost, accuracy, and operation time depends, is the conversion of the unknown analog weight signal corresponding to an article weight to digital data representative of the article weight.

In the past, in order to change from weighing operations in pounds to weighing operations in kilograms, it has been necessary to change certain switches under the scale cover and to also make final adjustments of certain circuit elements so the scale will accurately weigh in either pounds or kilograms. In the scale arrangements of the prior art, it is not possible to change the stored tare weight from pounds to kilograms or visa versa during a weighing operation. Neither has it been possible to automatically change the unit price and then recompute the total value during a weighing operation. Typical prior art multicapacity digital computing scale arrangements are described in U.S. Pat. Nos. 3,962,569 Loshbough et al; 3,962,570 Loshbough et al; and 3,986,012 Loshbough et al; and U.S. application Ser. No. 729,911 filed Oct. 3, 1976, Donivan L. Hall et al.

There is, therefore, a need for a digital weighing and computing scale having a relatively simple design which is capable of easily, rapidly, more effectively, and more accurately changing from weighing operations in terms of pounds to weighing operations in terms of kilograms or from weighing operations in terms of kilograms to weighing operations in terms of pounds. There is also a need to make such changes either before or during weighing operations. There is also a need to change the stored tare weight and unit price and the computed total value.

The present invention achieves the foregoing needs by providing a digital weighing and computing scale system which employs a microcomputer data processing means which is used for controlling the sequence of operations and computing the required data for the scale system. In accordance with this invention a lb/kg switch is provided. When in the lb position, the weight indications are in pounds. When in the kg position, the weight indications are in kilograms. When the position of this switch is changed either before or during a weighing operation, all the stored weight data including the tare weight is changed to the new units and the weight indicated in accordance with the position of this switch. In addition, the unit price is either converted to the value in accordance with the position of this switch or the stored unit price is cleared depending upon the condition of other switches. If the unit price is converted, then the total value is recomputed. If the unit price is only cleared, then the total value is also cleared. If the unit price is cleared, then a new unit price must be entered before the total value can be computed.

In order for a weighing scale to be able to provide a choice of full scale capacities, it is necessary that the weight signal or data be modified in either its analog form or its digital form in a manner which is dependent upon the particular scale capacity and units of weight which are selected.

The weight can be detected according to a single one of several possible scale capacities and weight units and then multiplied by an appropriate conversion factor when another scale capacity is selected. This, however, requires that a computer of such a weighing scale have a more complex sequence of operations because for each selected scale capacity, it must deal with substantially different numbers in performing all of its various checks and control functions.

Alternatively, the analog weight signal may be amplified by an amplification factor which is unique for each scale capacity. This selective modification of the analog gain has the disadvantage that it requires the use of either adjustable or multiple circuit elements, such as resistors, in the analog circuitry, one of which must be manually switched into the circuit for each selected amplification factor corresponding to each selected scale capacity. The use of such alternatively selectable circuit elements requires a substantial additional expense and creates problems in calibration.

These problems can be reduced by causing the full capacity analog weight signal for each scale capacity to produce the same digital number at the output of the analog to digital converter. This also permits a single span control to set the full capacity output for all selectable scale capacities. For example, in the exemplary embodiment of the present invention, a full scale weight for each scale capacity will produce a digital output of 30,000 net effective weight increments which are termed raw weight increments. The number of raw weight increments is then multiplied by a factor, depending upon the scale capacity to obtain the proper weight units.

It is a unique feature of the present invention that it provides substantially the same digital data with a full capacity weight for all selected scale capacities without requiring multiple circuit elements and without requiring modification of the analog circuit gain. This unique aspect of the present invention is provided by the microcomputer implementation of the analog-to-digital conversion.

Another unique feature of the present invention relates to the computing and displaying of a net weight. The prior art includes weighing and computing scales upon which a food container or other tare weight may be placed, weighed and have the tare weight entered into memory. This stored tare weight is available for later subtraction from the gross weight of the filled container to compute and display the net weight of the contents .

FIG. 1 is a block diagram illustrating the apparatus of the exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating the layout and relative interrelationship of the circuit diagrams of FIGS. 3 through 8 and is shown on the same sheet as FIG. 10.

FIGS. 3 through 8 show the detailed circuitry of an exemplary embodiment of the invention.

FIGS. 9 through 11 are block diagrams of the integrated circuits forming the central processor, memory and general purpose keyboard and display interface devices used in combination with the circuitry of the exemplary embodiment of the invention.

FIG. 12 is a diagram illustrating the operation of the exemplary embodiment of the invention.

FIG. 13 is a random access memory assignment table illustrating the assignments for the memory of the exemplary embodiment of the invention.

FIGS. 14A through 14Z and 14AA through 14DD are flow diagrams illustrating the operation of the preferred embodiment of the invention. FIG. number 14Q is not used for clarity.

In describing the preferred embodiment of the invention illustrated in the drawings, specific terminology will be resorted to for the sake of clarity. However, it is not intended to be limited to the specific terms so selected, and it is to be understood that each specific term includes all technical equivalents which operate in a similar manner to accomplish a similar purpose. For example, the term connection is not necessarily limited to direct connection but also includes connection through other circuit elements.

The means, apparatus, and structure, by which the above novel improvements, in accordance with the present invention, are achieved in the exemplary embodiment described herein, comprises various registers, counters, timers, flags, storage spaces, together with specific routines for the control of the respective apparatus or means by the central control unit. In addition, numerous switches, lamps and display devices cooperate with the central control unit and the various storage spaces, counters, timers, etc., which apparatus comprises input and output means for the system.

The exemplary embodiment of this invention described herein is incorporated in and arranged to cooperate with the digital weighing and computing scale disclosed in the copending U.S. patent application of R. C. Loshbough and E. G. Pryor Ser. No. 824,858 filed Aug. 15, 1977; which application is fully incorporated herein. The exemplary embodiment described herein discloses features claimed in the above application or in applications referred to in the above application.

The exemplary embodiment of the invention is illustrated in the block diagram of FIG. 1. A load cell 40 mechanically support a platter 12 and is supplied with electrical energy by a power source 42. The load cell applies an analog weight signal through a preamplifier 44 and filter 46 to a switching circuit 50. The analog weight signal has an amplitude which is dependent upon the weight supported by the load cell 40.

The switching circuit 50 is also connected to the power supply so that not only the analog signal but also two reference DC sources can be sequentially applied to the integrator 51 during the performance of a triple slope A/D conversion. The output of the integrator is amplified by an amplifier 52 and applied to a threshold detector so that the crossover of the integrator output with its reference output level is detected by the threshold detector 53. The output of the amplifier is also connected to the switching means 50 for use in resetting the integrator 51. The output of the threshold detector 53 is applied to a microcomputer 54 which is also connected to the switching circuit 50 for controlling its switching functions.

The microcomputer 54 is connected to a printer 28 and through latch decoder and driver circuitry 56 to indicator lamp displays 26. Operational mode selector switches 22 are also connected to data input terminals of the microcomputer 54.

The microcomputer is further connected to a general purpose keyboard and display interface 58 for receiving data from a keyboard 20 and transmitting data through a decorder/driver 60 to digit displays 24. The "PREPACK ON/OFF" switch 16 and the "Z" key 17 are individually connected to discrete inputs to the microcomputer 54.

In this exemplary embodiment, the analog-to-digital conversion is performed by the combination of the switching circuit 50, the reference DC sources derived from the power source 42, the integrator 51, the threshold detector 53 and the microcomputer 54. The amplifier 52 is provided to amplify the integrator output so that the threshold detector will more accurately determine when the integrator output crosses the threshold voltage.

The microcomputer 54 includes storage registers in which the elapsed time counts, which are derived from a microcomputer instruction loop, are accumulated. It also includes stored data for each scale capacity. The microcomputer 54 includes a central processor, associated memory and stored data for controlling the switching circuit 50 to appropriately apply the inputs to the integrator 51 in the proper sequence and at the proper time, for interrogating the ouput of the threshold detector 53, and for arithmetically processing the accumulated elapsed time intervals or counts.

FIG. 12 illustrates, in simplified form, the signal relationships which are most significant in describing the analog to digital conversion of the weight indications. The vertical axis represent amplitudes which are not drawn to scale in order that the principles of operation may be more clearly illustrated. The horizontal axis represents time.

The top most graph 12A depicts the computer interrogation and counting cycles and in the exemplary embodiment have a 65 microsecond period. These are not drawn to scale because several thousand such cycles would be needed. Each cycle represents the length of time required for the microcomputer to loop through its interrogation and indexing sequence of operations.

Below that is a graph 12B, illustrating in a solid line the output of the integrator 51 and also illustrating with broken lines, portions of alternative outputs from the integrator 51.

Finally, the lowest graph 12C illustrates the output state of the threshold detector 53. Its threshold level is set to correspond to the initial level V.sub.0 at the output of the integrator 51 and its output is high when the output of the integrator is negative and is low when the output of the integrator is positive.

Referring to FIGS. 1 and 12, at time T.sub.0, the microcomputer 54 switches the switching circuit 50 to apply the analog signal, which was derived from the load cell, to the input of the integrator 51. This analog signal continues to be applied and is integrated for the entire time interval T.sub.1. This input causes the output of the integrator to be driven from its initial level V.sub.0 along slope S.sub.1 to level V.sub.1. The magnitude of V.sub.1 -V.sub.0 is a directly proportional function of the amplitude of the analog signal and is also a function of its integration time T.sub.1.

The time interval T.sub.1 is a different but fixed and constant time for each different scale capacity and is controlled by the microcomputer 54 and is obtained by reading permanently stored timing data from the computer memory, loading it into suitable registers and sequentially setting the registers in accordance with selected timing loop instructions.

One unique feature of the present invention is that this first integrating interval T.sub.1, during which the analog signal is integrated, is different for each scale capacity and therefore different data is stored in memory and loaded into the time delay registers for each scale capacity.

A particular T.sub.1 time is chosen for each scale capacity so that whatever scale capacity is selected, a full scale weight on the platter for that scale capacity will always drive the integrator output to substantially the same level. Assume for example, that the above described integration along integrator output slope S.sub.1 represents a 20 pound weight on the platter 12 with a 30 pound scale capacity selected, then a 30 pound weight on the platter 12 would integrate along slope S.sub.B to arrive at V.sub.MAX at the time T.sub.1A after time interval T.sub.1. If, for example, a 15 kg scale capacity were then selected, a shorter analog signal integrating the time would be provided by the microcomputer 54 so that a 15 kg weight on the scale platter would drive the integrator output along the slope S.sub.C to reach V.sub.MAX at a time T.sub.1B.

In order to change from pounds to kilograms in accordance with this invention by means of a single switch, which in the exemplary embodiment is readily accessable and may be operated at any time either before or during a weighing operation, the T.sub.1 times for the two different units must be accurately controlled and determined so that the ratio of these times correspond to the conversion factors for changing weights from pounds to kilograms or from kilograms to pounds. Thus, in the exemplary embodiment of the invention described herein the T.sub.1 times are as follows:

At time T.sub.1A, which is the end of the first integrating time interval T.sub.1, the microcomputer 54 switches the switching circuit 50 to begin the second integrating time interval T.sub.2 by applying a first reference DC source I.sub.1 to the output of the integrator 51. This first reference DC source I.sub.1 is then integrated to drive the integrator output level, which represents the sum of the integral obtained during T.sub.1 and the integral being performed during T.sub.2, along slope S.sub.2 back towards and past the initial integrator output level V.sub.0.

After initiating this second integrating interval T.sub.2, the microcomputer begins periodically interrogating the output of the threshold detector 53 looking for the transition which indicates the crossover of the integrator output level with its initial level V.sub.0.

Each time the microcomputer interrogates the output of the threshold detector 53 and finds that corssover has not occurred, it increments a memory assigned to accumulate such interrogation counts T.sub.2 counts. Each such interrogation and counting cycle or instruction loop requires the identical time to perform which in the exemplary embodiment is 65 microseconds.

Eventually, at a time labelled T.sub.2A in FIG. 12B, the output of the integrator 51 crosses over its initial level V.sub.0 causing the output of the threshold detector to switch from a low state to a high state. This transition may occur anywhere within an interrogation and indexing cycle or the end or beginning of such a cycle. However, because of the digital ambiguity, the microcomputer 54 will not detect this transition until it interrogates the output of the threshold detector 53 at time T.sub.2B.

When the switching of the output of the threshold detector 53 is detected at T.sub.2 B by the microcomputer 54, no more interrogation and indexing cycle counts are accumulated in the memory register. Therefore, the digital count accumulated in the first memory register at time T.sub.2 B represents the sum of the amplitude (V.sub.1 -V.sub.0) plus any overshoot V.sub.2 -V.sub.0 of slope S.sub.2, beyond level V.sub.o.

On occasion, the coincidence of the integrator output with the threshold level V.sub.0 will occur relatively near the end of a counting cycle. The possibility then exists that circuit switching, which occurs at the end of the computer interrogating cycles, may cause transients which might cause erroneous operation. For example, if the crossover occurs just before an interrogation of the output of the threshold detector 53 by the microcomputer 54 so that very little overshoot occurs, then the output level of the integrator will be close to the level V.sub.0. If the next integrating interval T.sub.3 were then begun, a computer clock pulse may cause the threshold detector 53 to switch states prematurely.

A unique feature of the present invention is that these crosstalk problems can be eliminated by providing an extra delay at the end of the T.sub.2 interval after the microcomputer 54 has detected the V.sub.0 crossover. Conveniently, this delay interval, labelled T.sub.2 C, can be made equal to one interrogation cycle and will cause the integrator output to be driven further along S.sub.2 from V.sub.2 and V.sub.3. However, the count accumulating memory is not incremented so that no count is added to the memory register for that extra cycle.

After delay time T.sub.2 C, the computer 54 switches the switching circuit 50 to apply a second reference DC source I.sub.2 to the integrator 51. This second reference DC source I.sub.2 is substantially less than the first reference DC source I.sub.1 which was integrated during interval T.sub.2 because it is desired to integrate at a reduced slope S.sub.2 in order to obtain more precisely the time of the coincidence of the integrator output with its initial level V.sub.0. In the exemplary embodiment of the invention, the reference source which is integrated during the T.sub.2 interval is 32 times greater than the reference source which is integrated during the T.sub.3 interval. Therefore, the magnitude of the slope S.sub.2 of the integrator output during interval T.sub.2 is 32 times greater than the magnitude of the slope S.sub.3 during interval T.sub.3.

Upon the beginning of interval T.sub.3, the microcomputer 54 again goes through interrogating and counting cycles just as it did during interval T.sub.2. However, during interval T.sub.3, the interrogating and counting cycles are counted by incrementing a memory register referred to as the T.sub.3 counter or T.sub.3 register. Then, as during interval T.sub.2, counts continue to be accumulated in the second memory register until the first interrogation of the threshold detector 53 by the computer 54 which occurs after coincidence of the integrator output with the threshold level V.sub.0. When the computer detects the resultant output level change of the threshold detector 53 at time T.sub.4, and T.sub.3 integrating interval and the count accumulation is stopped by the microcomputer 54.

At time T.sub.4, the count accumulated in the second register during interval T.sub.3, is directly proportional to and represents the difference between the integrator output level V.sub.3 at T.sub.3A which is at the beginning of interval T.sub.3 and the integrator output level at T.sub.4 at the end of interval T.sub.3. For computational purposes, the integrator output level at the end of T.sub.3 is assumed to be V.sub.0. Since this is a digital ambiguity within one of the counting cycles for the integration along the lesser slope S.sub.3, it will be apparent from the following discussion that the error is less than one part in 30,000 at full scale capacity in the exemplary embodiment.

Nonetheless, the time T.sub.4, when the microcomputer detects the crossover, there will again be some overshoot past the initial level V.sub.0 if the crossover occurs between periodic interrogations of the output of the threshold detector 53.

In order to remove the affect of this overshoot and accurately reset the integrator precisely to the identical V.sub.0 prior to each integration, the microcomputer 54 switches the switching circuit 50 to effectively connect the integrator output to its input. This negative feedback drives the integrator output to V.sub.0 following T.sub.4 by effectively discharging the capacitor of the integrator 51.

The integration functions of the triple slope A/D conversion are completed with the accumulation in each of two memory registers of the digital count data taken along slopes S.sub.2 and S.sub.3. The microcomputer must now take this data and derive a digital number which is proportional to V.sub.1 -V.sub.0 and which therefore is proportional to the amplitude of the analog input signal which was integrated during time interval T.sub.1.

The counts in the T.sub.2 register are proportional to V.sub.1 -V.sub.2. The counts accumulated in the T.sub.3 register are proportional to V.sub.3 -V.sub.0. However, these counts were derived from the integration of two different reference DC sources of substantially different amplitudes. Therefore each T.sub.2 count represents a different and greater quantity of integrator output amplitude and thus a greater weight increment than is represented by each T.sub.3 count. In the exemplary embodiment, the first reference DC source I.sub.1 is 32 times greater than the second reference DC source I.sub.2 and therefore each T.sub.2 count represents 32 times as much amplitude (32 raw weight increments) as does each T.sub.3 count.

In order to equalize the value of each count in the T.sub.2 and T.sub.3 counters, the microcomputer 54 first multiplies the T.sub.2 count by the ratio of l.sub.1 /I.sub.2 which in the exemplary embodiment is 32. Thereupon, the result represents the raw weight increments.

By way of example, 600 interrogating and counting cycle counts may have been accumulated in the T.sub.2 register in driving the integrator output from V.sub.1 to V.sub.2 and 45 interrogating and counting cycle counts may have been accumulated in the T.sub.3 counter in driving the integrator output from V.sub.3 to V.sub.0 during interval T.sub.3. Consequently, in accordance with the invention, the microcomputer will multiply 600 by 32 to obtain a product of 19,200 raw weight increments represented by V.sub.1 -V.sub.2.

The microcomputer then processes the T.sub.3 count to convert it from a number representing V.sub.3 -V.sub.0 to a number representing V.sub.2 -V.sub.0. This is done by subtracting from the T.sub.3 count a number of counts representing V.sub.3 -V.sub.2. Since the integration along slope S.sub.2 from V.sub.2 to V.sub.3 required one interrogating and counting cycle during time T.sub.2, that interval T.sub.2C represents the same amplitude as is represented by a number of T.sub.3 counts which is equal to the ratio of the first reference DC source I.sub.1 to the second constant DC source I.sub.2. Consequently, the microcomputer subtracts that ratio I.sub.1 /I.sub.2 from the accumulated T.sub.3 count.

In the above example for the exemplary embodiment, the number 32 is the ratio which is subtracted from the T.sub.3 count of 45 yield a difference of 13 counts. These 13 counts represent 13 raw weight increments represented by V.sub.2 -V.sub.0.

Therefore, the microcomputer can now arithmetically derive the number of raw weight increments represented by V.sub.1 -V.sub.0 by subtracting this difference of T.sub.3 counts which represents V.sub.2 -V.sub.0 from 32 times the number of T.sub.2 counts. In the example, the microcomputer subtracts 13 from 19,200 to yield 19,187 raw weight increments.

This digital number is proportional to the amplitude of the analog weight signal which was integrated during T.sub.1. In the exemplary embodiment this digital represents weight increments which are referred to as raw weight increments herein:

Each weight indication is then filtered by an improved digital filter. Each weight, when obtained, is subtracted from the filtered weight and the difference divided by two. A one is then added or subtracted from the result to make the result approach the last weight and the last weight corrected by the final result.

This digital number of raw weight units is multiplied by the computer at a later time by the computer by a factor, depending upon the scale capacity to obtain the weight in the proper units for display.

The present invention maintains an accurate zero indication when the scale is not operating in the net mode and also maintains an accurate net zero indication in addition by updating the data stored in a tare weight register.

Tare weight data may be entered into a tare memory register by either of two methods. The digits of a tare weight may be keyed in through the keyboard 20 and this is referred to as a keyboard tare. The tare weight data may also be entered into memory by placing an empty container or other tare weight on the platter and depressing the "T" key. This is referred to as manual tare and causes the scale to read the tare weight and store it in the tare memory.

After a tare weight is properly entered by either of these operations, the computing and weighing scale displays the net weight, which is the difference between the weight of an object on the platter and the weight data stored in the tare register. Consequently, an object weighing the same as the tare weight, for example, the same empty container, should cause a zero net weight to be displayed. A lesser weight on the platter will generate the display of a negative weight.

Unfortunately, creep, hysteresis effects and drift may cause an object on the platter to generate slightly different tare weight data at different times. Similar difficulties have been observed in the maintenance of a gross zero indication as described in Loshbough et al, U.S. Pat. No. 3,986,012. In that situation, a separate auto zero register is used to store a correction factor for automatically correcting the gross zero indication. However, it has been discovered that the same auto zero register cannot be used for net zero tracking because whenever the scale reverts from a net mode of operation back to its gross mode, the auto zero register would still contain net zero tracking data and be erroneous for gross auto zero correction purposes.

The invention involves the periodic updating of the tare weight data to track such wander in order to maintain the display of a zero net weight under the conditions for which a zero net weight should be displayed and in order to use the most recently detected and most accurate tare weight data as a reference which is subtracted from total gross weight to compute net weight.

Each time the microcomputer 54 computes a new weight it examines that weight data to determine whether the tare weight data should be modified. If the net weight is found to be exactly zero, then no drift has occurred and no tracking is necessary. Since a zero indication already exists, the microcomputer skips the remaining net zero tracking sequence of operations. However, if the computed net weight is not exactly zero, it is then examined to determine whether it is close enough to a net weight of zero that its departure from zero can be attributed to creep, drift or hysteresis effects rather than to a change in the weight placed on the platter.

This decision, whether the net zero tracking should actually be performed, is made by determining whether the net weight is within a preselected, narrow, weight range or band centered about a net weight indication of zero. Therefore if the computed but non-zero net weight is outside this range, the remainder of the net zero tracking sequence of operations is skipped. However if it is within the range, net zero tracking is performed by modifying the previously stored tare weight data to compensate for the shift or wander of the net zero.

Data representing the preselected range within which net zero tracking is performed is permanently stored in the memory of the microcomputer 54. In the exemplary embodiment of the invention, this range is a predetermined number of increments which represent different weights for each scale capacity so the net zero tracking sequence of operation is done with data which has already been multiplied by a scale conversion factor to represent output increments of weight rather than units of raw weight increments.

For example, in the exemplary embodiment, for the following scale capacities, the net weight must be within the following ranges in order for the tare weight data to be modified to track the net zero:

If the net weight is within the preselected range for the selected scale capacity, then the microcomputer modifies the tare weight register in a direction which will reduce the next computed net weight by one increment of its least significant digit.

This is done by algebraically adding to the tare weight data a one having the same sign as the previously computed net weight.

For example, for the 30 lb.times.0.01 lb capacity, a computed net weight of +00.002 pounds will cause a +1 to be added to the least significant digit of the tare weight data, any carry being appropriately propaged. If the stored tare weight was 00.192 pounds it will become 00.193 pounds. Therefore, the next time a net weight is computed for the identical gross weight data, the net weight will be +00.001 pounds.

If the gross weight data does not change, continued repetition of the above sequence of operations will continue to increment the stored tare weight data ultimately to cause a net weight result of 00.000 pounds. Thus, in the exemplary embodiment 00.00 will be displayed when only the 4 most significant digits are displayed. The repetition of these net weight tracking operations occur approximately five times per second in the exemplary embodiment.

The exemplary embodiment of the invention incorporates and cooperates with many features shown in U.S. Pat. Nos. 3,962,569; 3,962,570; and 3,986,012; and in U.S. application Ser. No. 729,911 and an application of R. C. Loshbough and E. G. Pryor for Digital Scale Ser No. 824,858 filed Aug. 15, 1977 which are incorporated herein.

However, these features are briefly described to the extent which is helpful to enable those skilled in the art to construct an embodiment of the invention and to practice the invention.

The exemplary embodiment comprises a digital weighing and computing scale to determine the weight of merchandise, to compute the total price or value of the merchandise and to display, and optionally to print, the price per unit weight, the weight of the merchandise and the total value or total price of the merchandise.

FIG. 1 is a block diagram of the exemplary embodiment of the invention and was broadly described above. The exemplary embodiment has input and output structures which may be explained in more detail.

The first input device is the load cell 40 linked to a platter 12 upon which merchandise is supported. The load cell 40 provides the analog output signal which is related to the weight of the merchandise.

The second group of inputs comprises operator accessible switches 20 including a "PREPACK on/off" switch 16 for selecting a prepack mode of operation and a keyboard 20 having keys labelled and physically arranged as illustrated in FIG. 1. The "PREPACK on/off" switch is not provided for UK modes of operation when Half Pence pricing is used. While the "PREPACK on/off" switch 16 is not electrically a part of the keyboard, it is conveniently positioned adjacent the keyboard for ease of access by the operator. Similarly, the lb/kg switch 18 is provided and usually located adjacent the keyboard so the operator may readily change from pounds to kg or visa versa.

The third group of inputs comprises a plurality of programmable mode selector switches 22 which are selectively switched at the factory or by a service technician in the field and are inaccessible to the operator. These mode selector switches 22 are labelled as indicated in FIG. 1 and are switched to those operational modes which are appropriate for the weight and currency units, legal standards and requirements and to the merchandising and pricing methods of the particular store in which the weighing and computing scale will be used. In accordance with this invention, the lb/kg switch 18 is provided to enable the operator to change the scale at any time, either before or during a weighing operation, in either pounds or kilograms to kilograms or pounds respectively. Switch element number 3 of switch 2, designated 19 in FIG. 6, is provided to enable condition the scale to convert the unit price and total price or to clear the unit price and total price where the position of the lb/kg switch is changed.

The weighing and computing scale embodying the present invention also has three groups of output devices. The first group consists of two identical sets of three numerical display devices 24. One set is mounted so that it is visible to the scale operator and a duplicate set is mounted to be visible to the customer or purchaser of the merchandise.

Each display device contains five, cold cathode, gas discharge display digits with three lower commas, each digit having seven segments to display any number from zero through nine. The three displays of each duplicate set ordinarily display price per unit, net or gross weight and total value.

The second output group comprises a pair of duplicate front and back indicator lamp displays, one facing the operator and one facing the purchasing customer. Each indicator lamp display has six translucent windows upon which labels are printed and which are at times backlighted by suitable lamps for making the labels visible. As illustrated in FIG. 1, the labels include "ZERO", "NET", "PREPACK", "1/4", "1/2", and a sixth legend which is alternatively labelled at the factory either "LB" or "KG".

The third output is a printer 28 which is optional.

The "Z" key 17 is operated to zero or null the scale. After power is first applied to the weighing and computing scale embodying the present invention or after a power interruption, no unit price data or tare weight data will be accepted and no total price or value will be displayed until the exemplary embodiment has been so zeroed. The scale may also be zeroed at other times using the "Z" key.

The scale is zeroed in response to depression of the "Z" key 17 when no substantial weight is on the scale by loading the presently detected weight into a memory register for subsequent use as a correction factor. In subsequent weight measurements this correction factor is subtracted from the detected weight to provide a corrected weight. Consequently a zero weight indication will be displayed when there is no weight on the scale.

In order for the exemplary embodiment to perform the zero operation in response to depression of "Z" pushbutton 17, all of the following four conditions must exist. These interlocks prevent the customer from being defrauded by intentional or accidental creation of an erroneous zero. First the "Z" pushbutton 17 must be depressed continuously for at least 1.5 seconds. Second, the platform of the scale must have been motionless for a predetermined interval of time. Third, there must be no tare weight data stored in the memory registers of the exemplary embodiment. Fourth, there must be no significant weight on the platter.

Shortly after the exemplary embodiment has been zeroed in this manner the lamp behind the "ZERO" legend of the indicator lamp display 26 will be illuninated.

The keyboard 20 is a 4.times.5 matrix in which 15 of its key positions are used. The 10 keys labelled "0" through "9" are used to key in price per unit information and, under conditions subsequently described, may be used to key in a tare weight.

Tare weight data may be entered into memory registers in one of two ways. First, a known tare weight may be keyed in by using the keys labelled "0" through "9" of the keyboard 20 and then subsequently depressing the "T" key within two seconds after entry of the last tare weight digit. Such a keyboard entry of tare weight data is accepted only if the corresponding mode of operation is selected by the appropriate mode selector switches 22. Second, an ampty container or other object of unknown tare weight may be positioned on the platter 12 and the "T" key then depressed to cause the exemplary embodiment of the invention to automatically store in memory the weight of that object as the tare weight. This is termed a manual tare operation. A tare weight will be accepted and entered into memory only when certain conditions exist which are described in connection with FIGS. 14A-14Z in the detailed description of the operation of the exemplary embodiment.

If an operator discovers that erroneous tare weight data has been entered, the tare data may be cleared by pressing the key with the numeral "0" and then pressing the "T" key within 2 seconds of the operation of the "0" key. However, such a clearing of the tare data will only be accepted and the tare data will be cleared only if the net weight on the scale is less than 10 scale increments. This prevents the defrauding of a customer by the erroneous clearing or changing of the tare data while an object is on the platter.

After the entry and acceptance of tare weight data, the "NET" legends of the indicator lamp displays will be backlighted to signify that the exemplary embodiment is in a net mode of operation and therefore that its displayed data is a net weight.

If tare weight data has been entered by a manual tare, then the removal of the container will cause the exemplary embodiment to display the tare weight preceded by a negative sign.

The ten digit keys 0 through 9 are used to enter the price per unit weight either after tare data has been entered into memory or, under no tare conditions, by keying in the price per unit and failing to depress the "T" key.

The fraction keys 21 and 23 bear, respectively, the legends "1/2" and "1/4". These fraction keys are depressed to input the information that the pricing is per 1/2 unit or 1/4 unit of weight. Depression of a fraction key 21 or 23 at the appropriate time will cause the corresponding fractional legend on the indicator lamp displays 26 to be illuminated.

The "CLEAR" key of the keyboard 20 may perform two different functions. First, any price data which has been entered may be cleared by depressing the "CLEAR" key. Second, when the "CLEAR" key is pressed and held in a depressed position, all output displays will be blanked or held off. If the pushbutton is released and subsequently again held in a depressed state, all display segments and all display indicating lamps will be turned on.

These two modes permit the displays to be checked to make certain that there are no short circuits which are erroneously turning on display segments and no open circuits which are preventing display segments from being turned on.

When the weighing and computing scale embodying the present invention is used with a printer 28, the operator may depress the "PRINT" key to initiate the printing of an appropriate label bearing the price per unit, the total weight and the total value.

The manually programmable mode selector switches 22 comprise a plurality of individually operable, single pole, single throw switches. Their functions are enabled, that is their labelled conditions exist, when the switches are on or made.

The exemplary embodiment of the present invention has three selectable scale capacities, these are: 15.00 kg.times.0.005 kg., 30.00 lbs..times.0.01 lbs. and 6.000 kg.times.0.002 kg.

The circuitry of the weighing and computing scale illustrated in FIG. 1 is shown in detail in the schematic diagrams of FIGS. 3 through 11. FIG. 2 shows how FIGS. 3 through 8 are associated to illustrate the complete circuit. The random access memory assignments are illustrated in FIG. 13 and are discussed in connection with the subsequent description of the detailed operation of the exemplary embodiment.

FIG. 3 illustrates a load cell 40 which is mechanically linked to the platter 12 and includes four resistive strain gage elements which are connected in a Wheatstone bridge arrangement 70. Typical scale mechanisms suitable for cooperating in the embodiment of the invention described herein are shown in U.S. Pat. No. 3,847,238 granted to D. L. Hall, et al, on Nov. 12, 1974 and U.S. Pat. No. 3,074,496 granted to L. S. Williams on Jan. 22, 1963.

Electrical power from the regulated power supply 42 is applied across one pair of opposite terminals of the bridge 70. The other pair of opposite terminals of the strain gage bridge 70 forms the output of the strain gage bridge and is connected to the input of the preamplifier 44. With no strain, the bridge 70 would be balanced and the output would be zero volts. In this state each output terminal of the strain gage bridge is at the same potential intermediate the potentials of the terminals of the regulated power source 42. However, in practical application, the strain gage bridge 70 will be under the stress of the platter and other mechanical linkages.

Any weight positioned on the platter 12 will further deform the resistive element of the bridge 70 causing a variation in their resistance and unbalancing of the bridge. In this manner, an output analog voltage is obtained from the strain gage bridge 70 which is related to the weight of the object on the platter 12 and is applied and amplified by the preamplifier 44.

The preamplifier 44 has two differential operational amplifiers 72 and 74 which are connected for form a differential amplifier presenting a very high input inpedence to the output of the strain gage bridge 70 so that there is substantially no current drain from the bridge 70 while still providing a preamplifier which is a true differential amplifier rejecting all common mode voltages such as drift or changes in the bridge excitation voltage.

The non-inverting input of the OP-AMP 72 is connected to one of the output terminals of the strain gage bridge 70. The other output terminal of the bridge 70 is connected to the non-inverting input of OP-AMP 74. The OP-AMP 74 provides a substantially unity gain amplifier with its output fed across to the inverting input of the OP-AMP 72. In addition, the inverting input of the OP-AMP 74 is connected to the wiper of a potentiometer 76 which is used to shift the output level of OP-AMP 72. The potentiometer 76 is manually adjusted to compensate for small differences in the mechanical and electrical parameters of production parts and circuits to provide a total effective analog signal component resulting primarily from loading of the strain gages 70 when the platter has no object placed thereon. This known analog signal component or analog offset is subsequently removed by a subtraction in the digital data processing circuitry.

Referring now to FIG. 4, the output 80 of the preamplifier 44 provides a voltage having an amplitude proportional to the sum of the analog offset and the signal change resulting from an object being placed on the platter 12 and is applied to an active filter circuit 46. This active filter circuit 46 is a low pass filter designed to filter out scale platform or platter vibration. The output circuit of the active filter 46 includes a span adjustment potentiometer 92 which is connected as a simple voltage divider for adjustably selecting the desired proportion of the filtered analog weight voltage to be applied through the switching circuit 50 to the integrator 52 at the appropriate time. This potentiometer adjusts the analog circuit gain to a value suitable for the various scale capacities.

The switching circuit 50 under the control of the microcomputer 54 (see FIG. 1) may be used to selectively gate one of four possible inputs through four field effect transistors to the input 98 of the integrator 51. The four alternatively selectable inputs are: (1) the analog weight signal from the wiper of the potentiometer 92 which is applied through a resistor 85 and FET 94; (2) a reference DC source applied through resistor 87 and FET 95; (3) a second reference DC source which is applied through resistor 91 and FET 96; and (4) a reset signal applied through resistor 93 and FET 97. In the exemplary embodiment, resistors 85, 87, and 91 are all 500 K ohms.

The gates of four FETS 94, 95, 96, and 97 are connected to four discrete input/output terminals, 1, 42, 41, and 40 of the CPU as illustrated in FIGS. 5 and 9 so that the CPU can control these gates.

As previously described in the exemplary embodiment, the amplitude of the first reference DC source, which is integrated during the second integration interval T.sub.2 of the triple slope A/D conversion, is 32 times greater than the second reference DC source which is integrated during the third integration time interval T.sub.3.

This is accomplished in the exemplary embodiment by referencing the input to the integrator 51 to a particular non-zero potential rather than to ground. In particular, series resistors R and R/32 shown in FIG. 4 form a voltage divider between the power supply potential of -15 volts and ground. Resistor R is 32 K ohms and resistor R/32 is 1 K ohm. Therefore, the reference potential which is always applied to the non-inverting input of OP-AMP 99 of the integrator 51 has an amplitude equal to 1/33 of the power supply potential and has the same polarity. In the exemplary embodiment this reference potential fixed is at -15/33 volts relative to ground potential by resistors R and R/32.

During the first integrating interval T.sub.1 of the triple slope conversion, a positive analog weight signal is normally applied to the integrator 51. Then, during the second interval T.sub.2, the -15 volt power supply provides the first reference DC source having a polarity opposite to the polarity of the analog weight signal and having an amplitude of -32/33.times.15 volts relative to the reference potential at the noninverting input of the OP-AMP 99.

During the third integrating interval T.sub.3, FET 96 is switched on to apply a second reference DC source to the integrator which is derived through resistor 91 from ground potential. Since ground potential is positive with respect to the reference voltage at the noninverting input of OP-AMP 99 and has an amplitude of 15/33 volts, the connection of the integrator input 98 to ground through resistor 91 effectively provides a second reference DC source during interval T.sub.3 which is both opposite in polarity to and 1/32 the amplitude of the reference DC source applied during interval T.sub.2.

Except for this manner of referenceing the integrator 51, it is a conventional integrator circuit including an integrating capacitor 100.

The output of the integrator 51 is applied to the amplifier 52 and through it to the threshold detector 53. The amplifier 52 comprises an OP-AMP 104 and is provided to amplify the output of the integrator 51 to make the slope of the output of integrator 51 steeper so that the time of its crossover with its initial level can be more accurately determined.

The threshold detector circuit 53 includes an OP-AMP 106. It is simply a high gain amplifier which is driven from one saturation to the other when its input voltage crosses zero.

FIGS. 5-8 show the details of the input and output devices and circuitry and the digital data processing and control circuitry.

In accordance with the present invention, the microcomputer 54 of FIG. 1 may be any of several suitable types of commercially available microcomputers or other similar control circuitry including wired components of types well known in the computer and electronics arts.

In the exemplary embodiment of the invention the microcomputer 54 is essentially a PPS-4 parallel processing, microcomputer system developed by and using devices manufactured by Rockwell International Corporation. The microcomputer 54 is comprised essentially of a central processing unit or CPU which in the exemplary embodiment described herein is a Rockwell PPS-4/2 unit and a memory unit having both read only memory or ROM for storage of program and fixed constants and also random access memory or RAM for storage of data for use in processing. The preferred memory used with the exemplary embodiment of the invention is a Rockwell P/N A17XX device.

In addition to its connection to the output of the threshold detector 53, the microcomputer 54 is also directly connected to the mode selector switches 22, the printer 28, the "Z" key 17, keys 18 and 19, and the "PREPACK ON/OFF" switch 16. The microcomputer 54 is also connected to the front and back indicator lamp displays 26 through suitable interfacing latching, decoding and driving circuitry 56.

Finally, the microcomputer 54 is also connected to a general purpose keyboard and display interfacing device 58 for interfacing the keyboard 20 and the front and back digit displays 24 with the microcomputer 54. A general purpose keyboard and display interface or GPKD interface 58 is employed which in the exemplary embodiment described herein comprises a device manufactured by Rockwell International Corporation and designated P/N 10788. This unit, under the control of the microcomputer 54, receives and temporarily holds data keyed in on the keyboard 20 for subsequent transmission to the microcomputer 54. The GPKD interface unit 58 also receives data from the microcomputer 54 which it applied through decoder/drive logic 60 the front and back digit displays 24 under control of the microcomputer 54. The Rockwell PPS 4 microcomputer system uses four bit data words, eight bit instruction words and in the exemplary embodiment of the present invention twelve bit address words all of which are parallel transferred within the system.

Referring now to FIGS. 5-8, at the top of FIG. 5 is shown the bus system 201 interconnecting the CPU 210 of FIG. 5, the memory 310 of FIG. 6 and the GPKD 410 of FIG. 7. The bus system 201 includes a twelve line address bus 203 which is connected only to the memory 310 for addressing the RAM and ROM memory. The bus 201 further includes an eight line instruction/data bus 205 which transfers, at different times, either eight bit instruction words or two four bit data words bidirectionally. The bus 201 further includes two clock lines, CLKA and CLKB, a write command line and an input/output enable line W/10 for use during one clock phase time for instructing the RAM memory to write and for use during another clock phase time for disabling the RAM memory and enabling the input/output devices for the performance of an input/output instruction. The bus system also includes a "synchronized power on" CPU output line labelled SPO for use in initializing other devices in the circuit.

The CPU 210, which is shown as a single block in FIG. 5, is illustrated in greater detail in FIG. 9. FIG. 9 is a block diagram available with technical information from Rockwell International, Inc.

The CPU 210 as shown in FIG. 9 has an accumulator 810 which is the basic work register of the CPU. It also has an arithmetic logic unit 811 with a carry register 812 and an X register 813 all connected to the accumulator 810. The CPU 210 further has a data address register 814 and a program address register 815 which may be selectively interconnected with the address bus 203 output pins 27 through 38 through the multiplex driver circuits 816. The CPU 210 has two program address save registers 817 and 818 to provide two levels of subroutine stacking. The Rockwell CPU PPS 4/2 is provided with internal clock 819 when a suitable crystal 820 is connected to its pins 18 and 19. The instruction/data bus 205 is connected to pins 6 through 13 which in turn are connected to multiplex receivers 821 and 822 and the multiplex driver 823. Incoming instructions are decoded by the CPU in its instruction decode logic 824 and two separate flip-flops 825 and 826 are provided for programmer use.

In addition to the bus input/output capabilities, the CPU 210 is provided with 12 discrete input/output pins, four from each of the three registers 827, 828, and 829. These are connected as illustrated to pins 1-5, 23-26, and 40-42.

Referring back to FIG. 5, the discrete input/output register 828 of the CPU as shown in FIG. 9 is connected as shown in FIG. 5 to the four control lines labelled T.sub.1, T.sub.2, T.sub.3, and "Reset" which extend to the switching circuit 50 in order to control the integrations of the triple slope A/D conversion. The crystal 820, shown in FIG. 5, controls the frequency of its internal clock generator which is preferably 0.20 MHZ.

A time delay circuit 222 FIG. 5, is provided for delaying the CPU 210 and in particular its program counter (which must be returned to 0000) after power is first applied or after a brief power interruption or momentary power failure.

As illustrated in FIG. 5, output terminals 23-26 of the CPU 210 also provide four bit data to the printer.

FIG. 6 illustrates, in block form, the memory 310 which is illustrated in greater detail in FIG. 10. Referring to FIG. 10, the memory includes both RAM memory 911 and ROM memory 912. These are connected to the instruction/data or I/D bus 205 through a multiplexer 913 which is connected to pins 10-12 and 15-19. An address decoder 910 is connected to the address bus 203 through pins 14, 20, 21, 23, 24 and 28-34. The memory 310 further has sixteen discrete input/output ports connected at pins 1-8 and 35-42 through receiver buffers 917 to the multiplexer 913.

The read-only memory 912 has a storage capacity of 2k eight bit words, any of which may be addressed over the address bus 203 and its stored eight bit word returned to the CPU over the instruction/data bus 205.

The random access memory 911 has 128 four bit storage registers for storing four bit words. Dependent upon the clock phase and the state of the w/IO line connected from terminal 14 of the CPU to terminal 13 of the memory, the addressed memory register will read its four bit contents out onto the instruction/data bus 205 and will write, if so instructed, a new four bit work from the CPU into the addressed register through the multiplexer 913.

Returning to FIG. 6, the output 102 from the threshold detector 53 illustrated in FIG. 4 is applied to one of the discrete input/output ports at pin 42 of the memory 310.

Eight other discrete input/output ports connected to pins 1-8 of the memory 310 are connected to the twelve manual mode selection switches 22 illustrated in FIG. 6. Half of the twelve switches, labelled SW-1, are connected between pin 2 and through diodes to pins 3-8 of the memory 310. The other half of the twelve switches, labelled SW-2, are connected between pin 1 and pins 3-8. Each of the individual switches of both switches SW-1 and SW-2 are individually and independently actuable and each is labelled with a number which corresponds to the function listed in block 22 on FIG. 1. Consequently, the microcomputer 54 can interrogate the condition of switches SW-1 by strobing pin 2 and examining the data of lines 3-8 and can interrogate switches SW-2 by strobing pin 1 and examining the data of pins 3-8. It is to be understood that any particular one of these switches may be assigned any particular operational mode function.

Printer control signals are applied to the printer from the five discrete input/output memory ports 35-39 of the memory 310 illustrated in FIG. 6. The "print complete" signal when received from the printer is applied to the discrete input/output port 40 of the memory 310.

FIG. 7 includes, in block diagram form, the general purpose keyboard and display interface 410. FIGS. 7 and 8 illustrate the keyboard 20 and display drivers connected thereto.

The GPKD interface 410 used in the exemplary embodiment is a device manufactured by Rockwell International Corporation and given their type number P/N 10788. It is interconnected with the memory 310 and the CPU 210 through the data bus 205 as well as the clock A, clock B, synchronized power on and write/input-output lines of the bus 201.

A block diagram of the circuit of the GPKD interface 410 is illustrated in FIG. 11. Referring to FIG. 11, chip select decode circuit 1012 compares the chip address data applied by the CPU 210 to pins 2,4, and 42 of the GPKD over the instruction/data bus to the data on the chip select straps at pins 1, 3, and 41. If the strapped address is identical to the address on the instruction/data bus, if the instruction/data line connected to pin 6 is true, and if the write/input-output mode has been selected by the CPU so that the CPU has trued the W/IO input pin 5, then the GPKD is selected to execute the command.

The command is applied to the GPKD from the CPU 210 over that half of the instruction/data bus which is connected to pins 36 through 39. The command is decoded by the command decoding logic circuitry 1014. A bit time counter 1016 is provided to divide the clock frequency from the PPS clock and apply its output to a scan counter 1018. The scan counter 1018 provides timing signals for the display register control display bank select 1026, return sampling 1028, key buffer register 1032, and control 1030 and strobe select circuit 1024.

The GPKD of FIG. 11 includes two display registers A and B, which store display data. These display registers store data from the instruction/data bus and, upon command, output the data to their associated displays.

The strobe select circuit 1024, with its eight output pins, 27 through 34, sequentially outputs eight strobe signals to its eight output pins. These outputs may be used to strobe an 8.times.8 keyboard matrix or for multiplexing display characters.

The return sampling circuit 1029 receives data from the strobed keyboard indicating the states of the key matrix return lines from the keyboard. When a key closure is detected at the return sampling circuit 1028, the key buffer register control circuit 1030 and loads the key code for that key into the buffer register 1032. Subsequent key closures which are detected may also be stored in the key buffer registers 1032 until they are called for by and transferred to the CPU on a first in, first out basis.

Returning to FIG. 7, the eight strobe select output pins 27 through 34 are applied four to the display driver 513 of FIG. 8 and four to the display driver 514 of FIG. 8. The outputs of the display drivers 513 and 514 are applied to the anode drive terminals of the front and back displays.

Referring to FIG. 7, since various decimal point locations are required by the various countries, a switch labelled SW-3 consisting of six individually operated single pole, single throw switches is associated with transistors Q3 and Q4 for selectively enabling those digit positions in which decimals may be displayed.

Four of the strobe select lines at pins 27 through 30 of the GPKD 410 are additionally applied to the four input strobe lines of the keyboard matrix of the keyboard 20. The keyboard return lines are connected to pins 19 through 21, 23 and 24 of the return sampling inputs of the GPKD 410. These permit interrogation of the keyboard for key depressions.

The operation of the system can be most conveniently described in conjunction with FIGS. 14A through 14Z of the drawings (FIG. numbers 14Q and 14U are not used for clarity). The flow diagrams of FIGS. 14A through 14Z graphically describe the operation of the scale system utilizing the operating sequence represented by the program listing included herewith as an appendix in combination with the Rockwell PPS-4/2 microcomputer described above. However, it should be appreciated that the operating sequence of the system utilizing this operating sequence may be implemented on other types of commercially available computers in accordance with the above principles described herein.

The present invention, as incorporated in the exemplary embodiment described herein, is arranged to cooperate with many features and operations which are described and claimed in U.S. Pat. Nos. 3,984,667 to Loshbough, number 3,869,005 to Williams, Jr., and U.S. Pat. No. 3,861,479 to Pryor, which patents are specifically incorporated by reference herein; and U.S. patent application Ser. No. 729,911 of Donivan L. Hall and Edward G. Pryor entitled "Digital Scale With Antifraud Features", and the application of R. C. Loshbough and E. G. Pryor Ser. No. 824,858 filed Aug. 15, 1977, which patent applications are also incorporated by reference herein. In order to more clearly set forth the precise invention for which this patent is solicited, in such a manner as to distinguish it from other inventions and from what is old, those operations which are disclosed in the incorporated references will only be generally described, with the primary emphasis being given those operations forming a part of the instant invention.

Many of the operations of the scale system utilizing the operating sequence are performed only partially by single pass through the operating sequence (hereinafter referred to as an operating sequence cycle), so that a plurality of passes or cycles through the operating sequence may be required in order to complete a particular operation. Such operations are clearly disclosed in the incorporated references and will be referred to in the instant disclosure only where necessary to clearly set forth the instant invention. The details of the operations are completely disclosed in the accompanying program listing in the appendix and in the flow diagrams FIGS. 14A through 14Z.

The flow diagrams of FIGS. 14A through 14Z disclose in graphical form an exemplary operating sequence of the scale system, including the operations required for implementing the analog-to-digital conversion and the net zero tracking described herein. The flow diagrams consist of a series of geometrical shapes, each of which corresponds to a particular type of operation. Each rectangular block represents the performance of a function which is generally indicated by the notation found within the rectangular block. Each diamond shaped geometrical figure represents a decision making operation where one of two alternatives is determined. The hexagons represent that a subroutine is performed at that particular point in the operating sequence, with the subroutine being performed indicated by the notation within the hexagon. The oval-shaped geometrical figures represent a branch back operation and are used in conjunction with a subroutine to indicate that the operating sequence continues at that point in the main operating sequence where the subroutine was entered. A rhomboid geometrical figure represents either an input or an output operation. The numbers placed in circles to the top and left of the geometrical figures represent input locations to those particular operations. The numbers in the circles to the right and below the blocks in the flow diagrams represent an output connected to a different location in the flow diagrams indicating a transfer in the operating sequence. The mneumonic designations found in parenthesis adjacent to the circles containing numbers, indicate labels which have been given to a particular group of operations. These mneumonics may be utilized in referring back to the detailed operating sequence disclosed in the appendix by referring to the symbol table found at the end of the appendix. The symbol table found in the appendix lists, in alphabetical order, the mneumonic labels and the corresponding location in the detailed program listing of the operating sequence where the particular operations represented by the mneumonic label may be found. Also a table is included showing the operations represented by the mneumonic labels.

In order to accomplish the operations illustrated in FIGS. 14A-14Z, data is assigned to and stored in various registers or memory cells in the random access memory or RAM 911 as illustrated in FIG. 13.

The memory unit 310 which is shown in FIG. 6 and illustrated in more detail in FIG. 10, includes a random access memory or RAM with a capacity of 128 four-bit words and arranged as shown in FIG. 13. Each of the 128 four-bit words may contain any one of sixteen states. These states can represent numerical values of data or a status or condition.

In FIG. 13, the register addresses are referred to by the hexidecimal equivalents of their binary address. The two most significant hexadecimal digits of the address within the RAM define a particular column or grouping of four bit words and the least significant hexidecimal digit defines a row or particular four bit word within the RAM. The hexadecimal address designations are also used as reference numerals below. The various register or storage spaces in the RAM are shown in FIG. 13. These designations are essentially as shown in FIG. 13 of the above copending application Ser. No. 824,858 except as follows:

A kg flag register is provided at 014; a toggle flag at 015; a price convert enable at 040; a lb/kg switch register at 043; and a lb/kg interlock enable register at 052.

The operation of the exemplary embodiment of the invention is now described with reference to the flow chart diagrams of FIGS. 14A-14Z and 14AA-14DD. The first two digits of the alphanumeric reference numerals for the individual steps of the operation are the Figure numbers on which the particular steps are illustrated. The latter alphanumeric digits refer to the particular step in that Figure. The labels which are shown in parentheses on the drawings are the labels used in the program and therefore provide cross references to the appended program listing.

The power-up sequence is an initialization sequence which is performed when power is first applied to the central processor or there is an interruption of power to the central processor.

During step 14A2, various registers within the computer are cleared to an initial state to provide a known starting state for the operating sequence.

After the main program power-up sequence, the operating sequence then proceeds to the X10 CLEAR sequence beginning at step 14E1 which causes a clearing operation to take place with respect to the tare and auto-zero. The operating sequence then proceeds to the output sequence beginning at 14M19.

The main program then advances through the remaining sequences shown in FIG. 14M and then transfers to the sequences of FIGS. 14N and 14O and through the various sequences of FIGS. 14P through 14P15. These output and printer sequences are analogous to the output sequences such as described in the above identified patents and applications. The main program then advances through the various keyboard sequences or routines beginning at 14P16. If no key is operated, the program transfers to T19 of FIG. 14T and then to A8 assuming no verifying operation.

Upon transfer to block 14A8 via transfer A8, the various control and mode switches are scanned and the various registers in the RAM 911 conditioned or set in accordance with the condition of the various control and mode switches. These various operations are designated in blocks 14A8 through 14A9. These operations, and the operations relating to the scanning and response to the keyboard digit keys, are analogous to the corresponding operations described in the above patents and applications incorporated herein.

The various means and apparatus for performing the functions and improvements in accordance with the exemplary embodiment of the invention comprise the scale mechanism, keys, switches, register and storage spaces together with program sequences or routines in combination with the computer, and the output or display apparatus and the control thereof.

Thus the means for controlling the time the integrator means is connected to the scale means comprises program sequences of blocks 14A20 or 14A22 in combination with the computer.

The means for reading the weight includes the flow diagrams beginning at B8 of FIG. 14B of the drawing.

The switch means to change the weight displayed from pounds to kilograms comprises the LB/KG switch 18 and the read weight routine beginning at B8 of FIG. 14B.

The means to convert the stored tare weight; the means to convert the stored zero correction factor; and the means to convert the stored price per unit weight; comprise the program sequences or routines beginning with the flow charts of FIG. 14AA in continuation with the computer. In addition the various flags, registers, and storage spaces as described below are also employed in the conversions.

After all of the other mode selector switches have been scanned by the computer in accordance with block 14A9, control advances by a transfer AA1 to block 14AA1. In accordance with block 14AA1, the computer determines whether the LB/KG pound kilogram switch 18 is set to LB or pounds. Assuming first that this switch is in the pounds or LB position. As a result of this test, the computer then will transfer control via transfer AA4 to block 14AA3. In accordance with block 14AA3, zero is entered or loaded into the X register and control and advances to block 14AA4. Since it is assumed that the scale is in the 30 pound mode or capacity, the 6KG switch will not be on with the result that a program advances to block 14AA5 where the zero in the X register from block 14AA3 is loaded or transferred to the kilogram flag register space 014 while the previous zero in the kilogram flag register space 014 is transferred to the accumulater. Then in accordance with block 14AA6, the accumulater determines whether or not the previous condition of the KG flag 014 is the same as the present condition of this flag. Under the assumed conditions, both conditions are zero so the previous condition of this flag is equal the new condition with the result that the control now transfers via transfer AA13 to block 14AA12. In accordance with block 14AA12, zero is entered in the accumulater to clear the toggle flag 015. Thereafter, control transfers via transfer AA16 to block 14AA114 which causes the toggle flag 015 to be updated with the zero entered in the accumulater in accordance with block 14AA12. Then in accordance with block 14AA15, the condition of the toggle flag 015 is determined and since this toggle is not set at this time, control then transfers back to the block 14A10 via transfer A10.

Thereafter, the control advances to the other routines and functions of the main program as described herein and in the copending applications referred to above and incorporated herein. On each subsequent cycle of the program, the above operations are performed so long as the pound kilograms switch 18 remains in the 30 pound setting.

If now at some subsequent time, the scale operator or attendant desires to change the scale from a scale operating in the 30 pound capacity to a scale operating in the 15 kilogram capacity, either prior to a weighing operation or during a weighing operation, the operator will change the position of the pound kilogram switch 18 to the kilogram position. As a result, the next time the program is transferred to block 14AA1 via transfer AA1, control will advance from block 14AA1 to block 14AA2 instead of to block 14AA3 via transfer AA4 as described above. As a result, an eight is loaded into the X register in accordance with block 14AA2 and then the control transfers via transfer AA5 to block 14AA4 and six kilogram switch is now on, control then will advance to block 14AA5 where the eight will be loaded into the kilogram flag register 014 and the previously recorded zero on this register will be transferred to the accumulater. As a result, when control advances to block 14AA6, the previous condition of the KG flag and the new position of the KG flag are not equal so that control now advances to block 14AA7.

Assuming now that the pound kilogram interlock switch is not operated so that control will now transfer via transfer AA15 to block 14AA13 where an eight is entered into the accumulater for setting the toggle register flag 015 to eight. Consequently, when control then advances to block 14AA14 an eight is entered in the toggle register space. Then when control advances to block 14AA15, the toggle flag will be set so that control will advance to block 14AA15, which causes the number 2 flip-flop A25 of the central processing unit shown in FIG. 9 to be set in its one state to cause the weight recorded in the auto zero register space 04A through 04F to be converted to kilograms as will be described hereinafter. Next control will advance to block 14AA17 where control transfer to the subroutine beginning in block 14V1, which determines the scale capacity. After this capacity has been determined from the setting of the mode switches and switch 18, control then returns to the block 14AA18 of the routine shown in FIG. 14AA. At this time, the scale capacity will not be 30 pounds, so that the control does not advance to block 14AA19. Instead, control transfers to block 14BB1 via transfer BB1 where the conversion factor 090718 is entered in the ARI register 01A through 01F of FIG. 13.

As described herein and in the copending application, incorporated herein, the T.sub.1 time in the analog to digital convertor is different for different scale capacities and is different for 30 pound capacity and the 15 kilogram capacity. As a result, it is necessary to convert the auto zero factor recorded in the auto zero register 04A through 04F of FIG. 13 from a reading appropriate for pounds to a reading appropriate for kilograms. The appropriate conversion factor is 090718 entered in the ARI register in accordance with block 14BB1, as described above.

From block 14BB1 control advances to block 14BB2 where the address of the auto zero register is obtained and then the control advances to block 14BB3. Since the flip-flop 2 or flag 2 was set in accordance with block 14AA16, control now advances via transfer BB5 to block 14BB5 where the auto zero factor stored in the auto zero register space 04A through 04F is multiplied by the conversion factor 090718 and then in accordance with block 14BB6, the result is rounded off and the auto zero register storage area 04A through 04F is updated with the rounded off result of the converted auto zero factor.

Then control is advanced to block 14BB7 and since the flag 2 or flip-flop 2 is still set, control advances to block 14BB8 where the flip-flop or flag 2 is reset to prepare for the conversion of the tare wight recorded in the tare register space 05A through 05F of FIG. 13. Next, control is advanced to block 14BB9 where control is transferred to the FCPTY routine shown in FIG. 14V. At the end of this subroutine, control is transferred back to the program, or routines of FIG. 14BB and more particularly to block 14BB10. Since the pound kilogram switch 18 is set in the kilogram state or position, control then transfers via transfer BB13 to block 14BB12 where the conversion factor 453592 is entered in the ARI register space 01A through 01F of FIG. 13. This is the proper conversion factor to convert the unit price in per pound to the unit price per kilogram. From block 14BB12 control then transfers to block 14BB2 where the address of the auto zero register is again entered in the control circuits of the central processing unit and then control advances to block 14BB3.

This time when the control advances to block 14BB3, the number 2 flag or number 2 flip-flop will not be set because it was previously reset in accordance with block 14BB8 as described above. Consequently, control advances to block 14BB4 where the address of the tare register 05A through 05F if substituted for the address of the auto zero register. Then, in accordance with block 14BB5, the tare weight recorded in the tare register is converted by multiplying it by the converting factor 453592 and then the result is rounded off in accordance with block 14BB6 and the tare register space is updated with the resulting converted tare weight. Next, the control advances to block 14BB7 and since the flag 2 or flip-flop 2 is now not set, control transfers via transfer BB15 to block 14BB13.

In accordance with block 14BB13, the price conversion enabling mode switch 19 is checked. If this switch is not operated, then control advances to block 14BB14 where the price register is cleared, the factor flag and digit timer are cleared and the total price is cleared, if the weight is plus, but blank, if the weight is minus. From block 14BB14, control then transfers via transfer A10 back to the main program of FIG. 14A, block 14A10. Thereafter, the control advances through the various routines as the manner described herein and in the copending applications so long as the pound KG switch 18 remains in the kilogram position.

Assume now that the price conversion enabling switch 19 has been operated so that the price conversion is enabled under these conditions when control advances to block 14BB13, control then transfers via transfer BB18 to block BB15 where the temporary scratch pad register spaces 079 through 07F are cleared and the price is moved from the price register 065 through 069 to this temporary scratch pad register. Next, control is again transferred to the routine FCPTY in accordance with block 14BB16 where the capacity of the scale is again determined and after the routine is concluded, control transfers back to block 14BB17. Since the pound kilogram switch is still in its kilogram position, control now transfers via transfer CC10 to block 14CC9 where the conversion factor 220460 is entered in the ARI register 01A through 01F and then control transfers via transfer CC1 to block 14CC1 where the price is multiplied by the conversion factor and then rounded off in accordance with block 14CC2.

Also, in accordance with block 14CC2, the most significant digit of the result of the conversion and rounding off is addressed to determine its location and then, in accordance with block 14CC3, the condition of the five digit price enabling mode switch is checked. If this switch is operated and the five digit price enabled control transfers via transfer CC5 to block 14CC5. If the five digit price enabling switch is not operated, then five digit price is not enabled so that control will advance to block 14CC4 instead of being transferred via transfer CC5. In accordance with block 14CC4, the fourth most significant digit of the result of the price conversion and rounding off operation is addressed. Control then advances to block 14CC5. Thus, when control advances to block 14CC5, either through block 14CC4 or via transfer CC5, the addressed digit is tested to determine whether or not it is zero. If this digit is not zero, control transfers via transfer BB16 to block 14BB14 where the price register is cleared in the factor flag and digit timer cleared and the total price cleared if the weight is plus and blanked if the weight is minus. Thereafter, control again transfers back to the main program via transfer A10 to block 14A10. However, if when the control advances to block 14CC5, the address digit is zero, then control advances to block 14CC6 and the address incremented by one and control advance to block 14CC7. If the address is the top of the result register 005 through 00F, the result is moved to the price register 065 through 069 and control then transfers via transfer A10 back to the main program block 14A10 and the various routines employed to control the scale system. If, however, when control advances to block 14CC7, the resulting address is not the top of the result register 005, then control transfers via transfer CC5 to block 14CC5 and the control advances through blocks 14CC5, 14CC6, and 14CC7 until the incremented addressed digit in accordance with block 14CC6 at the top of the result register is zero so the control then advances from block 14CC7 to block 14CC8 and then to the main program block 14A10 via transfer A10 in the manner described. Thereafter, the various routines are employed to control the system in the manner described so long as the pound kilogram switch remains in its kilogram position. During all of the subsequent cycles of the main program with the pound kilogram switch in its kilogram position, the KG register flag 014 of FIG. 13 will have an eight recorded in it and the eight will be the same as previously recorded so that when the control advances to block 14AA6, the previous flag and the new flag condition will be the same so that the above described conversion routines will not be employed to control the system. Instead, control will advance via transfer AA13 to block 14AA12, block 14AA via transfer AA16 and then block 14AA15 and then via transfer A10 to block 14AA10 of the main program. Thus, the conversion routines described above are employed once after the pound kilogram switch is operated from one position to the other.

When it is desired to again weigh in terms of pounds by the scale system, in accordance with the present invention, it is only necessary to move the pounds kilogram switch 18 to its pounds position. Then when on the next program cycle, control advances to block 14AA1, the pound kilogram switch 18 will be in its pound position with a result that zero is ordered into the X register and then when control advances to about 14AA6, as described above, the previous kilogram flag register 8 will not equate to the new information in this flag register space 014 with the result that the program will advance through the conversion routines described above.

However, when the control advances to block 14AA18, since the pound kilogram switch 18 is in the pound position, control will advance to block 14AA19 where the conversion factor 110230 is entered in the ARI register space 01A through 01F. This conversion factor is the proper conversion factor to change the weight indication in the auto zero register 04A through 04F to a value suitable for operation in pounds mode rather than the kilogram mode.

Again, when control advances to block 14BB10, the pound kilogram switch will be in the pound or 30 pound position with the result that control advances to block 14BB11 where the conversion factor 022046 is entered in the ARI register 01A through 01F. This conversion factor is the proper conversion factor to change the weight stored in the tare register from kilograms to pounds. Again, if the price conversion switch 19 is in the able position, then when the control advances to block 14BB17 and with the pound kilogram switch 18 in the 30 pound position, control will advance to block 14BB18 where the conversion factor is 045359 is entered in the ARI register 01A through 017. This factor is the factor required to change the price entered in the unit price register from price per kilogram to price per pound.

Then later, as described herein and in the copending application, with the price entered in the price register or storage spaces 065 through 069, the total price or value will be computed based upon this price. Thus, upon unit price per pound.

Thus, all that is required to change the scale from operating in a pound mode to a kilogram mode or from a kilogram mode to the pound mode, is to properly position switch 18 by the operator or attendant and the various stored weights will be automatically converted to the desired mode of operation. If the price conversion switch 19 is not operated, price conversion is not enabled so that the price register and total price register will be cleared so that the operator will then have to enter a new unit price in the scale in order for the total price to be computed. On the other hand, if the price conversion switch 19 is operated, the price conversion is enabled so that this unit price will be converted and then the total price computed in accordance with the converted unit price.

At the end of the conversion, operations described above control will be returned to the main program block 14A10 via transfer A10.

In the beginning under the assumed conditions, the digit timer was previously or already zero so when control transfers from block 14A10 to block 14A11 control will transfer via transfer A15 to block 14A15.

Beginning with block 14A15, the read weight sequence of operations is performed in which the analog to digital conversion in accordance with the present invention is accomplished.

At the beginning of the read weight sequence of operations, a find scale capacity subroutine is performed. This subroutine is illustrated on FIG. 14V. It performs the interrogation of RAM registers 043 and 044 to determine what scale capacity is selected and places data in registers in the CPU 210, FIGS. 5 and 9, which is dependent upon which capacity is selected.

Referring to FIG. 14V, at step 14V1, the arithmetic scratch pad register 01A-01F is cleared and flag 1, i.e., flip-flop 825 of the CPU 210 is set to make an initial assumption that the 15 kilogram scale is not selected. Similarly, the carry register 812 of the CPU 210 is set for an initial assumption that the 6 kilogram scale is not selected.

Then, in step 14V2, the 30 lb. enable RAM register 043 is examined to determine whether the 30 pound scale is selected. If it is, operation jumps to step 14V6. However, if it is not, the carry is then reset in step 14V3 to assume that the 6 kilogram scale is selected. Then in step 14V4, the 6 kilogram enable register RAM 044 is examined to determine whether the 6 kilogram scale is selected. If it is, operation jumps to step V6. However, if it is not, the carry register is set and flag 1 is reset to note that the 15 kilogram scale is selected.

Then, at step 14V6, the flag 1 (FF825) and carry register 812 are used to load into the X register 813 of the CPU 210 a 5 if the 15 kilogram scale was selected, a 3 if 30 pound scale is selected and a 6 if the 6 kilogram scale is selected. In step 14V7 there is loaded into the accumulator 810 a 5 if the 15 kilogram scale was selected, a 1 if the 30 pound scale is selected, and a 2 if the 6 kilogram scale is selected. Then, in step 14V8, the address 001A of the arithmetic scratch pad register ARI is loaded in the BL section of the address register 814 and operation returns to the next order in the sequence of operations at which the find scale capacity sequence of operations was called.

Referring now again to FIG. 14A, data returned in this manner is then used in steps 14A16 through 14A22 to set up a timing sequence for providing the time interval during which the analog weight signal is integrated as part of the analog to digital conversion.

In the exemplary embodiment of the present invention, three, four bit, digital timers are employed; a "Long Timer" in RAM register 00A, a "Mid Timer" in RAM register 009, and a "Short Timer" in the accumulator and initialized to the values shown in blocks 14A17, 14A20, or 14A22. The times are then processed according to the subsequently described timing subroutines in order to provide the desired integrating time interval T.sub.1 illustrated in FIG. 12.

Although a single timer register having sufficient bit capacity could be used to provide the desired time interval, it is advantageous to use the short, mid and long timers described above.

As an example, if the scale has been set or conditioned to operate as 6 kilogram scale, the long timer 00A, is set to a 15 state, the mid-timer 009, is set to its 3 state, and the short timer in the accumulator is set to a 10 state.

After loading this initial timing data into the long, mid and short timers, the CPU 210 at step 14B1 switches the transistor 94 (FIG. 4) of the switching circuit 50 to its conduction state in order to apply the analog weight signal to the integrator circuit 51 and begin the integration.

The delay subroutine at step 14B2 then uses the previously loaded long, mid and short timers to provide the desired time-delay such as T.sub.1. This delay subroutine is illustrated in detail on FIG. 14W.

Referring now to FIG. 14W, upon entry into the delay subroutine at step 14W1, the four bit contents of the midtimer is loaded to register X 813 of the CPU. The four bit contents of the short timer is then loaded at step 14W2 into the accumulator and decremented. The timer is checked at step 14W3 to determine whether it had previously been 0. If it was not 0, then at step 14W4, a 105 microsecond delay is obtained by causing the CPU 210 to perform routine or series of instructions causing the CPU to count cycles for the purpose of obtaining the delay. Thereafter, the sequence of operation loops back again to step 14W2. Operation continues to loop through these 14W2 through 14W4 steps until the short timer is decremented to zero. Thus, it will loop through these steps a number of times equal to the number initially loaded into the short timer.

When a 0 is detected in step 14W3, the operation jumps to step 14W6 in which the mid-timer is loaded into the accumulator and decremented. The contents of the mid-timer is then checked at step 14W7 to determine whether it was a 0. If the mid-timer was not 0, a 1.26 millisecond delay is provided by setting the short timer to a 12 state and looping back to step 14W2. This causes the operations to loop through steps 14W2, 14W3, and 14W4 twelve times until the short timer again is decremented to 0. The 1.26 delay plus the times required by the other orders of the mid delay timer provide a delay of 1.3 milliseconds for each count in the mid delay timer.

Thereupon, steps 14W6, 14W7, and 14W8 will again be performed and the entire procedure repeated until the mid-timer was found to be 0 at step 14W7. Upon finding the mid-timer to be 0 at step 14W7, the operation jumps to step 14W10 which sets up a 14.3 millisecond time delay by loading an 11 state into the mid-timer. This delay plus the time required for the other portions of the long timer routing provide a delay of 15.64 milliseconds for each count of the long timer. The previously set long timer is then loaded into the accumulator at step 14W11 and is decremented. Then, at step 14W12, the timer is checked to determine whether it was previously 0. If the long timer was not previously 0, operation loops back to step 14W8 and then to step 14W2 and repeats the previously described loop until operation arrives again at step 14W12 and finds that the long timer was decremented to zero. In addition to the times determined by the short timer, the mid timer and the long timer, there is an entrance and an exit time, or dead time of 85 microseconds which is included in the selected time delay interval T.sub.1.

As noted above the T.sub.1 time for the 15 KG capacity is 95.950 MS; for the 30 pound capacity 105.770 MS; and for the 6 KG capacity is 239.805 MS. The times are accurately related to the respective scale capacities. When the entire selected time delay such as T.sub.1, during which the analog signal was integrated has expired and operation returns to step 14B3 of FIG. 14B.

Returning to FIG. 14B, at step 14B3, the timing loop counters which are going to be used during the time intervals for integrating the reference DC source are cleared. The discrete outputs of the CPU 210 are disabled and the state of the output 102 of the threshold detector 53 is examined.

If, during the first integrating interval T.sub.1 then (See FIG. 12), the output of the integrator 51 becomes opposite in polarity from the initial level V.sub.0 along a slope such as S.sub.D to a level such as V.sub.3 such output represents a negative raw weight of relatively large magnitude. This might happen if the platter were removed or if an operator lifted up on it. It will immediately cause the output of the threshold detector 53 to switch to its low state. If the comparator is found to be in a low state at step 14B5, then this indicates at step 14B6 that a large negative raw weight was detected and therefore all the discrete outputs of the CPU are enabled and operation jumps to step 14E14 at FIG. 14E and then to step 14M10. This results in skipping of many intermediate operations which check, filter, correct, or otherwise process the raw weight and which would not be meaningful with such negative weight data.

However, if a positive raw weight is found in step 14B5 such as would result from the integration along slope S.sub.1 to V.sub.1, operation proceeds to step 14B8 which stops the integration of the analog signal by switching transistor 94 to a nonconducting state and begins the first reference source integration, such as time interval T.sub.2, by switching the transistor 95 of FIG. 4 to its conducting state.

Steps 14B9 through 14B11 form the interrogation and counting cycle or instruction loop for the integration of the comparator or threshold detector during the T.sub.2 integration time of the first reference DC source. During each instruction loop, the output of the threshold detector 53 is periodically interrogated and a counter is incremented each time the output of the comparator has not occurred changed sign. This counting for both the first and second reference DC source integrating intervals T.sub.2 and T.sub.3 is done in three, four-bit counters, one counter for each of three hexadecimal digits.

While each of these three, four-bit counters could be formed in three, four-bit RAM registers, it is more convenient to form them in the save register 817 forming a part of the CPU 210 illustrated in FIG. 9. The twelve bits of the save register 817 can be considered three, four-bit counters referred to as counter 1, counter 2, and counter 3. This is convenient because the Rockwell PPS-4/2 CPU has an instruction, with the mnemonic CYS, which cycles the save register 817 and the accumulator. This convenient instruction provides a four-bit right shift of the save register 817 with the four-bits which are shifted off the right end of the save register 817 being transferred to the accumulator and with the contents of the accumulator being transferred into the left end of the save register 817.

As shown in steps 14B9-14B11, the counting begins by setting the carry register 812 of the CPU 210 (FIG. 9) to its 1 state. That carry is added to the contents of counter 1 with the results placed in counter 1. Then any carry generated from counter 1 is added to the contents of counter 2 with the result placed in counter 2. Then any carry produced by counter 2 is added to the contents of counter 3 and the result placed in counter 3.

At step 14B10, the output 102 of the threshold detector is then loaded to the accumulator and examined in step 14B12 to determine if it is yet low, that is whether the V.sub.0 level has been crossed. If the comparator is not low, operation then loops back to step 14B9 where it passes again through steps 14B9-14B11. Each pass through this loop requires 65 microseconds using the specific selected CPU instructions. Operation continues to loop through steps 14B9-14B11 until the comparator is found at step 14B11 to have switched to its low state. This indicates that the output of the integrator circuit 51 has crossed its initial voltage level V.sub.0.

An additional 65 microsecond delay is then provided at step 14B12 to extend the second integrating time by the interval T.sub.2C shown on FIG. 12 and described above. Then, at step 14B13, transistor 95 of FIG. 4 is switched to its non-conducting state to halt the integration of the first reference DC source.

The count contained in the three timing loop counters for the second integrating time interval T.sub.2 is then stored in the scratch pad registers 70, 71, and 72 of the RAM memory and the counters (the SA register 817) are cleared for reuse. Then, at step 14B15, the third timing interval T.sub.3 illustrated in FIG. 12 is begun by switching the transistor 96 of FIG. 3 to its conducting state to apply the second reference DC source to the integrator circuit 51.

Then steps 14B16, 14B17, and 14B18 provide an interrogation and counting cycle or loop of steps 14B9-14B11. While the steps of the T.sub.3 counting loop are not identical with the steps of the T.sub.2 loops, they require the same overall time of 65 microseconds. During each pass through this T.sub.3 cycle, the output 102 of the threshold detector 53 is examined to determine whether it has returned to its high state. So long as it has not, operation continues looping through the T.sub.3 interrogating and counting cycle of steps 14B16-14B18. However, whenever in step 14B18 the output 102 has been found to have shifted to its high state, then at step 14B19, the transistor 96 (FIG. 4) is turned off to stop the integration of the second reference DC source and the integrator 51 is reset by switching the transistor 97 to its conducting state.

Then, at step 14B20, the contents of counter 1 and counter 2 of the T.sub.3 counters is stored in RAM memory register spaces 73 and 74. At step 14B21, the scratch pad memories (i.e., register spaces 01A through 01F) illustrated in FIG. 13 are cleared for subsequent use.

Thus, the contents of each of the four-bit registers 70, 71, 72, 73, and 74 now represents a hexadecimal digit of the T.sub.2 and T.sub.3 count which in turn represent the raw weight on the scale. Next these counts are converted to decimal notation and then finally to raw weight increments. This is begun in step 14B22 by multiplying the contents of register 72 (which has stored in it the most significant hexadecimal of the T.sub.2 count) by 256 and moving the result to the weight register 02A through 02F illustrated in FIG. 13. Then, at step 14C1, the weight sign is cleared and the temporary scratch pad is again cleared. The contents of register 71 (which has stored in it the next most significant hexadecimal of the T.sub.2 count), the T.sub.2 counter is multiplied in step 14C2 by 16 and the result moved to the arithmetic scratch pad register illustrated in FIG. 13. Then, at step 14C3, the results of these two multiplications are added together with the result being moved to the weight register. Then, at step 14C4, the least significant hexadecimal digit of the T.sub.2 count is converted to decimal form and added to the sum in the weight register. At 14C5 the resulting total is placed in the weight register and represents the total count during time interval T.sub.2 in decimal digits. The arithmetic scratch pad register is then cleared. While the digits of this decimal number are different from the digits of the hexadecimal number, both numbers represent the same number of counts or cycles obtained during the T.sub.2 interval and each count represents 32 raw weight increments.

The decimal conversion of the T.sub.3 count then begins at step 14C6 by moving the contents of register 74 (which has stored in it the most significant digit of the T.sub.3 count) to the arithmetic register. As stated previously, the reference signal level during time interval T.sub.3 is 1/32 the reference signal level which is integrated during time interval T.sub.2 and therefore each count during time interval T.sub.2 represents 32 times as much analog weight signal (i.e., 32 raw weight increments) as does each T.sub.3 count. In order to eliminate the effect of the additional 65 microsecond delay provided at step 14B12 during time interval T.sub.2, (one additional T.sub.2 count) 32 counts are subtracted from the T.sub.3 count in step 14C6.

Conversion of the T.sub.3 count to decimal form then proceeds at step 14C7 by multiplying the result of the subtraction in step 14C6 by 16 and moving the result to the temporary scratch pad register (FIG. 13). The arithmetic register is also cleared and in step 14C8 the low digit of the T.sub.3 count is moved from register 74 (FIG. 13) to the arithmetic register and converted to decimal form. The result of the multiplication in step 14C7 which is stored in the temporary scratch pad register, and the result of the decimal conversion of step 14C8 which is stored in the arithmetic register, are then added together in step 14C8 to represent the total counts (raw weight increments) during time interval T.sub.3 reduced by 32 counts to compensate for the 65 microsecond delay as described above.

Because each T.sub.2 count represents 32 times as much analog weight signal amplitude as each T.sub.3 count, at step 14C9, the total of the T.sub.2 counts is multiplied by 32 and the result is moved to the weight register. Then, at step 14C10, the T.sub.3 count is subtracted from the T.sub.2 count in order to provide the net number of raw weight increments. This final number of raw weight increments, which is proportional to the sum of the weight on the scale platter and the analog offset, is then moved in step 14C11 to the weight register and is referred to as the raw weight.

Next, the presence or absence of platter motion is first detected and noted, the digital weight data resulting from step 14C11 is then filtered or updated, the appropriate initial analog offset is digitally subtracted and finally the "x10 EXPAND" operations are performed if that mode is selected. These operations are performed in the same manner as described in detail in the above identified copending application included herein by reference. The detection of motion begins at block 14C12 and the above operations extend through blocks 14D17 or 14D19.

Potentiometer 76 is adjusted initially at the factory to provide an analog offset under no weight conditions. However, it is undesirable to change this adjustment when changing from pounds to kilograms or visa versa. Thus this initial offset must be more accurately removed from the detected raw weight data then in the scale described in the above copending applications. This is done in steps 14D6 through 14D14. However, because a different analog signal integrating time interval is used for different scale capacities and the load cell output voltage is interpreted differently for different capacities, a different number must be subtracted from the raw weight for each scale capacity.

Therefore, in step 14D6, the find scale capacity subroutine of FIG. 14V is performed which returns the data described above. The returned data is used to set the arithmetic scratch pad register to 003405 if the 6 kg scale capacity is selected, to 001362 if the 15 kilogram scale capacity is selected, and to 001502 if the 30 pound scale capacity is selected.

After the arithmetic scratch pad register is set to one of these three numbers, which is the analog offset expressed in raw weight increments for the particular scale capacity selected, then in step 14D14, the chosen number of raw weight increments is subtracted from the raw weight and the result is moved to the weight register.

The control advances through the various routines in a manner similar to that described in the above copending applicaions until the control advances to block 14F10, which block defines a portion of the manual tare routine and operation.

Then in block 14F10, the most significant digit of the weight register is examined to see if it contains a zero. If it does not, operation must jump to step 14G1 and the manual tare operation skipped because the most significant weight digit will be used to display a negative sign in the net mode of operation.

If the most significant digit of the weight register is found to be zero, operation transfer to the DD routine shown in FIG. 14DD. Thus, routine is required to insure that if the tare weight is converted as described above in response to the operation of key 18, the converted tare weight will still have a zero for the most significant digit. Thus, the DD routing checks digits of the tare weight to ensure that the next most significant digit is less than a test digit, which test is different for the different scale capacities as indicated in the DD routine. If the tare weight is less than the respective test digits, the operation proceeds to block 14F11 and then to the following routines.

As indicated above for the 30 lb.times.0.01 lb scale capacity, two places are displayed to the right of the decimal point while for the 15 KG.times.0.005 KG and the 6 KG.times.0.002 KG. Thus, to change from the 15 KG capacity to the 30 lb capacity, or from the 30 lb capacity to the 15 KG it is necessary to properly display the weight. In accordance with the exemplary embodiment of the invention described herein, after the weight is rounded off in accordance with block 14I1 control advances to block 14I2. If the capacity is 30 lb control advances to block 14I3 when the weight is shifted one place to the left so the weight will be properly displayed for the 30 lb capacity.

To permit the use of the same routines as employed in the copending application, when it is desired to multiply the weight by the price, the weight is shifted to the right one place for the 30 lb capacity. Thus, after block 14L13 control is transferred to block 14U1 via transfer U1. If the scale is operating as a 30 lb scale control advances to block 14U2 where the weight is shifted one place to the right. Control then returns to block 14L14 and then advances through the various routine similar to the advance described in the above copending applications.

As described above, with reference to manual tare to permit the proper conversion of the stored tare weight in the exemplary embodiment of the invention described herein, the tare weight should not exceed predetermined limits or values for the various scale capacities.

Thus, it is desirable to also check and limit the tare weight is stored in the scale system from the keyboard.

In order to check the magnitude of the tare entered from the keyboard and to prevent the entering of too great a tare weight from the keyboard control transfers from block 14T6 or block 14T8 or 14T10 via transfer U4 or U6 to block 14U3 or 14U4 and then to the other blocks of FIG. 14U and then back to block 14T13 or 14T16 and then to the other blocks as described in the copending application incorporated herein by reference.

The exemplary embodiment of the invention described herein is arranged to cooperate with the scale system disclosed in the above identified copending application incorporated herein by reference. However, the invention is not limited to this exemplary embodiment. Instead it may be arranged to cooperate with other scale system employing the same or different computers including computer arrangements employing various components all wired together.