US 4,179,736 AGrant
Microprogrammed Computer Control Unit Capable of Efficiently Executing a Large Repertoire of Instructions for a High Performance Data Processing Unit
Issue Date:1979-12-18
•41 Claims
•22 Drawing Sheets
Abstract
A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions required to be executed by the data processing unit. The control sequence field is coded to designate which one of a group of hardware control sequences is to be executed by the hardware sequencing circuits for matching the performance of the execution unit and fetching apparatus. The second control store includes a plurality of groups of storage locations, each group for storing the microinstructions required for executing at least a portion of a program instruction. The microprogrammed control unit in response to each instruction op-code reads out signals corresponding to a control sequence field which are decoded to condition the hardware sequencing circuits for performing those operations required for execution of the instruction. The starting location in the second control store is referenced at the end of the designated hardware sequence and instruction execution proceeds under microprogram control.
Metadata
Assignee
- Honeywell Information Systems Inc.
Inventor
- John E. Wilhite
Application Information
Application Number:US 8539464
Filing Date:1977-11-22
Priority Date:1977-11-22
Art Unit:237
Classifications
IPC:
G06F 916
Field of Search:
364200 MS File;900 MS File
Patent Drawings (22 sheets)
Description
RELATED APPLICATIONS
1. "Data Processing System Programmable Pre-Read Capability" invented by John E. Wilhite, William A. Shelly and Charles P. Ryan, Ser. No. 853,944, filed on Nov. 22, 1977 and assigned to the same assignee as named herein.
2. "Hardware Controlled Transfers to Microprogram Control Apparatus and Return via Microinstruction Restart Codes" invented by John E. Wilhite, Ser. No. 853,981, filed on Nov. 22, 1977 and assigned to the same assignee as named herein.
BACKGROUND OF THE INVENTION
Field of Use
The present invention relates to data processing systems and more particularly to microprogrammed data processing systems.
Prior Art
Microprogrammed data processing systems, in order to minimize the size of a control store generally have employed techniques utilized for altering the execution characteristics of program instructions. These techniques involve the utilization of conditional branch microinstructions which test the states of various indicator circuits to select the appropriate sequence of microinstructions required for execution of the operations specified by a particular program instruction. Thus, it is possible to utilize common microinstruction sequences thereby reducing the control store size. Another system utilizes a second control store which stores a pair of addresses for specifying starting and execution microinstruction sequences for maximizing the sharing of microinstruction routines thereby reducing the size of the control store used for storing microinstructions. It also permits the adding of new instructions without requiring logic circuit changes. This system is disclosed in U.S. Pat. No. 4,001,788 which is assigned to the assignee of the present invention.
While the above arrangements provide for considerable flexibility and size advantages, the overall performances of such microprogrammed data processing systems are less than of non-microprogrammed systems. A microprogrammed unit of one system includes a control store and a hardware sequencer network which in response to address or control signals from such store together with condition signals generates additional fixed microoperation commands at higher speeds. This reduces the size of the microprogram normally required to execute a particular program instruction. This system is disclosed in U.S. Pat. No. 3,872,447. While this arrangement increases performance, it operates to extend the number of microcommands which may be obtained from a microinstruction without requiring an extension of the length of the microinstruction. Thus, it requires changes in the hardware sequencer network for different or new instruction requirements. Further, the structure system hardware sequencer network becomes complex where it must provide sequences for a large number of instructions.
Additionally, in the case of high performance pipelined systems, such systems typically perform instructions which are stored in cache units in such a manner that more than one instruction is actually being processed at any given instant of time. Thus, the sequences of operation also can involve cache cycles of operation which makes instruction decoding more complex. This renders the use of the above described arrangement impractical.
Accordingly, it is a primary object of the present invention to provide a microprogrammed control unit arranged to operate in a high performance data processing system.
It is a further object of the present invention to provide a microprogrammed control unit which allows for instruction modification without circuit changes.
It is still a further object of the present invention to provide a microprogrammed control unit which maximizes the sharing of microinstruction execution sequences with increased performance.
SUMMARY OF THE INVENTION
The above and other objects are achieved in a preferred embodiment of the present invention which comprises a cache oriented high performance microprogrammed pipelined data processing unit which includes an execution unit for executing program instructions and apparatus for fetching instructions and data from a cache oriented memory system. The microprogrammed data processing unit includes a decoder circuit, hardware control sequencing circuits and first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions the processing unit is required to execute. The second control store includes a plurality of groups of storage locations, each group for storing sequences of microinstructions required for executing different portions of the operations specified by the program instructions.
In accordance with the preferred embodiment of the present invention, the address field is coded to specify the starting location within the second store of a sequence of microinstructions required to execute the operation specified by the op-code of the instruction. The control sequence field is coded to include less bits than the op-code for designating which one of a group of predetermined hardware control sequences is to be executed by the hardware sequence circuits for an instruction.
During operation, the op code of each instruction is applied as an input to the first control store and accesses the contents of a predetermined one of the locations. Signals corresponding to an address field and a control sequence field are read out. The decoder circuit decodes the bits of the control sequence field and generates signals for conditioning the hardware sequencing circuits to generate control signals for performing a series of operations during a succession of hardware cycles of operations required for execution of the instruction. For each instruction, upon the completion of the hardware sequence, the hardware sequence circuits automatically transfer control to a sequence of microinstructions stored in the second control store at the starting address corresponding to the address signals read out from the first control store for completing the execution of the instruction.
In the preferred embodiment of the present invention, certain classes of sequences are established which permit the kind of performance desired for execution of the entire repertoire of instructions and are selected for each instruction to provide the particular type of performance required for efficient pipeline operation. In more particular terms, for efficient pipeline operation (i.e., processing instructions in sequence), it is important that the performance of the execution unit be matched to that of the instruction fetch apparatus for efficient pipeline processing.
In accordance with the teachings of the invention, a number of the classes of sequences established define the different types of cache/memory operations wherein the classes are selected so as to facilitate the decoding of those instructions requiring cache cycles of operation. For example, the sequences include load single operations, load double operations, store single operations, store double operations and effective address operations. All of the different instructions in the repertoire which require the execution of a given sequence such as a load single are assigned to be included within that class. When certain sequences such as a load single sequence are specified, instruction execution proceeds primarily under the control of the hardware sequence circuits.
In each case, the op-code of each such instruction causes the read out of the contents of a location within the first control store containing control sequence field having the same coded bit pattern. For those instructions specifying operations where the execution unit requires more cycles than those normally required to fetch data or instructions, other ones of the hardware sequences are designated by the coded control sequence fields. These sequences provide the necessary additional cycles to maintain synchronism between the operation of the execution unit and the fetching apparatus.
Additionally, in accordance with the present invention, each instruction is assigned a hardware sequence which enables as much of the instruction to be performed under hardware control before execution of the instruction is permitted to proceed under microprogrammed control. By matching the instructions to such sequences, this maximizes the overall performance of the data processing unit. Moreover, since certain instructions are automatically executed primarily under hardware control, this further increases the processing units performance. This is accomplished with the retaining of flexibility of a microprogrammed unit in that new instructions can be added or changed without requiring corresponding hardware changes.
Additionally, because the arrangement of the present invention provides for a limited number of sequences each normally used by a group of instructions, the decoding of the control sequence fields of instructions requiring no cache cycles such as instructions involved in address development operations is facilitated. Moreover, the complexity of such decoding circuits is considerably reduced while still retaining desired flexibility and performance.
The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying drawings. It is to be expressly understood, however, that each of the drawings is given for the purpose of illustration and description only and are not intended as a definition of the limits of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates in block form a system employing the principles of the present invention.
FIG. 2 shows in block diagram form the host processor 700 and the cache memory 750 of FIG. 1.
FIGS. 3a through 3i show in greater detail the different blocks of FIG. 2.
FIG. 4 shows in greater detail the cache unit 750 of FIG. 2.
FIGS. 5a through 5e show the lines which comprise different ones of the interfaces of FIG. 1.
FIG. 6a illustrates the format of the control store control unit of FIG. 2 in accordance with the teachings of the present invention.
FIG. 6b illustrates the format of the microinstruction words of the execution control store of FIGS. 2 and 3.
FIG. 7 is a state diagram used in describing the hardware sequencing of the apparatus of the present invention.
FIG. 8 is a diagram used in explaining the pipeline operations of the processor 700 in processing different series of instructions in accordance with the present invention.
FIGS. 9a through 9d illustrate the formats of certain types of instructions used in describing the operation of the present invention.
TABLE OF CONTENTS
Description of the Preferred Embodiment
General Description
System Interfaces
Data Interface Lines
Programmable Interface Lines
Interrupt Interface Lines
Local Memory Interface Lines
CP/Cache Interface Lines
General Description of Processor 700--FIG. 2
Detailed Description of the Processor 700
Control Logic Unit 704-1
Hardwired Sequences
I Cycle Control State/Cycle
Register Section 704-150
Address Preparation Unit 704-3
XAQ Register Section 704-5 and Data Address Output Section 704-4 FIGS. 3e and 3f
Execution Unit 714--FIG. 3g
Character Unit 720--FIG. 3h
The Auxiliary Arithmetic and Control Unit (AACU) 722--FIG. 3i
CACHE UNIT 750--FIG. 4
General Description
Command Buffer Section 750-1
Control Section 750-3
Control State Flip-Flops
CONTROL LOGIC SIGNALS
Cache Directory Section 750-5
Cache Storage Section 750-7
Instruction Buffer Section 750-9
DESCRIPTION OF OPERATION
HARDWIRED CONTROL STATE ACTIONS SECTION
ABBREVIATIONS OF TERMS USED IN THE HARDWIRED CONTROL STATE ACTIONS SECTION
System Operation
APPENDIX A
DESCRIPTION OF THE PREFERRED EMBODIMENT
General Description
As seen from FIG. 1, the system which incorporates the principles of the present invention includes at least 1 input/output processor (IOPP) 200, a system interface unit (SIU) 100, a high-speed multiplexer (HSMX) 300, a low-speed multiplexer (LSMX) 400, a host processor 700, a cache memory 750, at least one memory module corresponding to a local memory module 500, and at least one memory module corresponding to a remote memory module 800. Different ones of these modules connect to one of a number of ports of the system interface unit 100 through a plurality of lines of different types of interfaces 600 through 603. More specifically, the input/output processor 200, the cache memory 750, and the high-speed multiplexer 300 connect to ports G, E and A, respectively, while the low-speed multiplexer 400, local memory module 500, and main memory module 800 connect to ports J, LMO and RMO, respectively. The host processor 700 connects to the cache memory 750.
The input/output system of FIG. 1 can be viewed as including a number of "active modules", "passive modules" and "memory modules". The IOP processor 200, host processor 700 and high-speed multiplexer 300 serve as active modules in that each has the ability to issue commands. The active modules normally connect to ports A through H while the host processor 700 connects to port E through the cache unit 750 via interfaces 604 and 600. A plurality of passive modules are connected to three ports J, K and L. These modules correspond to the low-speed multiplexer 400 and the system interface unit 100 and are units capable of intercepting and executing commands applied to the lines of interface 601 as described herein. The last group of modules constitutes local memory modules, and main memory modules capable of executing two different types of commands applied to the lines of interface 603.
The input/output system of FIG. 1 normally functions as an input/output subsystem responsive to input/output instructions issued by the host processor 700. Ports E and F include interfaces for enabling connection of either multiplexer or processor modules of FIG. 1. These interfaces are described in greater detail herein.
For the purpose of the present invention, host processor 700 is conventional in design and may take the form of those units described in U.S. Pat. No. 3,413,613. In the preferred embodiment, the input/output processor 200 initiates and terminates channel programs required for the execution of input/output instructions, processes interrupt requests received from the system interface unit 100, and directly controls unit record peripheral devices coupled to low-speed multiplexer 400. The processor 200 connects to port G via the data interface 600 and interrupt interface 602.
The low-speed multiplexer 400, for the purposes of the present invention can be considered conventional in design, provides for attachment of low-speed peripheral devices via peripheral adapters, each of which couples to the lines of a device adapter interface (DAI). The interface and adapter may take the form of those units described in U.S. Pat. No. 3,742,457, which is assigned to the assignee of the present invention. The low-speed devices include card readers, card punches and printers. As seen from FIG. 1, the multiplexer 400 connects to port J via the programmable interface 601.
The high-speed multiplexer 300 directly controls transfers between the groups of disk devices and tape devices 309 through 312, which connect to different ones of the channel adapters 303 to 306. Each of the channel controller adapters 303 through 306 which can connect up to a maximum of 16 devices to a different one of the channel ports 0 through 3 via the interface lines of a channel adapter interface (CAI) 300-1. The high-speed multiplexer 300 connects to port A corresponding to a data interface 600, a programmable interface 601 and an interrupt interface 602.
For the purposes of the present invention, each of the channel controller adapters 302 through 305 may be considered in design and take the form of controller adapters described in the aforementioned U.S. Pat. No. 3,742,457.
SYSTEM INTERFACES
Before describing in detail the processor 700 and cache unit 750, constructed in accordance with principles of the present invention, each of the interfaces 600 through 604 discussed previously will now be described with reference to FIGS. 5a through 5e.
Referring first to FIG. 5a, it is seen that this figure discloses the lines which constitute the data interface 600 which is one of the interfaces which provides for exchange of information between an active module and the system interface unit 100. Exchange is accomplished by controlling the logical states of various signal lines in accordance with pre-established rules implemented through a sequence of signals termed a "dialog".
As seen from FIG. 5a, the interface includes an active output port request line (AOPR), a plurality of data to SIU lines (DTS 00-DTS 35, P0-P3), a plurality of steering data to SIU lines (SDTS 0-6, P), an active request accepted line (ARA), an accept read data line (ARDA), a plurality of data from SIU bus lines (DFS 00-35, P0-P3), a plurality of multiport identifier from SIU lines (MIFS 0-3, P), a double precision from SIU line (DPFS), and an accept status line (AST). The description of the interface lines are given in greater detail in the section to follow.
The lines of the programmable interface 601 shown in FIG. 5b provide for transfer of command information from an active module and a designated module. The transfer is accomplished by controlling the logic of states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed dialog. The programmable interface includes an accept programmable interface command line (APC), a plurality of programmable interface data from SIU lines (PDFS 00-35, P0-P3), a programmable interface ready line (PIR), a read data transfer request line (RDTR), a plurality of programmable interface data to SIU lines (PDTS 00-35, P0-P3) and a read data accepted line (RDAA). The description of the interface lines are given in greater detail herein.
A further interface is the interrupt interface 602 of FIG. 5c which provides for interrupt processing by the input/output processor 200. That is, the interface enables the transfer of interrupt information by an active module to the SIU 100 as well as the transfer of interrupt information by the SIU 100 to the input/output processor 200 for processing. Similar to the other interfaces, the transfer of interrupt requests is accomplished by controlling the logical states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed "dialog".
The interface includes an interrupt request line (IR), a plurality of interrupt data lines (IDA 00-11, P0-P1) and a plurality of interrupt multiport identifier lines (IMID 00-03) for modules connected to ports A through L. For modules connected to ports G and H, the interrupt interface further includes a level zero present line (LZP), a higher level interrupt present line (HLIP), an interrupt data request line (IDR), a release line (RLS) and a plurality of active interrupt level lines (AIL 0-2). As seen from FIG. 5c, the interrupt interface ports G and H do not include an interrupt multiport identifier line. The description of the interrupt interface lines are given in greater detail herein.
A next set of interface lines utilized by certain ones of the modules of FIG. 1 corresponds to the local memory interface lines of FIG. 5d. The local memory interface 603 provides for exchanging information between local memory 500 and the modules of the system. The exchange is accomplished by controlling logical states of the various signal interface lines in accordance with pre-established rules implemented through a sequence of signals termed a "dialog". The local memory interface includes a plurality of data to memory lines (DTM 00-35, P0-P3), a plurality of request identifier to memory lines (RITM 0-7, P0-P1), a plurality of specification lines to memory lines (SLTM 0-3, P), an accept P1 command line (APC), an accept ZAC command line (AZC) a P1 interface ready line (PIR), a ZAC interface ready line (ZIR), a read data transfer request line (RDTR), a plurality of data from memory lines (DFM 00-35, P0-P3), a plurality of request identifier from memory lines (RIFM 0-7, P0-P1), a double precision from memory lines (DPFM), a QUAD line, a read data accepted line (RDAA) and a system clock line (SYS-CLK).
Memory and programmable interface commands are transferred out of the same physical data lines of the interface. The interface does not include a set of lines for processing interrupt requests and therefore the modules connected to the local memory by the SIU 100 cannot directly cause a memory interrupt. The description of the local memory interface lines are given in greater detail herein.
A last set of interface lines utilized as an internal interface between the cache unit 750 and central processor 700 corresponds to the cache/CPU interface lines of FIG. 5e. The interface 604 provides for exchanging information and control signals between the processor 700 and the cache unit 750. The exchange is accomplished by controlling the logical states of the various signal interface lines. The cache/CPU interface includes a plurality of data to processor lines (ZDI 0-35, P0-P3), a plurality ZAC and write data lines (ZADO 0-23, RADO 24-35, P0-P3) a processor request signal line (DREQ-CAC), a plurality of cache command lines (DMEM 0-3), a hold cache line (HOLD-C-CU), a cancel line (CANCEL-C), a flush line (CAC-FLUSH), a read request line (RD-EVEN), a read instruction buffer line (RD-IBUF), a read data buffer line (DRDB), an initialization pointer line (INIT-IBUF), a plurality of instruction lines (ZIB0-35, P0-P3), a plurality of address pointer lines (ASFA32-33), a control line (DSZ), a read I-buffer data line (RD-IBUF/ZDI), a plurality of zone bit lines (DZD 0-3), a bypass cache line (BYP-CAC), a write signal line (WRT-SGN), an instruction buffer empty line (IBUF-EMPTY), an instruction buffer ready line (IBUF-RDY), an instruction buffer full line (IBUF-FULL); a CP stop line (CP-STOP), and a CP control line (DATA-RECOV).
Instructions, cache commands and data are forwarded to the cache unit 750 via different ones of these lines. Additionally, the operation of the processor 700 is enabled or disabled by certain ones of these lines as explained herein. The description of the CPU/cache interface lines are given in greater detail herein.
While FIGS. 5a through 5e show lines which connect the different modules of the system of FIG. 1 to SIU 100 in addition to the connection to processor 700 and cache unit 750, it will be appreciated that other lines are also included for signalling other conditions, as for example, certain error conditions and operational conditions. For further descriptions of the various modules of FIG. 1, reference may be made to U.S. Pat. No. 4,000,487. Now, the processor module 700 and cache unit 750 will be described in greater detail.
GENERAL DESCRIPTION OF PROCESSOR 700-FIG. 2
Referring to FIG. 2, it is seen that the host processor 700 includes an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit (AACU) 722, a multiply-divide unit 728, which are interconnected as shown. Additionally, the control unit 704 has a number of interconnections to the cache unit 750 as shown.
The execution control unit 701 includes an execution control store address preparation and branch unit 701-1, and an execution control store 701-2. The store 701-2 and unit 701-1 are interconnected via buses 701-3 and 701-6 as shown.
The control unit 704 includes a control logic unit 704-1, a control store 704-2, an address preparation unit 704-3, data and address output circuits 704-4, an XAQ register section 704-5 which interconnect as shown.
As seen from FIG. 2, the SIU interface 600 provides a number of input lines to the cache unit 750. The lines of this interface have been described in detail previously. However, in connection with the operation of cache unit 750, certain ones of these lines are specially coded as follows.
1. MITS 0-3 for Reads are coded as follows:
bits 0-1=00;
bits 2-3=Read ZAC buffer address;
For Write Operation bit 0-3=Odd word zone
2. MIFS lines are coded as follows:
bit 0=0;
bit 1=0 even word pairs (words 0,1);
bit 1=1 odd word pairs (words 2,3);
bits 2-3=ZAC buffer address to memory.
As concerns the interface lines DFS 00-35, P0-P3, these lines convey read data to cache unit 750. The lines DTS 00-35, P0-P3, are used to transfer data from cache 750 to the SIU 100.
The control unit 704 provides the necessary control for performing address preparation operations, instruction fetching/execution operations and the sequential control for various cycles of operation and/or machine states. The control is generated by logic circuits of block 704-1 and by the execution control unit 701 for the various portions of the control unit 704.
The XAQ register section 704-5 includes a number of program visible registers such as index registers, an accumulator register, and quotient register. This section will be discussed in greater detail with reference to FIG. 3. Other program visible registers such as the instruction counter and address registers are included within the address preparation unit 704-3.
As seen from FIG. 2, the section 704-5 receives signals from unit 704-3 representative of the contents of the instruction counter via lines RIC 00-17. Also, lines ZRESA 00-35 apply output signals from the execution unit 714 corresponding to the results of operations performed upon various operands. The section 704-5 also receives an output signal from the auxiliary arithmetic and control unit via lines RAAU0-8.
The section 704-5 provides signals representative of the contents of one of the registers included within the section as an input to the address preparation unit 704-3. The address preparation unit 704-3 forwards the information through a switch to the execution unit 714 via the lines ZDO 0-35. Similarly, the contents of certain ones of the registers contained within section 704-5 can be transferred to the execution unit 714 via the lines ZEB 00-35. Lastly, the contents of selected ones of these registers can be transferred from section 704-5 to the multiply/divide unit 728 via the lines ZAQ 00-35.
The address preparation unit 704-3 generates addresses from the contents of various registers contained therein and applies the resultant logical, effective and/or absolute addresses for distribution to other units along the lines ASFA 00-35. The address preparation unit 704-3 receives the results of operations performed on a pair of operands by the execution unit 714 via the lines ZRESB 00-35. The unit 704-3 receives signals representative of the contents of a pair of base pointer registers from the control logic unit 701 via the lines RBASA and RBASB0-1. Outputs from the multiply/divide unit 728 are applied to the address preparation unit 704-3. Lastly, the contents of a secondary instruction register (RSIR) are applied as input to the unit 704-13 via the lines RSIR 00-35.
The data and address output circuits 704-4 generate the cache memory address signals which it applies to the cache unit 750 via the lines RAD0/ZAD0 00-35. These address signals correspond to the signals applied to one of the sets of input lines ZDI 00-35, ASFA 00-35 and ZRESB 00-35 selected by switches included within the circuits of block 704-4. Also, word address signals are applied via the lines ASFA 32-33. These circuits will be further discussed herein in greater detail.
The control logic unit 704-1 provides data paths which have an interface with various units included within the cache unit 750. As described in greater detail herein, the lines ZIB 00-35 provide an interface with an instruction buffer included within the cache 750. The lines ZDI 00-35 are used to transfer data signals from the cache 750 to the control logic unit 704-1. Other signals are applied via the other data and control lines of the cache-CP interface 604. These lines include the CP stop line shown separately in FIG. 2.
As seen from FIG. 2, the control logic unit 704-1 provides a number of groups of output signals. These output signals include the contents of certain registers, as for example, a basic instruction register (RBIR) whose contents are applied as an input to control store 704-2 via the lines RBIR 18-27. The control logic unit 704-1 receives certain control signals read out from control store 704-2 via the lines CCSD0 13-31.
The control logic unit 704-1 also includes a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of processing an instruction. The contents of the secondary instruction register RSIR 00-35, as previously mentioned, are applied as inputs to the address preparation unit 704-3. Additionally, a portion of the contents of the secondary instruction register are applied as inputs to the auxiliary arithmetic control unit 722 via the lines RSIR 1-9 and 24-35.
The control store 704-2 as explained herein provides for an initial decoding of program instruction op-codes and therefore is arranged to include a number of storage locations (1024), one for each possible instruction op-code.
As mentioned, signals applied to lines RBIR 18-27 are applied as inputs to control store 704-2. These signals select one of the possible 1024 storage locations. The contents of the selected storage location are applied to the lines CCSD0 13-31 and to CCSD0 00-12, as shown in FIG. 2. The signals supplied to lines CCSD0 00-12 correspond to address signals which are used to address the execution control unit 701 as explained herein.
The remaining sections of processor 700 will now be briefly described. The execution unit 714 provides for instruction execution wherein unit 714 performs arithmetic and/or shift operations upon operands selected from the various inputs. The results of such operations are applied to selected outputs. The execution unit 714 receives data from a data input bus which corresponds to lines RDI 00-35 which have as their source the control logic unit 704-1. The contents of the accumulator and quotient registers included within section 704-5 are applied to the execution unit 714 via the lines ZEB 00-35 as mentioned previously. The signals applied to the input bus lines ZDO 00-35 from the address preparation unit 704-3 are applied via switches included within the execution unit 714 as output signals to the lines ZRESA 00-35 and ZRESB 00-35, as shown in FIG. 2. Additionally, execution unit 714 receives a set of scratch pad address signals from the auxiliary arithmetic and control unit 722 applied via the lines ZRSPA 00-06. Additionally, the unit 722 also provides shift information to the unit 714 via the lines ZRSC 00-05.
The character unit 720 is used to execute character type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructions are referred to as extended instruction set (EIS) instructions. Such instructions which the character unit 720 executes include the move, scan, compare type instructions. Signals representative of operands are applied via lines ZRESA 00-35. Information as to the type of character position within a word and the number of bits is applied to the character unit 720 via the input lines ZDB 00-07.
Information representative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes exponent data and data in hexadecimal form. The character unit 720 applies output operand data and control information to the unit 722 and the unit 728 via the lines RCHU 00-35.
The auxiliary arithmetic and control unit 722 performs arithmetic operations upon control information such as exponents used in floating point operations, calculates operand lengths and pointers and generates count information. The results of these operations are applied to execution unit 714 via the lines ZRSPA 00-06 and lines ZRSC 00-06 as mentioned previously. Information signals corresponding to characters such as 9-bit characters, 6-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are applied to section 704-5 via the lines RAAU 00-08.
As seen from FIG. 2, the unit 722 receives a number of inputs. Character pointer information is applied via the lines ASFA 33-36. EIS numeric scale factor information and alphanumeric field length information are applied to the unit 722 via the lines RSIR 24-35. Other signals relating to fetching of specific instructions are applied via the lines RSIR 01-09. Exponent signals for floating point data are applied to the unit 722 via the lines ZOC 00-08 while floating point exponent data signals from unit 704-1 are applied via the lines RDI 00-08. Shift count information signals for certain instructions (e.g. binary shift instructions) are applied to the unit via the lines RDI 11-17. As concerns the input signals applied to the lines RCHU 00-35, lines 24-35 apply signals corresponding to the length of EIS instruction fields while 18-23 apply address modification signals to the unit 722.
The last unit is the multiply/divide unit 728 which provides for high-speed execution of multiply and divide instructions. This unit may be considered conventional in design and may take the form of the multiply unit described in U.S. Pat. No. 4,041,292 which is assigned to the same assignee as named herein. The unit 728 as seen from FIG. 2 receives multiplier dividend and divisor input signals via the lines RCHU 00-35. The multiplicand input signals from register section 704-5 are applied via the lines ZAQ 00-35. The results of the calculations performed by the unit 728 are applied as output signals to the lines ZMD 00-35.
As mentioned previously, the cache unit 750 transfers and receives data and control signals to and from the SIU 100 via the data interface line 600. The cache unit 750 transfers and receives data and control signals to and from the processor 700 via the lines of interface 604. Lastly, the cache unit 750 receives address and data signals from the circuits 704-4 via the lines RAD0/ZAD0 00-35 and the lines ASFA 32-33.
DETAILED DESCRIPTION OF THE PROCESSOR 700
The various sections which comprise the processor 700 illustrated in FIG. 2 will now be discussed in greater detail with respect to FIGS. 3a through 3i.
Referring to FIGS. 3a and 3b, it is seen that the processor includes two control stores: (1) the control unit control store (CCS) 704-200 which forms part of the control unit 704; and (2) the execution control store (ECS) 701-3 which is included within the execution conrol unit 701.
The cache oriented processor 700 of the preferred embodiment of the present invention includes a three stage pipeline. This means that the processor 700 requires at least three processor cycles to complete the processing of a given program instruction and can issue a new instruction at the beginning of each cycle. Hence, a number of program instructions may be in some stage of processing at any given instant of time.
In the preferred embodiment of the processor 700 includes the following stages: an instruction cycle (I) wherein instruction interpretation, op-code decoding and address preparation take place; a cache cycle (C) wherein access to the cache unit 750 is made ensuring high performance operation; and, an execution cycle (E) wherein instruction execution takes place under microprogram control.
As concerns control, during the I cycle, the op-code of the instruction applied via lines RBIR 18-27 is used to access a location within control store 704-2. During a C cycle, the accessed contents from control store 704-2 are applied to lines CCS D0 00-12 and in turn used to access one of the storage locations of the execution control store 701-2. During the C cycle, the microinstructions of the microprogram used to execute the instruction are read out from the execution control store 701-2 into a 144-bit output register 701-4. The signals designated MEMD0 00-143 are distributed to the various functional units of processor 700. During an E cycle, the processor executes the operation specified by the microinstructions.
Referring specifically to FIG. 2, it is seen that the control store 704-2 includes a control unit control store (CCS) 704-200 which is addressed by the op-code signals applied to the lines RBIR 18-27. The CCS 704-200, as mentioned previously, includes 1024 storage locations, the contents of which are read out into an output register 704-202 during an I cycle of operation. FIG. 6a shows schematically the format of the words stored within the control store 704-200.
Referring to FIG. 6a, it is seen that each control unit control store word includes five fields. The first field is a 13-bit field which contains an ECS starting address location for the instruction having an op-code applied to lines RBIR 18-27. The next field is a three bit field (CCS.phi.) which provides for the control of certain operations. The bit interpretations of this field depend upon its destination and whether it is decoded by specific logic circuits or decoded under microprogram control. The next field is a 4-bit field which provides for certain register control operations.
The next field is a 6-bit sequence control field which is coded to specify a sequence of operations to be performed under hardwired logic circuit control as well as the type of cache operation. In the present example, this field is coded as 75.sub.8. The last field is a 6-bit indicator field which is not pertinent to an understanding of the present invention.
As seen from FIG. 3a, signals corresponding to the CCSA field of a control unit control store word are applied via a path 704-204 as an input to the execution generation circuits 701-7. Signals corresponding to the CCSR field are applied as an input to the execution unit 714 via path 704-206. Additionally, the same signals are applied as an input to the address preparation unit 704-3 via another path 704-208.
Signals representative of the sequence control field apply as an input to the sequence control logic circuits 704-100 via path 704-210. As explained herein, these circuits decode the sequence control field and generate signals for conditioning the cache unit 750 to perform the operation designated.
As mentioned previously, the execution address generation circuit 701-1 receives an input address which corresponds to field CCSA from the control store 704-2. As seen from FIG. 3b, these circuits include an input address register 701-10 whose output is connected to one position of a four position switch 701-12 designated ZECSA. The output of the switch serves as an address source for the control store 701-2. The first position of the switch 701-12 is connected to receive an address from the MICA register 701-14. The contents of register 701-14 are updated at the end of each cycle to point to the location within the ECS control store following the location whose contents were read out during that cycle.
The second position selects the address produced from the ZCSBRA branch address selector switch 701-18. The third position selects the address of the first microinstruction in each microprogram provided by the CCS control store which is loaded into the REXA register 701-10. When the CCS output is not available at the termination of a microprogram, a predetermined address (octal address 14) is automatically selected.
The first position of branch switch 701-18 receives signals corresponding to a branch address read out from store 701-2 into register 701-4 which is in turn forwarded to a return control register 701-20. The second, third and fourth positions of switch 701-18 receives signals from RSCR register 701-20, an MIC register 701-15 and the contents of a number of vector branch registers 701-36. The MIC register 701-15 stores an address which points to the microinstruction word following the microinstruction word being executed. This address corresponds to address from switch 701-12 incremented by one by an increment circuit 701-12.
The vector branch registers include a 4-bit vector branch register 0 (RVB0), a 2-bit vector branch register 1 (RVB1) and a 2-bit vector branch register 2 (RVB2). These registers are loaded during a cycle of operation with address values derived from signals stored in a number of different indicator flip-flops and registers applied as inputs to the number of groups of input multiplexer selector circuits 701-32 and 701-34. The outputs of the circuits 701-32 and 701-34 are applied as inputs to two position selector circuits 701-30. These circuits in turn generate the output signals ZVBR0, ZVBR1 and ZVBR2 which are stored in the registers 701-36.
The switch 701-36 provides an address based upon the testing of various hardware indicator signals, state flip-flop signals selected via an INDGRP field. The branch decision is determined by masking (ANDING) the selected indicator set with the INDMSKU and INDMSKL fields of a microinstruction word. If a vector branch is selected, INDMSKU is treated as 4 ZERO bits. The "OR" of the 8 bits is compared to the state defined by the TYPG and GO microinstruction fields. The hardware signals are applied via a number of data selector circuits 701-28 only one of which is shown whose outputs are in turn applied as inputs to a further five position multiplexer selector circuit 701-26. The output of the multiplexer circuit 701-26 feeds a comparison circuit which "ands" the indicator signals with the mask signals to produce the resulting signals MSKCBR0-7.
The signals MSKBR0-7 are applied to another comparison circuit which "ands" the signals with the condition branch test signals TYPGGO to set or reset a branch decision flip-flop 701-22 which produces a signal RBDGO whose state indicates whether branching is to take place. The output signal RBDGO is applied as a control input to the first two positions of switch 701-12. When the branch test condition is not met (i.e., signal RBDGO=0), then the incremented address from the MICA register 701-14 is selected.
In some instances, as seen herein, it is not possible to test the state of an indicator on the cycle following its formation. For this reason, history registers HR0-HR7, not shown, are provided for register storage of the Group 2 indicators. The states of such stored indicators are selected and tested in a manner similar to that of the other indicators (i.e., mask fields).
Additionally, the unit 701-1 includes a number of indicator circuits, certain ones of these are used to control the operation of certain portions of the processor 700 when the strings being processed by certain types of instructions have been exhausted. These indicator circuits are included in block 701-42 and are set and reset under the control of a field within the microinstruction word of FIG. 6a (i.e., IND6 field). The bits of this field read out from the ECS output register 701-4 are applied to an RMI register 701-38 for decoding by a decoder 701-40. Based upon the state of status indicator signals received from the various processor units (e.g. 714, 720, 722, etc.), the appropriate ones of the auxiliary flip-flops are switched to binary ONE states. The outputs of these flip-flops are applied via the different positions of a 4 position switch 701-44 to the GP3 position of switch 701-26 for testing. The same outputs are applied to a second position of a ZIR switch 701-43 for storage via the ZDO switch 704-340. The ZIR switch 701-43 also receives indicator signals from an indicator register (IR) 701-41. This register is loaded via the RDI lines 18-30 and 32 in response to certain instructions.
The indicator status signals for example include the outputs of the different adder circuits (AL, AXP) of the unit 720. These signals will set different ones of a number of exhaust flag flip-flops designated FE11, FE12, FE13, FE1E, FE2E, FE2 and FE3. The FE1E and FE2E flip-flops are set during any FPOA cycle of any instruction. These flip-flops in turn cause the FE11, FE12 and FE13 flip-flops to be set when the outputs from the AL or AXP adder circuits of unit 720. The setting and resetting of these indicators will be described herein in further detail in connection with the description of operation. However, the exhaust flag flip-flops pertinent to the example given herein are set and reset in accordance with the following Boolean expressions.
Wherein IND6FLD indicates a particular code;
The ZCSBRA switch 701-18 is normally enabled when the branch decision flip-flop RBD was set to a binary ONE in the previous cycle. The first position selects a 13 bit branch address from the current microinstruction applied via the RSCR register 701-20. The branch address enables any one of the locations of the ECS control store to be addressed directly. The second position selects the concatenation of the 6 low order address bits from the current mirosintruction applied via MIC register 701-15 and the 7 upper bits of the branch address from the current microinstruction applied via the RSCR register 701-20. This permits branches within a 64-word page defined by the contents of the MIC register 701-15 (current location+1).
The third position selects the concatenation of 4 low order bits from the RVBO vector branch register, 6 bits from the branch field of the current microinstruction stored in RCSR register and the 3 upper bits of the address stored in the MIC register. This permits 16-way branches. The fourth position selects the concatenation of the 2 low order ZEROS with 4 bits from the vector branch register RVBO with the 4 most significant bits of the branch address field of the current microinstruction and the 3 upper bits of the current address stored in the MIC register. This permits 16-way branches with 3 control store locations between each adjacent pair of destination addresses.
The fifth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register RVB1, with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits branches with 4 possible destinations with 3 control store locations between each adjacent pair of destination addresses.
The sixth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register RVB2 with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits 4-way branches with 3 control store locations between each adjacent pair of destination addresses.
The output of switch 701-12 addresses a specific location within control store 701-2 which causes the read out of a microinstruction word having a format illustrated in FIG. 6b. Referring to that Figure, it is seen that this microinstruction word is coded to include a number of different fields which are used to control the various functional units within processor 700. Only those fields which are related to the present example will be described herein.
CONTROL LOGIC UNIT 704-1
This unit includes the sequence decode logic circuits 704-100 as mentioned whose outputs feed a plurality of I cycle control state flip-flops of block 704-102. These flip-flops in response to signals from the circuits 704-100 as well as microinstruction signals from register 701-4 (DEMR038-40 which correspond to the mem address field MEMADR of FIG. 6b) generate the various required I cycle control states required for the execution of program instructions. It is assumed that block 704-102 also includes gate circuits which generate register hold signals [HOLDE00 which are distributed throughout the processor 700.
As seen from FIG. 3c, the I cycle control state flip-flops receive control input signals via control lines including a line CPSTOP00 from cache unit 750. As explained herein, the state of the CPSTOP00 line determines whether processor operation continues in that when the line is forced to a binary ZERO, the hold or enabling signals for the I cycle control state flip-flops and other storage registers are also forced to ZEROS. The hold signals corresponding to signals [HOLDI00 and [HOLDE00 operate to hold or freeze the state of the processor 700. Since no incrementing of the control store address can take, the ECS control store reads out the same microinstruction word. The signals [HOLDI and [HOLDE are set in accordance with the following Boolean expressions: [HOLDI=CACHE HOLD+TERMB (DREQ-IFDIR)+HOLD REL wherein the state of signal CACHE HOLD corresponds to the state of signal CPSTOP, the states of signals TERMB (DREQ-IF-DIR) are binary ONES during control state FPOA when the cache command specifies an I fetch or direct operation and the signal HOLD REL is a binary ONE until switched to a binary ZERO by the generation of a microprogram release signal; and [HOLD E=]HOLD I.
In accordance with the teachings of the present invention, each of the instructions which comprise the repertoire of the preferred embodiment of the present invention are assigned one of a number of control sequence codes (CCSS) as follows which enable efficient instruction cycle processing. These different classes of hardwired sequences are established to permit the kind of performance desired for the execution of the entire repertoire of instructions listed in Appendix A. The hardwired sequence selected for each instruction is chosen to provide the particular type of performance required for efficient pipeline operation.
The instructions are designated by mnemonics which are listed in an instruction index included in an appendix A. A number of the instructions are described in the publication "Series 60 (Level 66)/6000 MACRO Assembler Program (GMAP)" by Honeywell Information Systems Inc., copyright 1977, order number DD08B, Rev. 0.
The different assignable hardwired sequences operate in the following manner.
HARDWIRED SEQUENCES
LD-SGL SEQ
This hardwired sequence causes the control unit to generate the effective address during a FPOA cycle and to cause the cache unit to execute a read single memory cycle of operation. When indirect addressing is specified, control is transferred to an address preparation microprogram routine. The requested data is loaded into the RDI register at the completion of the cache cycle and is then availabvle for use during the execution cycle.
LD-SGL-DEL SEQ
This 2T hardwired sequence is the same as LD-SGL except that a 1T delay state is entered after the FPOA cycle (FPOA.fwdarw.FDEL.fwdarw.FPOA-NEXT).
LD-SGL-ESC SEQ
Same as LD-SGL sequence except the pipeline is stopped after the current FPOA cycle is completed (escape state is entered).
LD-HWU SEQ
Same as LD-SGL sequence except that bits 00-17 of RDI register are loaded from the cache unit. Memory bits 00-17 and zeros are loaded into RDI.sub.18-35.
LD-HWU-DEL
This 2T hardwired sequence is the same as the LD-HWU sequence except a 1T delay state is entered after state FPOA. The sequence is FPOA.fwdarw.FDEL.fwdarw.-FPOA-NEXT.
LD-HWU-ESC
This sequence is the same as the LD-HWU sequence except the pipeline is stopped after the completion of the current FPOA cycle.
LD/STR-SGL-ESC
This sequence is the same as the LD-SGL-ESC sequence except that in addition to normal read checks, a write check is also performed. This sequence is used for "READ-ALTER-REWRITE" types of operation.
LD/STR-HWU-ESC
This sequence is the same as LD/STR-SGL-ESC sequence except that bits 00-17 of the RDI register are loaded from the cache unit memory bits 00-17 and zeros are loaded in RDI.sub.18-35. LD-DBL SEQ
This sequence causes the control unit to generate the effective address during a FPOA cycle and causes the cache unit to execute a read double memory cycle of operation. The requested data is returned to the RDI register on two consecutive cycles.
LD-DBL-ESC SEQ
This sequence is the same as the DL-DBL sequence except the escape state is entered after the current FPOA cycle is completed.
STR-SGL SEQ
This 2T sequence (FPOA.fwdarw.FSTR) causes the control unit to generate an effective address and causes the cache unit to execute a write single memory cycle (FPOA) of operation. During the second cycle (FSTR) the register to be stored (as selected by the contents of the RRDX-A register) is transferred to the RADO register as follows ZX.fwdarw.ZDO.fwdarw.ZRESB.fwdarw.RADO.
STR-HWU SEQ
This sequence is the same as the STR-SGL sequence except that the cache unit causes a change only in bits 00-17 of a memory location.
STR-DBL SEQ
This 3T sequence (FPOA.fwdarw.FSTR-DBL.fwdarw.FSTR) causes the control unit to generate an effective address and causes the cache unit to execute a write double memory cycle (FPOA control state) of operation. During the second and third cycles the EVEN and ODD data words (as selected by the contents of the RRDX-A register) are sent to the cache unit.
RD-CLR SEQ
The sequence is the same as the LD-SGL sequence except the cache unit causes the memory location to be read and also cleared.
EFF-ADR SEQ
This sequence causes the control unit to load bits 00-17 of the RDI register with an effective address that is generated during a FPOA cycle while bits 18-35 of the RDI register are loaded with zeros.
EFF-ADR-ESC SEQ
This sequence is the same as the EFF-ADR sequence except the pipeline is stopped after the FPOA cycle (Escape state is entered).
TRF SEQ
This sequence causes the control unit to request two four word blocks of instructions (during EPOA and FTRF control states) for the instruction buffer in preparation for a transfer to control or any branch operation.
ESC SEQ
This sequence causes the pipeline to be stopped after the FPOA cycle. No memory cycles are initiated and there is no address preparation performed.
ESC-LD & ESC-STR SEQS
These sequences are the same as ESC and are used for executing testing operations.
ESC-EA SEQ
This sequence causes the control unit to load a temporary register with an address pointer generated during the FPOA cycle. The pipeline is stopped after FPOA.
DEL-STR-SGL SEQ
This 3T sequence (FPOA-FDEL-FESC) causes the control unit to generate an effective address during state FPOA and then switch to a second FDEL state. This allows the cache unit an extra cycle to fetch the data to be stored. At the completion of FDEL, the cache unit is caused to initiate a write single memory cycle of operation and the hardware switches to FESC state. The data to be written is transferred to the RADO register under microprogram.
DEL-STR-DBL SEQ
This sequence is the same as DEL-STR-SGL except the sequence is 3T. The sequence is FPOA.fwdarw.FDEL.fwdarw.FESC. A write double memory cycle is initiated during state FDEL. Data is transferred to the RADO register on the cycles following state FDEL under microprogram control.
EDIT SEQ (EIS)
This sequence is FPOA-EPOP1-FPOP2 followed by FPOP3. There is an escape to microprogram control which following the setting up of registers, tables, etc. required for processing edit operands signals the hardware control circuits to enter state FPOP3.
The remaining EIS sequences can be considered as having states similar to that of the EDIT sequence.
TSXn
This sequence causes the processor 700 to compute the effective address and update the instruction counter. During a second cycle (FTSX1), the updated instruction counter is loaded into the RDI register for subsequent transfer to the specified index register. The computed effective address is loaded into TEAO and the processor 700 transfers control to that location (FPI-INIT).
The hardwired control states used during I cycle processing in accordance with the present invention and a brief description of the operations performed during such control states or cycles are as follows:
As seen from FIG. 3c, signals corresponding to the I cycle control states are applied as inputs to a plurality of control flip-flops of block 704-104, decoder circuits of block 704-106, a number of control logic circuits of block 704-108 and to a plurality of control flag indicator flip-flops of block 704-110. It is also seen that the various indicator flip-flops of block 704-110 also receive microinstruction input signals via lines MEM054-57 from execution control unit 701-4.
As seen from FIG. 3d, signals generated by the hardware control logic circuits 704-108 fall into one of three groups as a function of the units whose operations are being controlled. That is, the groups are instruction buffer control, hardward control and hardware memory control.
In each case, each group of signals are ored together with equivalent signals generated by other sources and then decoded. The other sources correspond to fields within the two different formats of the microinstruction word of FIG. 6a which are loaded into RCSR register 704-112 from the ECS output register 701-4.
One field corresponds to bits 32-83 of one format (large CU) and another field (short CU) corresponds to bits 32-41 of another format. These fields are decoded by a decoder 704-114 into the sets of bits indicated and combined within the decoders 704-116, 704-124, 704-126 and 704-128 as shown. Further decoding is done by the circuits of blocks 704-118, 704-135 and 704-120. The results of decoding such fields are either distributed throughout processor 700 or are stored in an RMEM register 704-130, an RSZ flip-flop 704-132, an FREQDIR flip-flop 704-136 and an FREQCAC flip-flop 704-134.
Additional decoding of the large and short CU fields and signals from the I cycle state circuits of block 704-112 is done via a decoder 704-106 and 704-107. The decoder 704-106 generates control signals for loading different ones of the registers and for enabling various multiplexer/selector switches within the processor 700. The decoder 704-107 operates to generate signals for setting and resetting a pair (RBASB) of base pointer B flip-flops 704-144. Other combinations of these signals are used to set and reset the descriptor number flip-flops of blocks 704-140 and 704-142.
As seen from FIG. 3c, the decoder 704-116 receives a control signal [EXH00 generated by the decoder circuits of block 704-117. These circuits receive signals from the RDESC register 704-140 and signals from the exhaust flip-flops of block 701-1. In accordance with the states of these signals, the circuits force signal [EXH000 to a binary ZERO to inhibit the generation of a cache memory command upon the occurrence of an exhaust condition. The signal [EXH000 is generated in accordance with the following Boolean expression:
The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word. When set to a binary ONE, this indicates that the descriptor being processed is a numeric type.
The different flip-flops of block 704-104 will now be discussed in greater detail. In greater detail, the flip-flop FCHAR provides certain changes in the control of address generation. When the FCHAR flip-flop is set to a binary ONE during the processing of a load type instruction specifying character modification, then the contents of the RDI register is not changed under hardware control. This allows the RDI register to be loaded with data under microprogram control prior to starting the pipeline. Also, if the FCHAR flip-flop is set to a binary ONE during a store type instruction specifying character modification, then the execution address for this instruction is modified under hardware control to point to a unique address of the microinstruction sequence in the ESC control store that is to process this type of instruction.
The flip-flop FDT-FOUR provides additional control on the readout of the address register (ZAR.sub.0-19) of block 704-304. Flip-flop FADR-WD provides additional control for the ZDO switch 704-340. When this flip-flop is set to a binary ONE, then the ZAR position of the ZDO switch is forced to select a word address. The flip-flop FADR-B provides additional control for the ZDO multiplexer switch. When set to a ONE, then the ZAR position of the ZDO switch is forced to select a byte address. The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word. When set to a binary ONE, this indicates that the descriptor being processed is a numeric type. The flip-flop FIG-LEN provides additional control over the loading of registers within the unit 722 (length registers) and over memory operations. When set to a binary ONE, the RXP and PLN registers within unit 722 are not loaded from the RSIR register 704-154 during control states FPOP.
The FINH-ADR flip-flop inhibits the operation of the address preparation unit 704-3. When set to a binary ONE, an address cycle (FPOA/FPOP) consists of adding the contents of a temporary effective address register REA-T+ZERO. The register REA-T will have been loaded with the address prior to doing a FPOA/FPOP cycle. The FABS flip-flop enables the generation of absolute addresses. When set to a binary ONE, a 24-bit absolute address is used. As concerns the flag or indicator flip-flops of block 704-110, flip-flop FID when set to a binary ONE provides an indication that indirect address modification during an instruction is required on the descriptor loaded into the RSIR register.
The FRL flip-flop when set to a binary ONE indicates that the length is specified in a register associated with the instruction loaded into various instruction registers. The three flip-flops FINDA, FINDB and FINDC provide indications used in processing memory type instructions. Flip-flop FINDA is set to a binary ONE when length is specified in a register or when flip-flop FAFI is set to a ONE. Flip-flop FINDB is set to a binary ONE when the descriptor does not include nine bit characters. The flip-flop FINDC is set to a binary ONE when the descriptor does include six bit characters.
The FAFI flip-flop is set to a binary ONE when the processor circuits detect that indicator bit 30 of IR register 701-41 was set to a binary ONE during the execution of an EIS instruction indicative of a mid instruction interrupt (required to adjust pointer and length values because of interrupt). The FTRGP, FTNGO and FTRF-TST flip-flops are set to binary ONES in conjunction with transfer type instructions. More specifically, the FTRGP flip-flop provides a microprogram indication of being set to a binary ONE when the processor circuits detect the read out of a transfer type of instruction during the execution of an execute double (XED) or repeat (RPTS) instruction. The FTNGO flip-flop provides a microprogram indication of being set to a binary ONE when the condition of transfer signalled by the execution control unit 701 was transfer NO GO (i.e., transfer did not take place). The FTRF-TST flip-flop of this group indicates when set to a binary ONE that the previous instruction executed by processor 700 was a transfer type instruction and that the current I cycle is to be executed conditioned upon the presence of a transfer GO (TRGO) signal from control unit 701.
Additionally, the circuits of block 704-110 include a number of flip-flops used in performing indirect addressing operations under hardwired control for other than EIS instructions. These include FIR, FIRT, FIRL and FRI flip-flops which are switched to binary ONES as functions of the different types of indirect address modifications required to be performed. For example, the FRI flip-flop signals a register then indirect address modification and is switched to a binary ONE when a register indirect (RI) indicator is a binary ONE. The FIR flip-flop is switched to a binary ONE when an indirect the register (IR) indicator is a binary ONE. This flip-flop signals the beginning of an indirect then register address modification. the FIRL flip-flop is switched to a binary ONE when an indirect then tally indirect (IT-I) indicator is a binary ONE. This flip-flop signals a last indirect operation. Another flip-flop TSX2 provides an indication used in processing transfer and set index instructions while a STR-CPR flip-flop is used during the processing of store instructions.
As seen from FIG. 3c, the outputs from the control flag flip-flops of block 704-110 are applied as inputs to the branch indicator circuits of block 701-1. Also, output signals from the control flag flip-flops are also applied as inputs to the I cycle flip-flops of block 704-102.
REGISTER SECTION 704-150
As seen from FIG. 3c, the control logic unit 704-1 further includes a register section 704-150. This section contains the basic instruction register (RBIR) 704-152, the secondary instruction register (RSIR) 704-154, a base pointer A register (RBASA) 704-156 used for selecting one of the address registers RAR0 through RAR7 of block 704-304, a read index register A (RRDXA) 704-158 used for selection of index registers included within section 704-5 (not shown) and for selection of outputs from the ZDO multiplexer switch 704-340, a read index A save (RRDXAS) register 704-159, and a descriptor type register (RTYP) 704-160 indicating the type of data characters being pointed to by the descriptor value (e.g. 9-bit, 6-bit, 4-bit). The section 704-150 further includes a 1-bit instruction/EIS descriptor register designated R29 of block 704-162. The state of this bit in conjunction with the contents of the RBAS-A register 704-158 are used to select the particular address register used for address preparation. When register R29 of block 704-162 is set to a binary ZERO, this indicates that none of the address registers of block 704-304 are used during address preparation. The last registers of section 704-150 include the data in register (RDI) of block 704-164 and a read index register B (RRDXB) pointing to registers used by execution unit 714.
As seen from FIG. 3, the RBIR register 704-152 is loaded via a two position switch 740-170 connected to receive signals from the sources indicated (i.e., a switch ZIB-B 704-172 and lines ZDI 0-35). The RSIR register 704-154 similarly receives signals from the ZDI lines and switch 704-172. The RBASA register 704-156 receives signals from the ZDI line 0-2 in addition to a further switch ZBASA of block 704-174. The RRDXA register and RTYP register receive signals from the ZDI lines as well as a switch 704-176 and switch 704-178 as shown. Also, the RRDXA register receives signals from the RRDXAS register 704-159.
The switch 704-172 is a two position switch which receives inputs from the switches ZIB and ZRESB from the cache unit 750 and execution unit 714 respectively. The switch 704-174 is a three input switch which receives two inputs from the execution units 714 and the output of the ZIB switch of cache unit 750.
Switch 704-176 is a four input switch which receives two of its inputs from the execution unit 714 and a single input from cache unit 750. The first position of the ZRDXA switch 704-176 selects the output of a ZRDXM switch 704-185. One position of this switch provides a tag field value from bit positions 5-8, 14-17, and 32-35 of the RBIR register 704-152 and bit positions 32-35 of the RSIR register 704-154 selected from ZIDD switch 704-180 and a two position ZMF switch 740-176.
The second position of switch 704-185 provides a constant value from the output of the ECS output register 704-1 (CCM field 32-34). The signals from the lines ZIDD 27-35 are applied as inputs to control flag flip-flops of block 704-110. The switch 704-178 receives an input from the control store 704-2, an input from cache unit 750 and an input from execution unit 714.
The data input register 704-164 receives a series of input signals from a ZIDD switch 704-180 which connects in series to a ZDIA switch 704-181 whose output provides one input of a further switch 704-182 which directly loads into the RDI register 704-164. The ZDIA switch 704-181 provides a further input to a three input switch 704-183 which receives the other inputs indicated from cache unit 750 and execution unit 714.
The ZIDD switch 704-180 receives an effective address via switch 704-186 from the address preparation unit 704-3 as well as inputs from the RBIR register 704-152, the RSIR register 704-154 and a two position ZMF switch 740-187. The positions 18 through 35 of the REA position of switch 704-180 are derived from the ZDIA switch 704-181 as shown. The ZDIA switch 704-181 receives signals from the ZDI lines 0-35, a constant value generated from the inputs to a first switch position in addition to signals from the output of the ZIDD switch 704-80 and the ZRESB switch in execution unit 714. The switch 704-182 receives the output of the ZDIA switch and signals from the ZDI lines 0-35. The RRDXB register 704-189 is loaded by a three position switch 704-188. The switch receives via a first position signals from a RREG register included in the execution unit, a constant value from control store 701-2 via a second position and signals from the ZIDD switch via a third position.
The section 704-150 further includes a two position switch 704-185 and a scratchpad pointer register 704-186 whose output is used by the AACU 722 to form addresses for access to the scratchpad memory of the EU 714. The first switch position provides a constant value and is selected under hardware control (FPOA.multidot.R29). The second switch position applies as an output the contents of the RBASA register 704-156. This position is selected under both hardware and microprogram control (i.e., FPOA.multidot.R29 or MISCREG field).
It will be appreciated that the required timing signals for operating section 704 as well as other sections of processor 700 and cache unit 750 are provided by centrally located clock circuits. For example, in the preferred embodiment of FIG. 1, the clock circuits are located within the input/output processor 200. Such clock circuits can be considered as conventional in design and can comprise a crystal controlled oscillator and counter circuits. The timing or clocking signals from such clock circuits are distributed in a conventional manner to the various portions of the system of FIG. 1 for synchronized operation.
ADDRESS PREPARATION UNIT 704-3
The address preparation unit 704-3 includes a number of registers and adders. The registers include a number of base registers (i.e., TBASE0 through TBASEB) of block 704-300 used for storing descriptor values of an instruction, a pair of temporary effective address registers (TEA0, TEA1) and a pair of instruction counters (ICBA, ICBB) included within block 704-302 used for addressing the instruction buffer and eight address registers (RAR0 through RAR7) of 704-304 used during address preparation operations. The unit 704-3 also includes an instruction counter 704-310.
The adders include adder 704-312 used to update instruction counter 704-310 via switches 704-311 and 704-314 and a pair of adders 704-320 and 704-322. The adder 704-322 is used to generate an effective address value which is stored in a register 704-342 applied as an input of the control unit 704-1. The effective address is generated from a number of sources which include ZY switch 704-326 whose output is applied via a number of AND gates of block 704-327, selected address registers of block 704-304 or selected temporary address registers TEA0 and TEA1 of block 704-302 applied via another switch 704-328 or the index address signals ZX0-20 from unit 704-5. Additionally, adder 704-322 is used to update the contents of the instruction counter of the cache instruction buffer.
As seen from FIG. 3d, the outputs from adder 704-322 are also applied as an input to the adder 704-320. The adder 704-320 is used to combine base value stored in any one of the temporary base registers TBASE0 through TBASEB with the address signals ACS0S0-19 from adder 704-322. The resulting bits are applied as an input to a further adder network 704-320 which generates a logical address which is applied to the lines ASFA0-36 via an adder 704-321. This adder sums the operand inputs together with the carry inputs from blocks 704-300 and 704-320. The effective address is used to obtain an absolute address when the system is operated in a paged mode. Since this operation is not pertinent to the present invention, it will not be discussed further herein. For further information regarding such address development, reference may be made to U.S. Pat. No. 3,976,978.
The temporary base registers of block 704-300 are loaded via a switch 704-332. The switch receives an input from the execution unit 714 and the output from block 704-300. The execution unit 714 applies further inputs to the registers of block 704-302 via a switch 704-334 as well as to the address registers of block 704-304. An output multiplexer (ZDO) switch 704-340 enables the selection of the various registers within the address preparation unit 704-3 and unit 704-5 for transfer of their contents to the execution unit 714 via lines ZDO 0-35. Also, the ZDO switch 704-340 enables the contents of various ones of the registers and control flip-flops of unit 704-1 to be read out via a fourth position (ZDO-A). The fifth position enables the states of various indicators within the control store circuits of block 701-1 to be selected for examination.
XAQ REGISTER SECTION 704-5 AND DATA ADDRESS OUTPUT SECTION 704-4 FIGS. 3e and 3f
The section 704-5 includes the accumulator RA register 704-50, the quotient QA register 704-52 and the temporary index (RTX) register 704-54 utilized by the control logic unit 704-1. Additionally, it includes a group of eight index (X0-7) registers included within block 704-51. These registers are loaded via the ZRESA bus in execution unit 714. The selection of the register to be loaded is controlled by the contents of the RRDXB register 704-189. It will be noted from FIG. 3f that selection of outputs from the registers of block 704-51 is controlled by the contents of both the RRDXA and RRDXB registers 704-158 and 704-189 respectively. The contents of program visible registers RA, RQ, X0-7 and RTX are read out to the unit 704-3 via a ZXA2 switch 704-56, a ZXOB switch 704-57 and a ZX switch 704-58. From there, the register contents can be transferred to execution unit 714 or to cache unit 750 via the ZDO switch in unit 704-3.
As seen from FIG. 3f, the output of ZXA2 switch 704-56 is applied via an AND gate 704-61 and an OR gate 704-62 in accordance with the contents of RRDA register 704-158.
The selection of outputs from the above mentioned switches are controlled by the contents of the RRDXA register 704-158, the FNUM flip-flop of block 704-104 and the RTYP register 704-160 in addition to bits 55-77 (ZX field). The ZXA2 switch 704-56 provides for the read out of the upper or lower 18 bits of RA and RQ registers 704-50 and 704-52 for address modification. The selected output signals from the ZXA2 switch and the ZXOB switch are applied to the ZX switch together with the RAAU, RTX and RIC register signals as shown.
The ZX switch selects as an output, bits of the RA/RQ/X registers for a 9-bit character string via a first position, X/RA/RQ bits for a 6-bit character string via a second position, RA/RQ/X bits for a 4-bit character string via a third position and X/RA/RQ bits for word type modification.
Positions five, six and seven are used for selecting the contents of the RAAU register, RIC register and RTX register respectively. A further ZXB2 switch 704-59 provides a second path to the unit 714 for read out of the program visible registers via the lines ZEB0-35. A similar path to the unit 728 is provided via the lines ZAQ0-35.
The section 704-4 includes the registers and switches used for transferring commands and data to the cache 750. Such transfer operations normally require at least two cycles, one for sending an address and another for sending the data. Bits 5-8 of a command word are derived from the output of a four position switch 704-40. This switch receives a first constant value via a first position, the contents of a RZN register 704-42 via a second position, a second constant value via a third position and a third constant value via a fourth position.
Bits 1-4 of a command are applied by the circuits of block 704-1 to an OR gate circuit 704-44 together with bits 5-8. The OR gate 704-44 also receives via a ZADO switch 704-46 bits 1-8 of an RADO register 704-48. The RADO register 704-48 is an address and data out register which receives via a first position of a ZADOB switch 704-48 a logical (virtual) address from address preparation unit 704-3 via the lines ASFA0-35 and data output signals from the EU 714 via lines ZRESB0-35. The positions of the ZADOB switch 704-48 is under the control of the FMTD field for small CU format and the RADO field in the case of large CU format.
As seen from the Figure, either the ZZN1-8 bits or the ZADO bits 1-8 are applied as outputs to the RADO/ZADO lines as a function of the state of control signal [RADO-ZADO. Bits 0 and 9 are always binary ONES while bits 10-35 are furnished by the RADO register 704-46.
Additionally, the unit 704-5 of the preferred embodiment includes a four position selector ZREG switch 704-53 which is controlled by the coding of the CCSR field. The output of the ZREG switch is used to load the RREG register 714-42 with constant values or with signals corresponding to bit positions 24-26 of the RBIR register 704-152. On a next cycle, signals corresponding to the contents of RREG register 714-42 are transferred to the RRDXB register 704-189. In the case of instructions which reference CCS codes specifying instructions within the STR-SGL or STR-DBL classes, the same signals are transferred to the RRDXA register 704-158. Further, the contents of RREG register 714-42 may be loaded into RBASA register 704-156 under microprogram control.
EXECUTION UNIT 714-FIG. 3g
The unit 714 includes as major units, addressable temporary register banks 714-10 and 714-12, an arithmetic logic unit (ALU) 714-20, a shifter 714-24 and a scratchpad memory 714-30. Additionally, the unit 714 includes a number of multiposition data selector switches 714-15, 714-17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38 to provide flexibility in selecting operands and output results.
In operation, the operands are selected via the ZOPA switch 714-15 and ZOPB switch 714-17 from one of the registers of the banks 714-12 and 714-10 or from other input lines such as ZEB0-35 or RDI0-35 as shown. The ALU 714-20 and shifter 714-24 performs operations upon the selected operands and the results are selected via the switches 714-24, 714-36 and 714-38 to be applied to the output bus lines ZRESA 0-35 and ZRESB0-35. Similarly, the contents of a scratchpad location selected via the contents of a scratchpad pad buffer 714-32 can be read out via the switches 714-34, 714-36 and 714-38.
The selected output results or other data are thereafter loaded into other registers within processor 700 including the temporary register banks 714-12 and 714-10 or the scratchpad memory 714-30 of execution unit 714.
In greater detail, the sources of operands are identical for both the ZOPA and ZOPB switches 714-15 and 714-17. The selection of switch position for the ZOPA switch and ZOPB switch is under the control of bits 9-12 and bits 13-16 of the microinstruction word. The ALU 714-20 performs logical, decimal or binary operations upon the selected operand data under the control of bits 24-28 of the microinstruction word of FIG. 6a.
The shifter 714-24 is a combinatorial logic network used to align, shift or rotate binary data under microprogram control. The input data signals from the ZSHFOP and ZEIS switches 714-28 and 714-22 can be viewed as being concatenated to form a single double word input. The shifter 714-24 provides a 36-bit output shifted in accordance with the shift count. The ZSHFOP switch 714-28 is controlled by bits 24-25 of the microinstruction word while the shift count is established by the sequence control constant fields (bits 138-143 of the microinstruction word of FIG. 6a which is appropriately selected via the auxiliary arithmetic control unit 722. For the purposes of the present invention, the ALU 714-20 and 714-24 may be considered conventional in design.
The scratchpad memory 714-30 provides a working space for storing various data required for the execution of certain instructions as well as various constants and descriptor values. For example, octal locations 10-15 are used to store an edit instruction table value required for carrying out edit operations. Writing into the scratchpad memory 714-30 involves first loading the RSPB buffer register 714-32 with input data applied via the ZRESB switch 714-38. During a next cycle, the contents of the register 714-32 are written into the location specified by the signals applied to the ZPSPA 0-6 lines by the AACU unit 722. Writing takes place when bit 22 of the microinstruction word (RSP field) is forced to a binary ONE.
As concerns the other switches, as mentioned, the results produced by the unit 714 are provided via the ZALU switch 714-26, the BSPDI switch 714-34, the ZRESA switch 714-36 and the ZRESB switch under microprogram control. The ZALU and ZSPDI switches provide a first level of selection to the ZRESA and ZRESB switches which provide a last level of selection. Since both the ZRESA and ZRESB switches have identical input sources, they can provide the same output data. The selection of ZALU switch data is under control of bits 30-31 (ZALU field) while the selection of ZSPDI data is under control of bit 23 (ZSPDI field). The selection of ZRESA and ZRESB data is under the control of bits 17-18 and bits 19-20 respectively of the microinstruction word of FIG. 6a.
The registers of banks 714-12 and 714-10 are addressed independently by bits 3-5 (TRL field) and bits 6-8 (TRH field) respectively. The first bit in each field specifies whether one of the four registers is to be addressed while the other 2 bits select the register to be addressed.
CHARACTER UNIT 720-FIG. 3h
It is seen that the unit 720 includes a bank of 4 registers 720-10, a number of registers 720-22, 720-24, 720-28, 720-30, 720-42, 720-46, 720-54, 720-63, 720-64, 720-68 and 720-70, conversion logic circuits 720-27, adder networks 720-32 and 720-34, comparator network 720-72 and a number of decoder/detector networks 720-36, 720-38, 720-44, 720-48, 720-50, 720-56, 720-58 and 720-74 interconnected via a number of multiposition selector switches 720-26, 720-40, 720-62, 720-12 through 720-20. The control and selection of such switches and the strobing of the various registers is under the control of a number of flip-flop circuits included in block 720-80 and a pair of zero detector circuits 720-82 and 720-84.
The RCH bank of registers 720-10 are used as operand buffer registers for storing information received from the EU 714 via the ZRESA lines 0-35. A first register (OP1) is used to store the operand specified by descriptor 1 or data sent to unit 728 or unit 722. A second register (OP2) is used to store the operand specified by descriptor 2. Third and fourth registers (TABLE ENTRY 1, TABLE ENTRY 2) are used to store edit insertion table entry values obtained from EU 714.
The RCN1 register 720-28 holds the actual character position data for descriptor 1 which is used to select a character to be selected by ZCU switch 720-12. The RCN2 register 720-30 holds signals designating the character position data of descriptor 2. The contents are used to select a character from switch 720-14.
The ZCU and ZCV switches 720-16 and 720-18 are under the control of the ZCU and ZCV flip-flops of block 720-80. The RCN 1 and RCN 2 registers 720-28 are loaded under the control of the CN1 and CN2 flip-flops of block 720-80 in response to signals generated by decoder 720-56. This is done as a function of the character type (4, 6 or 9-bit characters) defined by the contents of the RTF1 and RTF2 registers 720-42 and 720-46 and the starting character position signals generated by the conversion logic circuits of block 720-27. The circuits of block 720-27 convert signals ZCN0-2 applied via switch 720-26 corresponding to an input character position value into an output character position. For 9-bit characters, there is no conversion necessary (i.e., input character position=output character position).
The two bit RTF1 register 720-42 holds the character type information relative to descriptor 1 while the two bit RTF2 register 720-46 holds the character type information for descriptor 2. The one bit RTF3 register 720-52 holds the character type information for descriptor 3. When descriptor 3 consists of 9-bit characters, the detector 720-50 sets the RTF3 register to a binary ONE. In all other cases, the RTF3 register is set to a binary ZERO. As seen from the Figure, these registers are loaded via switch 720-40.
The five bit RMOP register 720-70 stores the "microoperation" values required for processing an edit instruction while the 4-bit RIF register 720-63 stores the information field (IF) values for such instructions. The 9-bit RCD register 720-64 is used during certain compare instruction operations for storing a first operand value. The 5-bit RTE8 register 720-68 stores the 5 most significant bits of the eighth edit insertion table entry value in response to a load signal generated by decoder 720-74 in response to a load command. The REFILL register 720-22 is used to store signals received from the unit 704-150 via the lines ZIDD 0-8. The RAD register 720-24 stores character position bits received from the unit 704-3 via the lines ASFA34-36.
The indicator flip-flops of block 720-80 store the result of an operation specified by the contents of the RMOP register 720-70. The indicators include a 2-bit MOP indicator A (MOPIA), a 3-bit MOP indicator B (MOPIB) and a 1-bit END indicator. The MOPIA indicators are decoded as follows:
00 go to MOP execute operation
01 go to LOAD MOP operation
10 Test MOPIB
11 N/A.
The MOPIB indicators provide additional status when the MOPIA indicators have the value "10". They are decoded as follows:
000: test the state of a length 1 indicator for underflow (L1UDF set when the output of the AXP adder equals 0 means L1 exhausted) and the state of the CN1 overflow indicator (CN1 OVF).
001: test the state of a length 3 indicator for underflow (L3UDF set when the output of the AL adder equals 0, means L3 exhausted) and the state of a CN3 overflow indicator (CNLOVF) which is set when the output of the AP adder equals 0.
010: test the states of the LIUDF, CN1OVF, L3UDF and CN3OVF indicators.
011: decrement by 1, the length 2 value and test the states of the L3UDF and CN3OVF indicators during a first cycle and test the states of a length 2 underflow indicator (L2UDF) and the CN2OVF indicator during the second cycle.
100: test the states of the L3UDF, CN3OVF, L1UDF and CN1OVF indicators during a first cycle. Transfer the contents of the RAAU register to EU 714, decrement the length 3 value by 1 and increment the CN3 value by one during a second cycle. During a third cycle, test the states of the L3UDF and CN3OVF indicators.
101: load the table entry value.
110: change the table values.
111: N/A.
The END indicator is set to indicate that the operation specified by the MOP value is complete.
THE AUXILIARY ARITHMETIC AND CONTROL UNIT (AACU) 722-FIG. 3i
The AACU 722 includes 3 parallel adder networks 722-2, 722-6 and 722-8 designated herein as a pointer adder network, an exponent adder network and a length adder network respectively. The pointer network 722-2 includes two banks of 4 registers (RP0-RP3 and RP4-RP7) 722-20 and 722-22. Each bank has its own multiposition switch (722-23 and 722-24) for selecting the data to be written therein and a pair of four position output switches for selecting the data to be read therefrom (i.e., switches 722-27, 722-28 and 722-29, 722-30). Additionally, bank 722-20 has a second input switch 722-32 whose output feeds the ZRPA switch 722-23 and provides for the selection of additional input data.
The ZRPC switch 722-32, the ZRPA switch 722-23 and the register bank 722-20 are jointly controlled by either bits 64-68 (ZRPAC field), bits 69-71 (ZRPAC-3 field) or bit 67 (ZRPAC-4 field) depending upon the microinstruction format. The ZRPA switch 722-23 can select one of the outputs from the ZRPC switch 722-32 via a first position, a value for loading a character offset for address modification/loading address register instructions for the character unit 720 via a second position and a character pointer value for a 9-bit character via a third position.
The ZPA switch 722-27 and the ZPB switch 722-28 select data from the RP0-RP3 register bank 722-20 under the control of bits 59-60 (ZPA) and bits 61-62 (ZPB) respectively. The ZRPB switch 722-24 and register bank 722-22 are jointly controlled by a single control field depending upon the type of microinstruction format bits 74-78 (ZRPB-0), bits 69-73 (ZRPB), bits 72-74 (ZRPB-3) or bit 68 (ZRBP-4). The ZRPB switch 722-4 can select the output of adder output switch 722-36 via a first position, an information field from the character unit 720 via a second position, a word or character pointer value for a 9-bit character via a third position and a character pointer value for a 9-bit character via a fourth and a fifth position.
The ZPC switch 722-29 and the ZPD switch 722-30 select data from the RP4-RP7 register bank 722-23 under the control of bits 57-58 (ZPC field) and bits 67-68 (ZPD field) respectively. As seen from FIG. 3, the outputs from the switches 722-27 through 722-30 are applied to the A and B operand switches 722-25 and 722-26. The outputs of these switches are applied to a pointer adder 722-34.
The ZAPA switch 722-25, the ZAPB switch 722-26 and the adder 722-34 are jointly controlled by a single control field bits 79-84 (AP field) or bits 82-83 (AP-3 field) depending upon the microinstruction format. As seen from the Figure, the ZAPA and ZAPB switches 722-25 and 722-26 select the outputs from the ZPA, ZPC, ZPB or ZPD switches or a constant value for application to adder 722-34.
A ZLX switch 722-36, a ZXC switch 722-38, a RSC register 722-40 and a ZRSC switch 722-42 operated under microprogram control are arranged to provide shift counts to the execution unit shifter. The ZSC switch 722-38 can also be used for loading data into the RP0-RP3 register bank 722-20 via the ZRPC and ZRPA switches 722-32 and 722-23 or into the RP4-RP7 register bank 722-23 via the ZRPB switch 722-24.
The selection of ZLX switch positions is controlled by bits 48-49 (ZLX field). The ZSC switch 722-38 is used to select one of the outputs of the ZLX switch 722-38 under the control of bits 50-52 (ZSC field). The RSC register 722-40 is loaded with the right most 6 bits from the output of the ZLX switch 722-38 under the control of bit 47 (RSC field). The two position ZRSC switch 722-42 selects which of two sources is to supply a shift count to the execution unit 714. Bit 84 (ZRSC field) selects either bits 138-143 (CNSTU/L field) or the RSC register 722-40 as a shift count source.
The last group of circuits shown in block 722-2 include a ZAAU switch 722-44 and a RAAU register 722-46 connected to receive the output of switch 722-44. The ZAAU switch 722-44 is used for transferring data to the register 722-46. From there the data is transferred via the section 704-5 to the execution unit 714 on the ZEB lines 0-35.
The inputs of the ZAAU switch 722-44 are selected by bits 50-52 (ZAAU field). The first position applies a 9-bit character output from the character unit 720 via the lines ZOC 0-8. The second and third positions are used for displaying the outputs from the length adder and exponent adders of blocks 722-6 and 722-8. The RAAU register 7-2-46 is loaded from the ZAAU switch 722-44 in response to bit 47 (RAAU field).
As seen from FIG. 3i, the exponent adder network 722-6 includes a single bank of 4 registers (RXPA-RXPD). The bank 722-60 has a multiposition switch 722-62 for selecting the data to be written therein and a pair of four position output switches for selecting data to be read therefrom (i.e., switches 722-64 and 722-66). The ZXP switch 722-62 and the RXPA-RXPD register bank 722-60 are controlled by bits 59-62 (ZXP field), bits 65-66 ZXP-1 field or bits 75-77 (ZXP-3 field).
A first position of the ZXP switch 722-62 is used to load the exponent result into register bank 722-60. The second position is used to store the result from the length adder 722-8. The next or third position is used for storing exponent values received from the character unit 720. Lastly, the fourth position is used for storing numeric scale factor information received from the RSIR lines 24-35.
The ZXPL switch 722-64 and ZXPR switch 722-66 select data from the register bank 722-60 under the control of bits 63-64 (ZXPL field) or bit 64 (ZXPL-1 field) and bits 65-66 (ZXPR field) respectively. The outputs from the switches 722-64 and 722-66 are applied as inputs to an A operand switch 722-68 and B operand switch 722-70 respectively. These switches apply selected inputs to a pair of 12-bit adders (AXP and AXM) of block 722-72 which generate an exponent output value applied to an output ZAXP switch 722-74. A single control field AXP (bits 69-73) controls the operation of the ZXPA switch 722-68, ZXPB switch 722-70, the adders, the ZAXP switch-22-74 and the loading of a RE register 722-76.
One adder AXM is arranged to receive the contents of the RE register 722-76 for providing absolute value when the sign of value generated by the AXP adder is negative (i.e., the AXP sign indicator not shown has control over the ZAXP switch selection).
The ZXPA switch 722-68 can select via a first position the contents of the RE register 722-76 or the output from the ZXPL switch 722-64 via a second position. The ZXPB switch 722-70 can select via a first position, a constant value, via a second position binary floating point exponent signals applied to the RDI lines 0-7, via a third position a numeric scale factor value applied to the RSIR lines 24-35, a fourth position the output from the ZXPR switch 722-66 and via a fifth position the output from the ZLNA switch 722-84.
The third adder network 722-8 for managing operand length data, similar to network 722-6, includes a single bank of 4 registers (RLN1-RLN4). The bank 722-80 has a multiposition switch 722-82 for selecting the data to be written therein and a pair of four position output switches for selecting data to be read therefrom (i.e., switches 722-84 and 722-86). The ZLN switch 722-82 and the RLN1-RLN4 register bank 722-80 are controlled by bits 59-63 (ZLN-1 field), bit 63 (ZLN-2 field) bits 79-81 (ZLN-3 field) or bits 79-83 (ZLN-4 field) depending upon microinstruction format.
The ZLN switch 722-82 applies the output of the length adder as an output via a first position, the output of the ZAXP switch 722-74 via a second position and a length field value from RSER lines 24-35 via a third position. Additionally, it applies a numeric length field value from RSIR lines 30-35 via a fourth position, a shift count value from RDI lines 11-17 via a fifth position and a length value from RCH lines 24-35 via a sixth position as inputs to register bank 722-80.
The ZLNA and ZLNB switches 722-84 and 722-86 select data from the register bank 722-80 under the control of bits 53-54 (ZLNA field) and bits 55-56 (ZLNB field) respectively as inputs to an A operand switch 722-88 and a B operand switch 722-90 respectively.
The outputs of these switches are applied as inputs to a 12-bit length (AL) adder 722-92. The ZALA switch 722-88, the ZALB switch 722-90 and AL adder 722-92 are all controlled by bits 74-78 (AL field). The ZALA switch 722-88 selects as an operand the output of the ZLNA switch via a first position, a constant field via a second position, the output of the ZPC switch via a third position and a numeric length field via a fourth position.
The ZALB switch 722-90 can select as an operand, a constant field via a first position, the output of the ZLNB switch 722-86 via a second position, the output of the ZXPL switch via a third position, a shift count value from RDI lines 11-17 via a fourth position, the output of the ZPC switch via a fifth position, the output of the ZPA switch via a sixth position and bit positions 6 and 7 of the ZPC switch 722-29 via a seventh position.
The unit 722 includes another group of circuits for furnishing a scratchpad address to unit 714. The circuits include a ZSPA switch 722-100, a RSPA register 722-102 and a ZRSPA switch 722-104, each controlled by bits 48-49 (ZSPA field), bit 47 (RSPA field) and bits 50-52 (ZRSPA field) respectively. The ZSPA switch 722-100 can select as an output, bits 91-97 corresponding to a scratchpad address field via a first position and the output of pointer adder 722-34 via a second position.
The ZRSPA switch 722-104 can select as an output, the contents of register 722-102 via a first position, a scratchpad address field via a second position and a descriptor value applied from the RSIR lines 32-35 via a third position and a value from the RSPR register of unit 704-150 via a fourth position. Additionally, the unit 722 includes a pair of registers 722-106 and 722-108 which are loaded with signals corresponding to bit positions 21-23 of RSIR register 704-154. One register is loaded when bit 53 of the microinstruction word of FIG. 6b or the FPOP flip-flop is a binary ONE. The registers are selected for loading in accordance with the states of the RDESC register 704-140 (00 or 10=R1DW; 011=R2DW).
The various control field signals used by the AACU 722 are derived from a decoder 722-110 which receives as inputs, the various microinstruction word bits loaded into a register 722-122.
CACHE UNIT 750-FIG. 4
General Description
The cache unit 750 is divided into five primary sections: a command buffer section 750-1, a control section 750-3, a cache directory section 750-5, a cache storage section 750-7 and an instruction buffer section 750-9.
Command Buffer Section 750-1
The command buffer section 750-1 includes a four word write command buffer 750-100 and a four word read command buffer 750-102 which are addressed via the counters 750-104 and 750-106. The write ZAC buffer 750-100 provides storage for a single ZAC write command while the read ZAC buffer 750-102 provides storage for up to four read ZAC commands.
The processor 700 transfers commands via the RADO/ZADO lines of interface 605 through the first position of a selector switch 750-110. The processor 700 transfers cache command information via the DMEM and DSZ lines through the first position of a selector switch 750-112. The states of these lines are held or stored in a register 750-114. As seen from the Figure, this information is also written into the buffers 750-100 and 750-102.
In addition to the cache command signals, the processor 700 sets a DREQCAC line. The processor 700 sets other control lines (e.g. HOLD-C-CU, CANCEL-C, CACFLUSH, BYPASS-CAC, READ IBUF, READ EVEN) when it wants to have the cache unit 750 perform other types of operations.
The states of the other control lines are decoded by a decoder 750-116 whose output is used to enable the ZAC buffers 750-100 and 750-102. Additionally, the processor 700 transfers zone bit signals for certain types of write commands via the lines DZD0-3. These signals are loaded into a RDZD register 750-132 via a switch 750-134. From there, the contents are applied via a switch 750-136 to a set of byte CBYSEL lines. Additionally, the signals on the DZO lines are applied to the MITS lines via a switch 750-139. Other zone signals (bits 5-8) are loaded into an RC address register 750-140 and thereafter applied to another set of byte CBYSEL select lines via a switch 750-142.
A plurality of busy bit registers 750-120 and 750-122 are used to determine which of the locations in the RZAC buffer 750-102 are available. The states of these registers are decoded via a priority decoder network 750-130 which selects the first available buffer location. The value developed is stored in the register 750-106 and is used as a write address for the read ZAC buffer 750-102. When the cache request involves doing a backing store (MEM memory) fetch (cache miss signaled by the state of signal BSPD), the appropriate busy bit or both busy bits are set in accordance with the number of SIU responses (ARDA signals) which will be generated. The busy bits are set by signals applied to a pair of lines SETBOTHBSY and SETONEBSY from a decoder, not shown, which decodes the particular command resulting in the application of a signal to one of the BSY lines. For example, a read single command (not bypassed) causes two SIU ARDA responses, each response for bringing in a pair of words. Thus, both busy bits are set. In the case of a read single bypass command, there is only one SIU ARDA response. Hence, only one busy bit is set. Resetting of the busy bits takes place in response to the ARDA line via a RSPB register 750-124 which receives signals from the SIU 100 via the RMIFS lines.
In greater detail, the contents of registers 750-120 and 750-122 are set in accordance with the number of ARDA responses as mentioned when a PENBIT signal is a binary ONE (i.e., the pending bit corresponding to the block is not set). The decoder circuit 750-130 decodes the states of the busy bits and sets counter register 750-106 to the appropriate address value specifying the next empty location within read RZAC buffer 750-102.
The same address signals PRACW0-1 are also applied to a second position of the switch 750-139 in the case of read commands. From there, the signals are loaded into a 4-bit MITS register 750-138 and applied to the MITS lines. The main memory 800 operates to return the coded signals to cache unit 750 via the MIFS lines upon transferring the requested pairs of data words of a block. Thereafter, the signals are loaded into a 4-bit RMIFS register 750-125 and then into the RSPB register 750-124 when the control state signal THCFD is a binary ONE. The received value causes the resetting of the appropriate busy bit indications stored in registers 750-120 and 750-122.
It will be noted that the RMIFS bit signals 2 and 3 are used to address read RZAC buffer 750-102 for read out of the appropriate command. Additionally, as explained herein, signals from an out pointer circuit (COUT), not shown, are used to access commands stored in read ZAC buffer 750-102. The busy bit indications stored in registers 750-124 and 750-126 are applied as inputs to the exclusive OR circuits of block 750-132. These circuits are operative to generate output signals indicative of the number of busy bits set. These outputs are in turn applied to different positions of a 4 position selector switch 750-133. By selecting the appropriate position or location, in response to the RMIFS bit signals 2 and 3, the switch 750-133 provides output signal SECRCV whose state determines when the cache unit 750 has received the second pair of words of a block. The SECRCV signal is applied as an input to block 750-3.
The outputs of the write ZAC buffer 750-100 and read ZAC buffer 750-102 are applied to different ones of a group of two position switches 750-150, 750-152, 750-154, 750-156 and 750-158. The output of ZAC buffer switch 750-150 is loaded into a SIU output register 750-174 via the switches 750-170 and 750-172. The output from the ZAC switch 750-152 is loaded into a pair of data register 750-180 via the switches 750-177 and 750-178.
The outputs of switches 750-154 and 750-158 are applied to a further switch 750-160 and stored in a holding register 750-162. The output of switch 750-156 is applied to a decoder 750-166 together with the DMEM outputs of switch 750-160. The other outputs from this switch are applied to a decoder 750-168. Additionally, the output of the switch 750-158 is applied to a decoder 750-164.
The decoder 750-166 decodes the cache commands received from processor 700 via the DMEM0-3 lines and those read out from the buffers 750-100 and 750-102 and generates signals for transferring commands to the cache storage 750-7 and directory 750-5. That is, the cache decoder 750-166 is used to control what information will be written into the cache storage 750-7 from the processor 700. The decoder 750-168 decodes the states of the BYPCAC and DSZ1 signals. It will be noted that the source of these last mentioned signals corresponds to processor 700 or switch 750-154.
The decoder 750-164 decodes the commands read out from the buffers 750-100 and 750-102 and generates signals for transferring commands to MEM memory (backing store) via the SIU 100. That is, the S decoder 750-164 is used to control the sending of information from the command buffers 750-100 and 750-102 to the SIU.
Additionally, the ZPSW switch 750-178 via a first position selects the ZAC command from the processor 700 on the RADO/ZADO lines for transfer to the SIU 100 on the DTS lines via the switch 750-172 or writes the main memory data into cache storage 750-7 via the RDO, RDI data registers 750-180. The second position of the ZPSW switch 750-178 applies the data output of the ZALT switch 750-177 to the DTS lines (ZAC data) or writes the main memory data from the DFS lines into cache storage 750-7 via the RDO, RDI registers 750-180 or transfers the ZAC commands to the processor 700 via the ZDI lines.
The ZACSW2 switch 750-170 is used to transfer a ZAC command (first position) or data from the ZAC buffer to the SIU 100 via the DTS lines (second position).
CONTROL SECTION 750-3
This section includes a number of control state flip-flops which generate signals for sequencing the cache unit 750 through the required cycles of operation for processing the various commands. Additionally, the section includes the necessary logic circuits for generating the required control signals during the required cycles of operation. For the purposes of the present invention, these circuits may be implemented in a conventional manner. Therefore, in order to simplify the description herein, only a brief description and the Boolean expressions will be given for certain control state flip-flops and control logic circuits as required for an understanding of the operation of the present invention.
The control state flip-flops generate a series of timing sequences which control the following data transfer sequences:
(1) processor to cache, SIU (operation to cache and to SIU);
(2) processor to SIU (transfer write data to SIU);
(3) ZACBUF to cache (operation to cache);
(4) ZACBUF to SIU (operation to SIU);
(5) processor to ZACBUF (write data saved in buffer);
(6) SIU to cache, processor (2 words transferred);
(7) SIU to cache, processor (1 word transferred).
The transfers utilize the following flip-flops.
CONTROL STATE FLIP-FLOPS
The OATB flip-flop is the first flip-flop set in a first sequence which enables a transfer information from the SIU 100 to cache 750 and to the processor 750.
The OATB flip-flop is set for one cycle in accordance with the following Boolean expression: ARDA.multidot.DPFS.
The THCFD flip-flop is the next flip-flop set in the first sequence which enables the information received furing cycle OATB from the SIU 100 to be transferred to processor 700 via the ZDI lines. The THCFD flip-flop is set for one cycle in accordance with the following Boolean expression:
The UG COGTH flip-flop when set permits the setting/resetting of a F/F bit, the setting of a pending bit, the setting of RR bits, writing MSA into the address of the directory section and writing data for write-signal command into CACHE memory. It is set and reset in accordance with the following Boolean expressions:
The UGSOGTH flip-flop is the first set in a CPU to SIU sequence. When set, a first data word is put on the DTS lines. It is set for one cycle in accordance with the following Boolean expression:
The CAOPR flip-flop is set in response to the read for an AOPR response. It is set for one cycle in accordance with the following Boolean expressions:
The CPR-FF flip-flop is used for determining when the cache unit will respond to a DREQ-CAC signal from processor 700. When this flip-flop is set to a binary ONE during a previous cycle, the cache unit will not respond to a request except in the cases of PREREAD, INST-F1, INST-F2, LDQUAD, RD-SINGLE or RD-DBL type commands. It is set and reset in accordance with the following Boolean expressions:
The RBPSD flip-flop is used for turning off the processor 700 in the case of HOLD-ON-MISS or BYP-CAC condition. When the data comes back from the SIU 100, this flip-flop is reset except for an INST-F1 cycle. In the case of IF-1, after 4 words have been received from the SIU, this flip-flop is reset. It is set and reset in accordance with the following Boolean expressions:
CONTROL LOGIC SIGNALS
1. The CPSTOP signal is the signal which is used to turn off the processor 700.
2. The CAC-BYS1 signal indicates when the cache unit is busy. CAC-BSY1=OATB+THCFD.
3. The [$F/E-WRT signal is a write enable signal for setting and resetting the full/empty bits.
4. The [$PEN1-WRT signal is a write enable signal for setting the operation pending bits.
5. The [$PEN2-WRT signal is a write enable signal for resetting the pending bits when all data associated with a request has been received from main memory.
6. The RZAC-ALL-BSY signal indicates the busy status of the RZAC buffer established in accordance with the states of the busy bits.
7. The [$RMIFS signal is a write strobe signal which allows the multiport identifier bits to be stored when data or status information is received from main memory. These bits identify which location in the RZAC buffer contains the ZAC word associated with the received data (i.e., the data pertains to which of the several possible outstanding read requests).
8. The ALTSW0-DT signal enables incoming data from main memory to be saved in the RD0 and RD1 registers.
9. The ALTSW2-DT signal enables data from the ZAC buffer to be transferred to the RD0 and RD1 registers.
wherein DS-ALT=DS-11+DS-12+DS-13.
10. The signals OPSW0-DT through OPSW2-DT control the ZDI switch for transfers of data words from cache to processor 700 via the ZDI lines.
11. The signals ZACSW1-LC1 and ZACSW2-LC2 control the switch 750-702 which selects the source address for all cache memory chips. The sources are the processor 700 when receiving commands, the ZAC buffer and the CADR address register.
12. The signal DATA-RECOV enables the processor 700 to recover from a stop condition (e.g. restrobe registers).
DATA-RECOV=THCFD.multidot.(CINST-F1+CRD-SING).multidot.(FMIFS-1.multidot.WD SELO+THCFD.multidot.CRD-DBL (FSMIFS-1.multidot.WDSELO+FMIFS-1.multidot.WDSELO+FMIFS-1.multidot.WDSELO+ CBYP-CAC)+THCFD.multidot.CRD-RMT.
13. The RD-BSY signal establishes when certain state flip-flops are reset.
14. The SSET-IN signal is used to set certain state flip-flops. SSET-IN=RBPSD.multidot.CDBL-FF.multidot.PENBIT-FF.multidot.UGCOGTH.multido t.CAOPR.multidot.CAC-BSY1. [CPR-FF.multidot.CPR-RD.multidot.CINST-F2.multidot.CLD-QUAD.multidot.CRO-S NG.multidot.CRD-DBL].multidot.[CRD-TYP.multidot.RZAC-ALL-BSY].multidot.DREQ -CAC.
15. SEC-RCV=RMIFS-2.multidot.RMIFS-3.multidot.[RBB-00.sym.RBB-01]+RMIFS-2.mult idot.RMIFS-3.multidot.[RBB-10.sym.RBB-11]+RMIFS-2.multidot.RMIFS-3.multidot .[RBB-20.sym.RBB-21]+RMIFS-2.multidot.RMIFS-3.multidot.[RBB-30.sym.RBB-31].
16. The BPSD signal indicates a cache hit condition. ##EQU1## wherein SP-i-00-14 corresponds to the address directory outputs (the saved address bits), F/Ei corresponds to the full/empty bit "i" and PENi corresponds to the pending bit "i".
It will be appreciated that in the above expressions that the symbols
.multidot.denotes an AND operation,
+denotes an OR operation, and
.sym.denotes an Exclusive OR operation.
CACHE DIRECTORY SECTION 750-5
This section includes a 4 level control directory 750-500 and a 4 level set associative address directory 750-502. The directory 750-502 includes 128 columns, each column being divided into 4 levels, 15 bits in length thereby providing space in each column for four blocks. The control directory 750-500 includes 128 10-bit locations, each of which stores a 10-bit word of control information. The control information for each of the blocks includes two round robin (RR) bits, 4 full/empty (F/E) bits and 4 operation pending bits as shown.
The full/empty bits indicate whether a particulate directory address has any significance (i.e., is valid). For a cache hit to occur, the F/E bit must be set to a binary ONE. A binary ZERO indicates the presence of an empty block. The round robin bits provide a count which indicates which block was replaced last. This count is incremented by 1 under the control of the full/empty bits by a counter 750-512 and is used to identify the next block to be replaced. As seen from FIG. 3, this operation takes place when the round robin and full/empty bits are read out into a pair of output registers 750-504 and 750-506. The full/empty bits are also read into a register 750-510 which controls the incrementing of the round robin bits. That is, the round robin bits are used after all the full/empty bits are set to establish which of the full blocks is to be used for new data. The resulting value (ADDRR0-1) is applied as an input to switch 750-518. All of the full/empty bits are reset by an initialize signal. The full/empty bits can be set via a register 750-516. When the processor 700 issues a read request which is a miss, during the state UGCOGTH, a value "1000" is loaded into the register 750-516. This value is written into the control directory 750-500. On the next request, the value "1100" is loaded into the register 750-516 and etc. until all the full/empty bits are set.
The operation pending bits are used to indicate when a particular operation is still outstanding. For example, the pending bits when set indicates that all the read data for a particular block has not been received. Accordingly, during a read operation, when the address directory signals a hit, with the pending bit set, the cache unit 750 halts the operation of processor 700. Hence, no new request is made to main memory.
The network for setting and resetting the operation pending bits includes a 4-bit buffer register 750-520, a block decode register 750-524 and a decoder 750-512. The registers 750-520, during a write cycle of operation, are addressed by the signals PRZACW0-1 via an address register 750-522 and signals MIFS2-3 during a read cycle. The block decode register 750-524 forces different ones of the output signals BKDCOD0-3 to binary ONES under the following conditions: (1) If at least one full/empty bit is a ZERO, when that bit is set to a binary ONE, the corresponding pending bit is set via the decoder 750-512. When all the full/empty bits are set, the next value for the round robin count is encoded and that bit position within the set of four pending bits is set to a binary ONE. A pending bit is reset via the decoder 750-512 only when the cache 750 has received all of the information (i.e., 4 words) from SIU 100. The contents of the registers 750-520 indicate the position of the pending bit to be reset. The pending bits read out from control directory 750-500 are applied as an input to decoder 750-514 for updating as required.
The pending bits are set and reset under the following conditions.
The actual control signals are as listed previously.
The address directory 750-502, as mentioned, contains 128 sets of 4 words, each 15 bits in length. Each 15-bit word corresponds to the address of a 4 word block in the cache storage section 750-7. Whenever, a ZAC command is processed and involves either writing to or reading from cache unit 750, the 15 bits of the block address contained in the ZAC buffers 750-1h0 or 750-102 are compared on a "set basis" with the address contents of the directory 750-502 to determine the presence of a hit or miss condition. More specifically, the directory 750-502 makes its associations on bits 0-14 of the ZAC address for detection of a hit or miss condition. These bits correspond to the address signals applied to either the ZAC 11-18, 20-26 lines or to the ZAD0/RADO: 10-24 lines selected via an input two position ZACSW switch 750-530.
The address of the directory set is defined by a cache address (CADDL0-6) applied via a three position input switch 750-702. This enables the referencing of 4 block addresses which are read out and applied as one input to each of a group of 4 comparator circuits 750-536 through 750-542. Each of the comparator circuits compares its block address with bits 0-14 of the ZAC address. The results generated by the circuits 750-536 through 750-542 are applied to corresponding inputs of a first group of AND gates 750-544 through 750-550 together with corresponding ones of the full/empty bit signals from register 750-506. A second group of AND gates 750-552 through 750-558 combine the outputs from AND gates 750-544 through 750-550 with signals ZEXTBK0-3 indicative of which block is being selected applied via register 750-518.
The AND gates 750-552 through 750-558 provide a group of output block selection signals (i.e., signals CBSEL0-3) which are applied as inputs to a cache storage 750-700 and to a group of directory hit detection circuits of block 750-560. The circuits of block 750-560 include a group of AND gates 750-562 which logically combine signals indicative of the operation pending bits with the block selection signals, the results of which are "ored" by an OR gate 750-564 to provide a directory hit signal on line BPSD. The circuits of block 750-560 force the line BPSD to a binary ONE when the address bits 0-14 match the directoy contents, the corresponding full/empty bit is a binary ONE, and the corresponding pending bit is a binary ZERO. It is assumed there are error conditions.
CACHE STORAGE SECTION 750-7
The section 750-7 includes a storage unit 750-700 having 2048 (2K), 40-bit word locations organized into 128 sets of 4 blocks. The unit is constructed from bipolar chips, conventional in design. The cache storage unit 750-700 is addressed by the 7-bit address CADDL0-6 applied via the switch 750-702. The address is stored in a holding register 750-704. This causes 4 blocks of 4 words to be applied as inputs to a group of 1 of 4 selection switches (not shown). The appropriate block (level) is determined by the states of the block select signals applied to the CBSEL0-3 lines. The signals applied to the CBYSEL0-7 lines via switch 750-708 provide the appropriate selection of even word and odd word bytes. Between words 0, 2 and 1, 3 the byte selection is independent and proceeds as follows:
The signals applied via lines CWSEL0-3 via a decoder 750-706 is used for designating the words. This ensures that the contents of the appropriate bit positions of the group of memory chips which comprise the unit 750-700.
The words of a selected block are applied as inputs to a number of sets of OR (NAND) gates 750-712 through 750-716. Each group of gates select the word of the selected block. The word outputs from the OR gates are applied as inputs to an instruction buffer 750-900 via a second position of a two position switch 750-902 and to the first 4 positions of an output ZDI switch 750-720 for forwarding to processor 700. The fifth position of the switch applies the word contents of registers 750-180 to processor 700 via a ZBP switch 750-902. Lastly, the sixth position of the ZDI switch 750-720 applies the output of the instruction buffer 750-900 via the ZIB lines 0-39.
As seen from the Figure, during a write cycle of operation, the word contents from the register 750-180 are applied as inputs to the unit 750-700.
INSTRUCTION BUFFER SECTION 750-9
This section includes a 16 word instruction buffer 750-700 which receives data inputs from the registers 750-180 via the switch 750-902. As mentioned previously, the outputs from cache storage 750-700 are also written into the buffer 750-700 via the switch 750-902. Control signals and address signals applied via a switch 750-904 are decoded by a decoder 750-906 and are used to set a read address counter 750-908 and a write address counter 750-910 to the appropriate states. The address outputs of the counters are applied via a switch 750-912 and 750-914 to the buffer 750-900 and used to provide the appropriate addresses during read and write cycles of operation.
DESCRIPTION OF OPERATION
With reference to FIGS. 1-9d, the operation of the present invention will now be described in connection with the processing of several different types of instructions having formats illustrated in FIGS. 9a through 9d.
However, before discussing these instructions, reference will first be made to the state diagram of FIG. 7. This diagram illustrates the sequencing of the I cycle control state storage circuits of block 704-102 as a function of the coding of the "CCS" sequence field applied via the lines 704-210. As seen from FIG. 7, the control state FPOA ia a beginning state for processing all instructions.
The FPOA state is entered when the FPOA control state flip-flop of block 704-102 of FIG. 3 switches to a binary ONE. This flip-flop is set to a binary ONE under hardware control in accordance with the following Boolean expression:
That is, the FPOA cycle is entered following an [END cycle when there is no hold condition relating to the pipeline (i.e., signal HOLDI=1), the instruction buffer 750-900 is not empty (i.e., DIBFEMTY=1), it has at least one instruction ready for transfer to processor 700 (i.e., DIBFRDY=1), the previous instruction did not produce a store compare condition (i.e., [STRCPR=1), is not an execute or repeat instruction (i.e., DXEDRPTS=1) and the pipeline has been restarted (i.e., DPIPE1-4=1).
When in control state FPOA, the RBIR register 704-152 stores the instruction op-code as well as the remainder of the instruction word having one of the formats illustrated in FIGS. 9a and 9b. Also, the RSIR register 704-154 stores the same instruction word. In the case of an instruction having the format of FIG. 9a, the RBASA register 704-156 stores the upper three bits of the y field while the RRDX-A register 704-158 stores the td portion of the instruction word TAG field. The R29 flip-flop 704-162 stores the value of the AR bit 29 of the instruction word.
During control state FPOA, the hardware circuits of block 704-101 decode the CCS sequence field read out from the CCS control store 704-200 in response to the 10-bit op-code (bits 18-27) applied via the RBIR register 704-152. It is the coding of the CCS sequence field which establishes what path the processing of the instruction is to follow. Accordingly, the coding of the CCS sequence field determines the types of operations performed during the FPOA and subsequent cycles which complete as much processing of each instruction as possible under hardware control. Examples of the specific operations are set forth in the section "Hardwired Control State Actions" included herein.
Considering the paths in greater detail, it is seen from FIG. 7 that the hardware circuits of block 704-102 sequence from the FPOA state to control state FTRP-NG when a control flag flip-flop FTRF.multidot.TST indicates that the previous instruction was within the transfer class and that the condition for transfer or branching was not met ([TRGO=1). During control state FTRF-NG, the processor hardware circuits generate signals for reinitializing the instruction buffer as a function of the contents of the instruction counter. This enables the discontinuance of that stream of instructions and a change back to the current stream of instructions whose address is indicated by the instruction buffer circuits. The FTRF-NG control state is then followed by one of the cycles FPI-INIT through FWF-IBUF as a function of the coding of the I buffer status lines.
In the case of normal instruction processing, the path followed as a consequence of decoding the CCS sequence field is that labelled FTRF-TST+[TRG0. This path indicates that the previous instruction was not within the transfer class (FTRF-TST=1) or if it was within such class the condition for transfer is going to be met ([TRG0=1). Hence, this path indicates continued processing of a transfer class instruction under hardware control. It will be noted that if the previous instruction was a transfer class instruction (FTRF-TST=1) and if the current instruction is a transfer class instruction (TRF), then the hardware circuits of block 704-102 remain in control state FPOA (i.e., follow path TRF to FTRF-TST).
The point X in FIG. 7 denotes from the coding of the CCS sequence field whether the particular instruction is in the EIS class, the ESC class or TRF.multidot.EA class, the EIS.multidot.ESC.multidot.[EA.multidot.TRF class or the EIS.multidot.ESC.multidot.[EA class. In the case of the EIS class, the coding of CCS sequence field determines how many descriptors are needed for that particular EIS instruction. Each of the EIS instructions has the multiword format illustrated in FIG. 9b and can require up to three descriptors. The CCS fields for all instructions requiring one, two and three descriptors are grouped together within the decoding circuits. Additionally, signals applied via address lines of the instruction buffer circuits of the cache unit 750 are decoded to determine how many descriptor values or words are presently stored in the instruction buffer. These sets of signals are compared and when there are not enough descriptors presently in the I buffer to complete the instruction, then the circuits of block 704-102 switch from FPOA to control state FPIM-EIS. During control state FPIM-EIS, the processor circuits generate signals for conditioning the cache unit 750 to perform an instruction fetch operation for fetching four more words from main memory or backing store which are loaded into the instruction buffer.
Once the required numbers of descriptors have been fetched and the cache unit 750 signals that the instruction buffer is ready (IBUFRDY=1), the hardware circuits of block 704-102 are at point C. If the instruction buffer is not ready (IBUF-RDY=1), the hardware circuits 704-102 switch to control state FWF-DESC wherein the processor 700 waits for the descriptor. When the instruction buffer is ready (IBUFRDY=1), the hardware circuits are again at point C.
It will be noted that all EIS type instructions (CCS codes 110000-111111) follow a path to point C. If the CCS field indicates that the instruction is a bit type EIS instruction (BIT=1), then the hardware circuits 704-102 switch control state (FESC) without performing any FPOP cycles of operation. If the CCS sequence field indicates that the instruction is not within the bit type class (i.e., BIT=1), the hardware circuits 704-102 switch to control state FPOP for one cycle of operation. It will be appreciated that the number of descriptors within the EIS multiword instruction determines the number of FPOP cycles.
In accordance with the teachings of the present invention, a maximum number of descriptors are processed under hardware control before the circuits 704-102 switch to control state FESC enabling control to be transferred to a microprogram routine within the execution control store 701-2. For those EIS multiword instructions which require address preparation on three descriptors, the hardware circuits 704-102 remain in the FPOP control state for executing two cycles during which the processor circuits generate addresses for the first and second descriptors before switching to control state FESC.
It is seen from FIG. 7 that depending upon the type of instruction as defined by control sequence field and the type of address preparation required, address preparation for the different descriptors proceeds until it is determined that address preparation can no longer continue under hardware control. More specifically, during the FPOP cycle, address preparation is performed for descriptors of the classes of instructions which include instruction types NUM2 through MVT conditioned on the fact that the descriptor is not an indirect descriptor (FID=1), that the descriptor does not specify an indirect length (FRL=1) and it is not a Type 6 descriptor (TYP6=1) or address preparation is to be completed under hardware control (FINH-ADR=1) in addition to other unusual situations which cannot be handled under hardware control (i.e., FAFI=1). When the circuits of block 704-104 force signal FINH-ADR to a binary ZERO, this indicates the the address preparation had been completed under microprogram control and therefore does not have to be performed during a FPOP cycle.
The circuits of block 704-110 force signal FAFI to a binary ONE when the address preparation can be accomplished during the FPOP cycle and there are no special conditions such as the occurrence of a mid instruction interrupt.
Lastly, the condition RDESC=00 is defined by the states of flip-flops of block 704-142 and indicates the occurrence of a first FPOP cycle during which the processor circuits prepare the address of the first descriptor.
In the event that there are some special type of conditions presently defined by the function f, the hardware circuits of block 704-102 switch to control state FESC. This enables the transfer of control to routines stored in the ECS control store 701-2 for continuing the processing of the instruction under microprogram control.
Additionally, in accordance with the preferred embodiment of the present invention, the circuits of block 704-102 include flip-flops which provide control states FIDESC and FWF-IDESC for processing under hardware control indirect operand descriptors for EIS instructions.
For a first indirect descriptor, it becomes necessary to hold up completion of the I cycle for a cycle and let the execution unit 714 complete its operation. As soon as the E cycle is completed, the processor circuits under hardware control fetch the indirect descriptor. In greater detail, when the CCS field indicates that the instruction is an EIS instruction and bit 31 of the RSIR register is a binary ONE (see FIG. 9c), this means that the first descriptor of the EIS instruction is an indirect operand.
During control state FPOA, the hardware circuits of block 704-102 hold up completion of the I cycle (i.e., HOLD-I=1) for one cycle. That is, a control flip-flop FPOAID included within block 704-102 is switched to a binary ONE in response to a first clock pulse which forces the [HOLDI00 signal to a binary ZERO. Upon the occurrence of a next clock pulse, the FPOAID flip-flop is reset to a binary ZERO which allows the [HOLDI00 signal to be forced to a binary ONE (see expressions listed under FPOA control state in "Hardwired Control State Actions" section).
For the remaining EIS descriptors, the hardware circuits of block 704-102 do not hold up the completion of any more I cycles following control state FPOA. From FIG. 7, it is seen that the control state FPOP is entered. However, the hardware circuits of block 704-102 immediately switch to control state FIDESC upon detection of an indirect descriptor. This state is followed by a switching to control state FWF-IDESC and a return to control state FPOP completing the processing of a first indirect operand descriptor. These states are repeated for each descriptor word specified by the MF field of the instruction word as having an indirect operand (see FIG. 9b).
Considering instructions other than EIS type instructions, it will be noted from FIG. 7 that when the CCS sequence field indicates that the instruction is within the escape class or within the transfer class and require indirect address modification, the hardware circuits 704-102 immediately switch from control state FPOA to the FESC control state. As mentioned, control is transferred to the appropriate microprogram routines stored in ECS control store 701-2. Thereafter processing of the instruction proceeds under microprogram control. As indicated in FIG. 7, the occurrence of certain microinstruction codes causes the hardware circuits 704-102 to switch to control state FPOP.
The arrangement for transferring control and the conditions under which control is transferred need not be dicussed further herein. However, for further information, reference may be made to the patent applications listed in the introduction. For the purpose of the present invention, it need only be understood that the hardware circuits of block 704-102 passes control to the ECS control store 701-2 for completion of certain types of instructions which cannot executed in a pipeline mode of operation.
The above mentioned instructions include EIS type instructions as well as those instructions in which the hardware circuits of block 704-102 switch to control state FESC during the processing thereof. It will be noted that in accordance with the present invention, the particular coding of the CCS sequence field enables the processor 700 to detect an early point in time whether an instruction can be executed in the pipeline mode of operation.
It can also be seen from FIG. 7 that non-EIS type instructions other than transfer class instructions (TRF=1) which require indirect addressing and are not within the escape class (ESC=1) follow a path which causes the hardware control circuits of block 704-102 to switch to control state FWF-IND. For execute double and repeat instructions, XED or RPT, the hardware control circuits 704-102 switch to control store FESC. Thereafter, indirect address preparation is performed under microprogram control.
In accordance with the preferred embodiment of the present invention, indirect address modification operations for instructions having the format shown in FIG. 9a are performed under hardware control. These include register then indirect (RI), indirect the register (IR) and indirect then tally (IT). Other IT address modification operations requiring other than indirection are performed under microprogram control.
As seen from FIG. 7, when register indirect address modification is required (i.e., the tm field specifies a register than indirect type modification), the hardware control circuits of block 704-102 switch from the FWF-IND control state to the FPOA control state provided that the CCS field indicates that the instruction is not an execute double or repeat instruction (i.e., RI.multidot.XED.multidot.RPTS=1).
The RI address modification is a 2T operation (i.e., FPOA (RI).fwdarw.FWF-INT.fwdarw.FPOA). During control state FPOA, when the tm portion of the instruction word contents of the RSIR register 704-158 indicate RI address modification, the processor circuits inhibit the loading of the CCS field address into the ECS address register 701-10 of FIG. 3b. Also, the processor 700 takes action to fetch from memory the indirect word specified by the effective address resulting under R type modification (i.e., generates a read single memory command as explained herein).
During control state FWF-INT, the processor 700 under hardware control transfers in for the indirect word, having the format shown in FIG. 9d, from cache unit 750 and forces the RI flip-flop of block 704-110 to a binary ONE. The RI flip-flop remains a binary ONE for the duration of the next FPOA control state. This flip-flop is used to force the R29 register 704-162 to a binary ZERO since the indirect word fetched from memory has its AR bit 29 set to a binary ONE (see FIG. 9d).
As seen from FIG. 7, when the tm field of the instruction specifies an indirect then register address indirect modification and the instruction is other than an execute double or repeat (i.e., (IR+FIR).multidot.XED.multidot.RPTS=1), the hardware control circuits of block 704-102 switch from the FWF-IND control state to the FIRT control state. The IR modification is a 3T operation (i.e., FPOA(IR).fwdarw.FWF-IND.fwdarw.FIRT.fwdarw.FPOA). The same operations mentioned in connection with RI modification are carried out during control state FPOA.
During control state FWF-IND, the control state flip-flop FIRT and the FIR flip-flop are forced to binary ONES. This state is followed by control state FIRT during which the original contents of the RRDXA register 704-158 saved in the RRDXAS register 704-159 are transferred to RRDXA register 704-158 where the address modification specified by the indirect word is either of R or IT type. At this point, the development of an effective address is complete (last indirection).
Also, the control flip-flop FIRL is forced to a binary ONE. The FIRL (flip-flop indirect last) flip-flop remains a binary ONE for the duration of the next FPOA control state. Since the operation is not complete, the FIR flip-flop remains at a binary ONE during control state FPOA.
During the next control state FPOA, the FIRL flip-flop forces the R29 register 704-162 and RSIR tag bits 30-31 to binary ZEROS. This completes the I cycle of operation for that instruction. A similar sequence is followed in the case of a non-execute double or repeat instruction requiring an indirect then tally address modification. This is a 3T operation (i.e., FPOA (IT).fwdarw.FWF-IND.fwdarw.FIT-I.fwdarw.FPOA). During control state FWF-IND, in addition to loading the indirect word into the processor registers (i.e., ZDI.fwdarw.RSIR, RDI and RRDX-A, R29), the control state flip-flop FIT-I is forced to a binary ONE and the RRDXAS register 704-159 is forced to ZEROS.
During control state FIT-I, the ZERO contents of RRDXAS register 704-159 are loaded into RRDXA register 704-158. Also, the FIRL flip-flop is foced to a binary ONE. Similar to that described above, the R29 register 704-162 and RSIR tag bits 30-31 are forced to binary ZEROS by the FIRL flip-flop. The "Hardwired Control State Actions" section illustrates the various operations described above in greater detail.
As seen from FIG. 7, non-EIS type instructions which are not within the escape class and do not require generation of an effective address (EIS.multidot.ESC.multidot.EA) follow a path to point XX. These instructions have the format of FIG. 10a and their tm portion of their TAG fields are coded to specify no indirection (i.e., 00 code). As indicated, the tm portion of an instruction is tested for indirection during the FPOA cycle and when indirection is not specified, the control flag [EA is forced to a binary ONE state.
As seen from FIG. 7, the various groups of instructions following this path are those which reference CCS sequence fields coded to specify sequences listed within group A, group B, group C, TRF, STR-SGL, STR-HMU and STR-DBL. Instructions requiring group A sequences as well as those instructions whose processing has reached point B follow the path to point XXX. Point XXX in FIG. 7 indicates the point at which processor 700 has completed the I cycle processing of an instruction and must then fetch the next instruction from the I buffer for processing. Before that can be done, the processor 700 must make certain that the instruction just completed has not placed it in an execute double or repeat loop (i.e., the instruction is not an XED or RPT instruction). If the processor 700 has been placed in a loop, the hardware circuits of block 704-102 switch to control state FXRPT followed by control state FESC. This ensures that the processor 700 does not fetch the next instruction but instead control is transferred to the ECS control store 701-2 wherein the next operation(s) are carried out under microprogram control. More specifically, during control state FXRPT, the processor 700 under hardwired control forces the ECS control store 701-2 to the appropriate address and during control state FESC transfers control from the hardware circuits.
When the CCS sequence field indicates that the instruction is not an execute double or repeat type of instruction and that the control flag STR-CPR is a binary ONE indicating that the instruction buffer must be reloaded because of a store operation, the hardware circuits of block 704-102 switch to control state FPI-INIT. The STR-CPR flag is set to a binary ONE during a cache write operation when the address of the cache command equals the address of the instruction block. During this state, the processor 700 initializes the instruction buffer via the circuits of block 704-128. Thereafter, the hardware circuits of block 704-102 switch to control state FPIM-2 to fetch the next instruction. This state is followed by a return to control state FPOA as shown in FIG. 7.
When the CCS sequence field indicates that the instruction is neither an execute double or repeat instruction and the instruction buffer does not have to be reloaded because of a store compare operation ([STR-CPR=1), the hardware circuits of block 704-102 switch to one of three control states FPIM-1, FPOA and FWF-IBUF as shown. In the case where the instruction buffer is empty (IBUF-EMPTY=1), it switches to control state FPIM-1 to enable the fetching of instructions to fill the instruction buffer. After the instruction buffer has been filled, the hardware circuits of block 704-102 switch to control state FPOA to begin the processing of the next instruction. In the case where the buffer is not empty, (IBUF-EMPTY=1) but is ready for read out of the next instruction (IBUFRDY=1) the hardware circuits of block 704-102 immediately switch back to control state FPOA.
It will be noted from FIG. 7 that in the event the instruction buffer is not in a ready condition (IBUFRDY=1), the hardware circuits of block 704-102 switch to the FWF-IBUF control state and remain in that state until the instruction buffer is ready (IBUF-RDY=1). When it is ready, the hardware circuits of block 704-102 switch to control state FPOA.
It will be noted that instructions which reference CCS fields coded to specify the sequences listed in group B follow the path labelled group B wherein the hardware circuits of block 704-102 switch from control state FPOA to control state FESC. Similarly, instructions which reference CCS fields coded to specify the sequences listed in group C cause the hardware circuits of block 704-102 to switch to control state FDEL followed by control state FESC. In each case, these instructions require operations which cannot be executed by processor 700 under hardware control but which required certain microinstruction routines for completing the processing thereof.
As seen from FIG. 7, the instructions which reference CCS fields coded to specify STR-SGL or STR-HWU sequences are processed under hardware control provided these instructions do not require character address modifications (FCHAR=1). In such cases, the hardware circuits of block 704-102 switch to control state FSTR.
Those instructions which reference CCS field codes specifying an STR-DBL sequence, the hardware circuits of block 704-102 switch from control state FPOA to the FSTR-DBL control state followed by control state FSTR. In the case of each of three types of sequences mentioned, the hardware circuits of block 704-102 follow a path back to point B for fetching the next instruction from the instruction buffer.
In accordance with the preferred embodiment, the path labelled TSXn is followed when the CCS field is coded to specify the TSX instructions within the class. Initially, the path is the same as that followed by instructions within the ESC-EA class. Hence, similar operations in generating an effective address are performed by processor 700 during control state FPOA. Additionally, the instruction counter is updated by being incremented by one.
The hardware circuits of block 704-102 then switch to control state FTSX1. During this state, the updated instruction counter contents are loaded into the RDI register 704-164. The hardware circuits of block 704-102 switch control flag flip-flop FTSX2 to a binary ONE and thereafter switch to control state FPI-INIT. The control flag flip-flop FTSX2 causes the processor 700 to reference effective address generated during control state FPOA and stored in TEA0 during control state FPI-INIT. It will be appreciated that normally,the processor 700 references the address value IC+0+0 during control state FPI-INIT. The hardware circuits of block 704-102 then switch to control state FPIM-2 followed by control state FPOA.
It will be appreciated that FIG. 7 only discloses the hardware operations relative to the I cycle of operation. As mentionwed, the processing of a given instruction is performed to the extent possible under hardware control. Depending upon the class into which an instruction falls as specified by the CCS field establishes the operations performed during the FPOA control state and subsequent control states. As explained herein and as seen from the section, Hardwired Control State Actions, the hardware circuits of block 704-102 as a function of the coding of the CCS sequence field, generates the appropriate type of cache command during control state FPOA. This action as well as the other actions occurring during the control states of FIG. 7 are as indicated in the following section.
HARDWIRED CONTROL STATE ACTIONS SECTION FPOA CONTROL STATE
1.
If FINH-ADR=1 then
[Y(29)+X(RRDX-A)+ADR(29)].fwdarw.ASEA;
[Y(29)+X(RRDX-A)+ADR(29)]+ZBASE.fwdarw.ASFA;
If RSIR.sub.30-31 =00 then 1.fwdarw.EA*;
If RSIR.sub.30-31 .noteq.00 then 0.fwdarw.EA; RBAS-A(29).fwdarw.RSPP;
2.
If FINH-ADR=1 then
[0+0+REA-T].fwdarw.ASEA;
[0+0+REA-T]+ZBASE.fwdarw.ASFA;
1.fwdarw.EA
3. ASEA.fwdarw.REA; ASFA.fwdarw.RADO
[$CACHE-REG=1
4.
If FTRF-TST=1 then 0.fwdarw.FTNGO
5.
If FMSK-29=1 then MASK R29 to 0
If FIRL=1 then MASK RSIR 30, 31 to 00 0.fwdarw.FIR
0.fwdarw.FRI 0.fwdarw.FIRL
6.
If (FTRF-TST.multidot.[TRGO).multidot.TRF.multidot.EA.multidot.EIS=1 and
if EA.multidot.(LD-SGL+LD-HWU+RD-CLR+EFF-ADR+NO-OP) then 1.fwdarw.END; and
if EA.multidot.(STR-SGL+STR-HWU+STR-DBL)=1 then ZREG.fwdarw.RRDX-A; 0.fwdarw.R29; and
if TSXn.multidot.EA=1 then IC+1.fwdarw.IC CCS.fwdarw.CCS-REG; CCS-O.sub.0-1 .fwdarw.RTYP.sub.0-1 and
if EA [DEL-STR-SGL+DEL-STR-DBL+TSXn+INST-GR]+[EA.multidot.ESC]=1 where INST-GR=LD-SGL-ESC+LD-DBL-ESC+LD-HWU-ESC+EFF-ADR-ESC+ESC-EA then 00.fwdarw.RBAS-B
7.
If FTRF-TST.multidot.TRF.multidot.EA=1 then
a. [INIT-IBUF=1;
b. CCS.fwdarw.CCS-REG;
8.
If FTRF-TST.multidot.[TRGO.multidot.EIS
If FREQ-DIR=1 then [HOLD I=1
If FREQ-DIR=1 then RBIR.sub.27-35 .fwdarw.ZIDD.sub.27-35 .fwdarw.R29, RRDX-A, FID, FRL;
If BIT=1 then 01.fwdarw.RTYP.sub.0-1 ;
If MTM-MTR=1 then 00.fwdarw.RTYP.sub.0-1 ;
If BIT.multidot.MTM-MTR=1 then ZIB.fwdarw.RTYP.sub.0-1
RIR.sub.30 .fwdarw.FAFI;
ZIB=RSIR, RBAS-A;
If (NEED-DESC).multidot.(IBUF-RDY)=1 then FTRF-TST=1 then [READ-IBUF/ZIB (CUR)=1 FTRF-TST=1 then [READ-IBUF/ZIB (OPS)=1 CCS.fwdarw.CCS-REG
9.
If FPOA-ID.multidot.RSIR.sub.31 then HOLD-I.fwdarw.1
If FPOA-ID.multidot.RSIR.sub.31 .multidot.[HOLD-E then 1.fwdarw.FPOA-ID;
If FPOA-ID.multidot.[HOLD-E then 0.fwdarw.FPOA-ID
10.
If FTRF-TST=1 and
If [TRGO=1 then Toggle FABUF-ACTV; If XED-RPTS=1 then 1.fwdarw.FTRGP
If [END=1 then [RDI/ZRESB=1
11.
If [TRGO=1 then inhibit IC Strobe; 1.fwdarw.FTNGO
12.
0.fwdarw.FTRF-TST
DMEM AND VALUES GENERATED DURING CONTROL STATE FPOA
[MEM, [SZ for FPOA
If FTRF-TST.multidot.[TRGO=1 then [MEM.fwdarw.None;
If (FTRF-TST+[TRGO).multidot.ESC=1 then [MEM=None;
If (FTRF-TST+[TRGO).multidot.EIS=1 then [MEM=None;
If (FTRF-TST+[TRGO).multidot.ESC.multidot.EIS.multidot.EA=1 then [MEM=Read Single; [SZ=Sgl;
(FTRF-TST+[TRGO).multidot.EA
If ESC-EA+DEL-STR-SGL+TSXn+DEL-STR-DBL+NO-OP=1 then [MEM=None;
If LD-SGL+LD-SGL-ESC+LD-SGL-DEL then FCHAR.multidot.RRDX-A=DU.multidot.DL=1 then [MEM=Read Single; [SZ=Sgl; FCHAR.multidot.RRDX-A=DU=1 then [MEM=Direct; [SZ=HWU; FCHAR.multidot.RRDX-A=DL=1 then [MEM=Direct; [SZ=HWL; FCHAR=1 then [MEM=None
If LD-HWU+LD-HWU-ESC+LD-HWU-DEL=1 then RRDX-A=DU.multidot.DL=1 then [MEM=Read Single; [SZ=HWU RRDX-A=DU=1 then [MEM=Direct; [SZ=HWU RRDX-A=DL=1 then [MEM=Direct; [SZ=ZERO
If STR-SGL=1 then
if FCHAR=1 then [MEM=Write Single; [SZ=Sgl and if FCHAR=1 then [MEM=None
If TRF=1 then
if FTRF-TST.multidot.FABUF-ACTV=1 then [MEM=Inst. Fetch-1; [SZ=B and
if FTRF-TST.multidot.FABUF-ACTV=1 then [MEM=Inst. Fetch-1; [SZ=A and
if FTRF-TST=1 then [MEM=None
If EFF-ADR+EFF-ADR-ESC=1 then [MEM=Direct; [SZ=HWU
If LD-DBL+LD-DBL-ESC+LD-DBL-FP-ESC=1 then [MEM=Read Double
If RD-CLR=1 then [MEM=Read Clear
If STR-DBL=1 then [MEM=Write Double; [SZ=DBL
If STR-HWU=1 then [MEM=Write Single; [SZ=HWU
If LD/STR-SGL-ESC=1 then [MEM=Read Single; [SZ=Sgl; [R/W=1
If LD/STR-HWU-ESC=1 then [MEM=Read Single; [SZ=HWU; [R/W=1
FSTR CONTROL STATE
1. REG(RRDX-A).fwdarw.ZX;
2. [ENAB-ZX-A2=1;
3. ZX, ZX-A2.fwdarw.ZDO;
4. ZRESB.fwdarw.RADO;
5. [END=1.
FSTR-DBL CONTROL STATE
1. REG(RRDX-A).fwdarw.ZX;
2. [ENAB-ZX-A2=1;
3. ZX, ZX-A2.fwdarw.ZDO;
4. ZRESB.fwdarw.RADO;
5. 0010.fwdarw.RRDX-A;
6. 1.fwdarw.R29.
FESC CONTROL STATE
1.
If [DIBUF/PIPE=10+11 or [PIPE=001+100] then [END=1.
2.
If [DIBUF/PIPE=11 or [PIPE=100] then 1.fwdarw.FWF-REL.
FWF-IND CONTROL STATE
ZDI.fwdarw.RDI
If (RI+IR+IT-I)=1 then ZDI.fwdarw.RSIR
ZDI.fwdarw.RRDX-A, R29
If RI.multidot.(DXED-RPTS)=1 then 1.fwdarw.FRI
If (IT-I).multidot. =1 then 0.fwdarw.RRDXAS.sub.0-3
If IR.multidot. =1 then RRDX-A.fwdarw.ZRDXAS.sub.0-3 and 1.fwdarw.FIR.
FIT-I CONTROL STATE
1.
RRDXAS.fwdarw.RRDX-A.sub.0-3
2.
1.fwdarw.FIRL
FIRT CONTROL STATE
1.
If RSIR-31=1 then RRDXAS.fwdarw.RRDX-A and 1.fwdarw.FIRL
FXRPT CONTROL STATE
1. CCS.fwdarw.CCS-REG
FTSX1 CONTROL STATE
1. IC.fwdarw.ZX
2. ZX.fwdarw.ZDO
3. ZRESB.fwdarw.RDI
4.1.fwdarw.FTSX2
FDEL CONTROL STATE
1.
[0+0+REA-T].fwdarw.ASEA; and [0+0+REA-T]+ZBASE.fwdarw.ASFA.
2.
ASEA.fwdarw.REA; ASFA.fwdarw.RADO; and ZBASE.sub.33-35 .fwdarw.RBASE.sub.33-35 ; and
3.
[$CACHE-REG=1.
4.
If DEL-STR-SGL=1 then [MEM=WRITE SGL; [SZ=SGL.
5.
If DEL-STR-DBL=1 then [MEM=WRITE DBL; [SZ=DBL.
6.
If DEL-STR-SGL.multidot.DEL-STR-DBL=1 then [MEM=NONE.
7.
If LD-SGL-DEL+LD-DBL+LD-HWU-DEL=1 then [END.
FPI-INIT CONTROL STATE
1.
If FTSX2=1 then [0+RIC+0].fwdarw.ASEA;
If FTSX2=1 then [0+0+REA-T].fwdarw.ASEA;
ASEA+ZBASE.fwdarw.ASFA.
2.
0.fwdarw.FTSX2
3.
ASEA.fwdarw.REA; ASFA.fwdarw.RADO.
4.
[$CACHE-REG=1.
5.
ASEA.fwdarw.REA-T.
6.
Toggle FABUF-ACTV.
7.
[MEM=INST-FETCH1.
8.
[INIT-IBUF-OPS=1.
FTRF CONTROL STATE
1.
[4+0+REA-T].fwdarw.ASEA and [4+0+REA-T]+ABASE.fwdarw.ASEA.
2.
ASEA.fwdarw.REA; ASFA.fwdarw.RADO (force 00.fwdarw.RADO.sub.32-33).
3.
[$CACHE-REG=1.
4.
RBAS-B.fwdarw.ZBAS-C; O, REA.fwdarw.RDI; 1.fwdarw.FTRF-TST.
5.
ZDI.fwdarw.RBIR, RSIR, RBAS-A, RRDX-A, R29.
6.
[READ-IBUF/ZIB (OPS)=1.
FTRF-NG CONTROL STATE
1.
[0+0+REA-T].fwdarw.ASEA; and
[0+0+REA-T]+ZBASE.fwdarw.ASFA.
2.
[END=1.
FPIM-1 CONTROL STATE
1.
[4+0+REA-T].fwdarw.ASEA and
[4 (forces 00.fwdarw.RADO.sub.32-33)+0+REA-T]+ZBASE.fwdarw.ASFA.
2.
ASEA.fwdarw.REA; ASFA.fwdarw.RADO (force 00.fwdarw.RADO.sub.32-33) and [$CACHE-REG=1.
3.
ASEA.fwdarw.REA-T; and
[MEM=INST-FETCH1; and
RBAS-B.fwdarw.ZBAS-C.
FPIM-2 CONTROL STATE
1.
[4+0+REA-T.fwdarw.ASEA.
2.
ASEA.fwdarw.REA; and ASFA.fwdarw.RADO (force 00.fwdarw.RADO.sub.32-33); and [$CACHE-REG.
3.
If ASFA-C27=1 then ASEA.fwdarw.REA-T; ASFA, ZWS.fwdarw.RIB-VA, RIB-WS; and [MEM=INST-FETCH2; IPTR-CUR-SEL.fwdarw.[SZ; and
If ASFA-C27=1 then [MEM=NONE; and
RBAS-B.fwdarw.ZBAS-C, and
ZDI.fwdarw.RBIR, RSIR, RBAS-A, RRDX-A, R29, and
[READ-IBUF/ZIB=1.
FWF-IBUF CONTROL STATE
1.
If IBUF-RDY=1 then [READ-IBUF/ZIB (CUR), and
ZIB.fwdarw.RBIR, RSIR, RBAS-A, RRDX-A, R29.
FPIM-EIS CONTROL STATE
1.
[4+0+REA-T].fwdarw.ASEA; and
[4+0+REA-T]+ZBASE.fwdarw.ASFA.
2.
ASEA.fwdarw.REA, and ASFA.fwdarw.RADO (force 00.fwdarw.RADO.sub.32-33);
[$CACHE-REG=1.
3.
ASEA.fwdarw.REA-T; and
[MEM=INST-FETCH1; and
RBAS-B.fwdarw.ZBAS-C; ASFA-C27.fwdarw.FEIS-STR-CPR; and
ZIB.fwdarw.RSIR, RBAS-A; and
If BIT.multidot.MTM-MTR=1 then ZIB.fwdarw.RTYP.sub.0-1 ; and
If IBUF-RDY=1 then [READ-IBUF/ZIB, and CCS.fwdarw.CCS-REG.
FWF-DESC CONTROL STATE
1.
If IBUF-RDY=1 then [READ-IBUF/ZIB; and CCS.fwdarw.CCS-REG.
ZIB.fwdarw.RSIR, RBAS-A; and
If BIT.multidot.MTM-MTR=1 then ZIB.fwdarw.RTYP.sub.0-1.
FPOP CONTROL STATE
1.
If FINH-ADR=1 then
[Y(29) EIS+X (RRDX-A, RTYP, FNUM)+ADR (29, RTYP.sub.0)].fwdarw.ASEA;
[Y(29) EIS+X (RRDX-A, RTYP, FNUM)+ADR (29, RTYP.sub.0)]+ZBASE.fwdarw.ASFA.
2.
If FINH-ADR=1 then
[0+0+REA-T].fwdarw.ASEA;
[0+0+REA-T]+ZBASE.fwdarw.ASFA.
3.
If FID=1 then
HOLD-E=1
RSIR.fwdarw.ZIDD
ZIDD.fwdarw.RRDX-A, R29
4.
ASEA.fwdarw.REA; ASFA.fwdarw.RADO;
[$CACHE-REG=1;
If FIG-LEN=1 then ZLN.fwdarw.RLEN
5.
ASEA.fwdarw.REA-T (RDESC);
[FID+FRL+FAFI].fwdarw.FINDA; (TYP=6).multidot.FINH-ADR.fwdarw.FINDC;
TYP=9+FINH-ADR.fwdarw.FINDB; FINDC+[SET-FINDC.fwdarw.DINDC;
FINDA+[SET-FINDA.fwdarw.DINDA;
FINDB+[SET-FINDB.fwdarw.DINDB.
6.
RDESC=00 (First Descriptor)
If FNUM.multidot.EDIT=1 then
RSIR.sub.21-23 .fwdarw.R1DW; RTYP.sub.0-1 .fwdarw.RTF1;
If FIG-LEN=1 then RSIR.sub.24-35 .fwdarw.RXPA, RLN1
If FINH-ADR=1 then ASFA.sub.34-35 .fwdarw.RP4 ASFA.sub.34-35 .fwdarw.RP0 if RSIR21=1 ASFA.sub.34-36 .fwdarw.RP0 if RSIR21=1.
If FNUM.multidot.EDIT=1 then
RSIR.sub.21-23 .fwdarw.R1DW; RTYP.sub.0-1 .fwdarw.RTF1; ASFA.sub.34-36 .fwdarw.RCN1.sub.0-2
RSIR.sub.24-29 .fwdarw.RXPA;
If FIG-LEN=1 then RSIR.sub.30-35 .fwdarw.RLN1
If RSIR.sub.21 =1 then ASFA.sub.34-35 .fwdarw.RP0
If RSIR.sub.21 =1 then ASFA.sub.34-36 .fwdarw.RP0.
If FNUM=1 then
RSIR.sub.24-29 .fwdarw.RXPA; RSIR.sub.21-23 .fwdarw.R1DW; ETYP0(O).fwdarw.RTF1; ASFA.sub.34-36 .fwdarw.RCN1.sub.0-2
If FIG-LEN=1 then RSIR.sub.30-35 .fwdarw.RLN1
If RSIR.sub.21 =1 then ASFA.sub.34-35 .fwdarw.RP0
If RSIR.sub.21 =1 then ASFA.sub.34-36 .fwdarw.RP0.
A. If [FID.multidot.FRL.multidot.FAFI.multidot.(TYP=6+FINH-ADR)]=1 then
1.
0.fwdarw.FINH-ADR, FIG-LEN
2.
If MTM-MTR wherein DREV=MRL+TCTR+SCAN-REV=1 then 1=[READ-IBUF/ZIB; ZIB.fwdarw.RSIR, RBAS-A;
01.fwdarw.RDESC; If TRANC=1 then IR30.fwdarw.FAFI;
If TRANC=1 then RBIR.sub.9-17 .fwdarw.ZIDD.sub.27-35 .fwdarw.R29, RRDX, A, FID, FRL;
If TRANC=1 then ZIB.fwdarw.R29, RRDX-A;
If SCAN.multidot.CMPC.multidot.CMPCT=1 then ZIB.fwdarw.RTYP; If EDIT=1 then 0.fwdarw.FNUM.
3.
If [TCT+SCAN-FWD+MVT+CONV].multidot.[ZLN.sub.24-35 =0+FIG-LEN].multidot.FE11 then MEM=PRE-READ.
4.
If (NUM2+NUM3+EDIT) (ZlN.sub.30-35 =0+FIG-LEN). FE11 then [MEM=PRE-READ.
5.
If MLR (ZLN.sub.24-35 =0+FIG-LEN).multidot.FE11=1 then (TYP=9).multidot.FESCD=1 then [MEM=LD QUAD; 1=[INIT-IBUF; and if (TYP=9.multidot.FESCD=1 then [MEM=PRE-READ.
6.
If (CMPC+CMPCT) (ZLN.sub.24-35 =0+FIG-LEN).multidot.FE11=1 then (TYP=9).multidot.FESCD=1 then [MEM=RDSGL; [SZ=ZONED; (TYP=9.multidot.FESCD=1 then [MEM=PREREAD.
7.
If OTHERWISE=1 then [MEM=NONE.
B. If [FID.multidot.FRL.multidot.FAFI.multidot.(TYP=6+FINH-ADR)]=1 then
1.
[MEM=NONE.
7.
RDESC=01 (Second Descriptor)
If EDIT.multidot.FNUM=1 then RSIR.sub.21-23 .fwdarw.R2DW, RTYP0-1.fwdarw.RTF2; If FINH-ADR and RSIR21=1 then ASFA.sub.34-35 .fwdarw.RP1 RSIR21=1 then ASFA.sub.34-36 .fwdarw.RP1 ASFA.sub.33-35 .fwdarw.RP6.
IF FNUM.multidot.EDIT=1 then RSIR.sub.21-23 .fwdarw.R2DW, RTYP0-1.fwdarw.RTF2; ASFA.sub.34-36 .fwdarw.RCN2.sub.0-2. If FIG-LEN=1 then RSIR.sub.30-35 .fwdarw.RLN2.
If FNUM=1 then RSIR.sub.24-29 .fwdarw.RXPB; RSIR.sub.21-23 .fwdarw.R2DW; RTYP0, (0).fwdarw.RTF2; ASFA.sub.34-36 .fwdarw.RCN2.sub.0-2. If FIG-LEN=1 then RSIR.sub.30-35 .fwdarw.RLN2.
A. If FID.multidot.FRL.multidot.FAFI.multidot.(TYP=6 FINH-ADR)=1 then
1.
0.fwdarw.FINH-ADR, FIG-LEN.
2.
If (NUM3+EDIT)=1 then
RBIR.sub.0-8 .fwdarw.ZIDD.sub.27-35 .fwdarw.R29, RRDX-A, FID, FRL; [READ-IBUF/ZIB (CUR); IR30.fwdarw.FAFI ZIB.fwdarw.RSIR, RBAS-A, RTYP.
3.
If (NUM2+NUM3+EDIT) (ZLN.sub.30-35 =0 +FIG-LEN).multidot.FE21 then [MEM=PRE-READ, 10.fwdarw.RDESC if NUM2+NUM3.
4.
(ZLN.sub.24-35 =0+FIG-LEN).multidot.FE21.
5.
If (CMPC+CMPCT)=1 then [MEM=PRE-RD.
6.
If OTHERWISE=1 then [MEM=NONE.
B. If FID.multidot.FRL.multidot.FAFI(TYP=6+FINH-ADR)=1 then
1.
[MEM=NONE.
8.
RDESC=10 (Third Descriptor)
If FNUM.multidot.EDIT=1 then RSIR.sub.21-23 .fwdarw.R1DW, If RTYP0-1=00=1 then 1.fwdarw.RTF3 If RTYP0=1.noteq.00=1 then 0.fwdarw.RTF3 If FIG-LEN=1 then RSIR.sub.24-35 .fwdarw.RLN1 If FINH-ADR=1 then ASFA.sub.34-35 .fwdarw.RP4; If RSIR.sub.21 =1 then ASFA.sub.34-35 .fwdarw.RP0 If RSIR.sub.21 =1 then ASFA.sub.34-36 .fwdarw.RP0.
If FNUM.multidot.EDIT=1 then RSIR.sub.21-23 .fwdarw.R1DW, If RTYP0-1=00=1 then 1.fwdarw.RTF3 If RTYP0-1=00.noteq.1then 0.fwdarw.RTF3 If FIG-LEN=1 then RSIR.sub.30-35 .fwdarw.RLN1 If RSIR.sub.21 =1 then ASFA.sub.34-35 .fwdarw.RP0 If RSIR.sub.21 =1 then ASFA.sub.34-36 .fwdarw.RP0.
If FNUM=1 then RSIR.sub.21-23 .fwdarw.R1DW; If RTYP0=0=1 then 1.fwdarw.RTF3 If RTYP0.noteq.0=1 then 0.fwdarw.RTF3 If FIG-LEN=1 then RSIR.sub.30-35 .fwdarw.RLN1 If RSIR.sub.21 =1 then ASFA.sub.34-35 .fwdarw.RP0 If RSIR.sub.21 =1 then ASFA.sub.34-36 .fwdarw.RP0.
A. If [FID.multidot.FRL FAFI(TYP=6+FINH-ADR)]=1 then
1.
[MEM=NONE.
B. If [SET-FESC=1 then 1.fwdarw.FESCD.
FIDESC CONTROL STATE
1.
[Y(29)+X(RRDX-A)+ADR(29)].fwdarw.ASEA; [Y(29)+X(RRDX-A)+ADR(29)]+ZBASE.fwdarw.ASFA; ASEA.fwdarw.REA; ASFA.fwdarw.RADO; [CACHE REG=1; If DU+DL=1 then [MEM=READ-SNGL; [SZ=SINGLE); 1=[HOLD-E; 0.fwdarw.FID; RBIR30.fwdarw.FAFI; If RDESC=00 then RBIR.sub.27-35 .fwdarw.ZIDD.fwdarw.R29, RRDX-A, FRL; If RDESC=01 then RBIR.sub.9-17 .fwdarw.ZIDD.fwdarw.R29, RRDXA, FRL; If RDESC=10 then RBIR.sub.0-8 .fwdarw.ZIDD.fwdarw.R29, RRDX-A, FRL.
FWF-IDESC CONTROL STATE
1.
ZDI.fwdarw.RBIR, RBAS-A;
HOLD-E=1
If RDESC=00 and if BIT.multidot.MTM-MTR=1 then ZDI=RTYP
If RDESC=01 and if (SCAN+CMPC+CMPCT)=1 then ZDI.fwdarw.RTYP
If RDESC=10 then ZDI.fwdarw.RTYP.
SYSTEM OPERATION
Now, the operation of the apparatus of the present invention will be described with reference to several different types of instructions. By way of a first example discussed with specific reference to FIG. 8, it is assumed that the instruction buffer contains four instructions which correspond to an add to A (ADA) instruction, a store A (STA) instruction, a load indicator (LDI) instruction and a load A (LDA) instruction. Each of the instructions have the format shown in FIG. 10a. For ease of explanation and the description given above, it will be assumed that the tm portion of the tag field of each of the four instructions does not specify an indirect address operation. Also, it is assumed that the instructions do not specify a direct upper (DU) or direct lower (DL) type of operation.
The operation codes of the ADA, STA, LDI, and LDA instructions in accordance with the preferred embodiment reference locations in the CCS control store 701-2 including CCSS fields having the following codes: 000000, 010000, 000010 and 000000 respectively. This means that the ADA and LDA instructions are included within the LD-SGL class, the STA instruction is included in the STR-SGL class and the LDI instruction is included in the LD-SGL-ESC class. The various control states assumed by the hardware circuits of block 704-102, the operations performed during the I, C and E cycles of operation in executing the four instructions is pipelined fashion is as illustrated in FIG. 8.
Referring to FIG. 8, it is seen that the processor hardware circuits complete I cycle operations. The path taken in FIG. 7 is FPOA.fwdarw.point XXX.fwdarw.FPOA. During the FPOA control state, the processor 700 performs under hardware control indicated operations. That is, it generates an effective address as a function of the contents of R29 register 704-162, RBAS-A register 704-156 and RRDX-A register 704-158. The resulting effective address is loaded into the REA register. It is also added to the base address and thereafter loaded into the RADO register 704-46 of FIG. 3e. Since the tm portion, the instruction tag field does not specify indirection, the control flag EA is forced to a binary ONE. Also, a code (RBIR 24-26) specifying the A register is loaded into RREG register 714-42 of FIG. 3g.
As mentioned, the CCS field referenced by the ADA instruction is coded to specify a LD-SGL sequence. Since the td portion of the tag field of the instruction does not specify a DU or DL operation, the processor circuits of block 704-108 generate a read single command to be issued to cache unit 750 under hardware control.
In greater detail, the generated address corresponding to the descriptor absolute address loaded into the RADO register 704-76 serves as the command address. Additionally, command bits 1-4 and zone bits 5-8 are generated by the circuits 704-118 of FIG. 3c and switch 704-40. These signals are applied through switch 704-40 in place of bits 1-8 from switch 704-46 while bits 0 and 9 are forced to ZEROS. The zone bits 5-8 are set to binary ONES since they are not used for read commands. Command bits 1-4 are converted to a command code of 0111 by the decoder circuits of block 704-118. This command code specifies a memory read quad operation for fetching a 4 word block from main memory 800.
The circuits of block 704-108 in response to the CCS field and control state signals from block 704-102 operate to generate hardware cache memory command control signals [MEM0TB through [MEM3TB. In the case of a cache read single command, the signals [MEM0TB through [MEM3TB correspond to a code of "1000". In accordance with the teachings of the present invention, the circuits of block 704-108 generate the signals [MEM0-TB through [MEM3-TB in accordance with the following Boolean expressions:
These expressions show the relationship between the CCS codes and the command signals applied to the DMEM lines.
Other circuits included within block 704-108 decode the CCS field and generate the [SZ signals which indicate which half of the RDI register 704-164 is to be loaded. The [SZ signals serve as a size indicator providing information as to whether it is a direct upper (DU) or direct lower (DL) operation or single operation. In the case of a read single operation, the [SZ signals are binary ZEROS.
As seen from FIG. 8, the circuits of block 704-106 force the register strobe signals [CACHE-REG and [CCS to binary ONES. The signal [CACHE-REG loads the read single command code into the RMEM register 704-130 while the [CCS signal loads the address of the CCS word applied via the bus 704-204 to be loaded into the ECS address register 701-10 of FIG. 3b. The cache command code stored in RMEM register 704-130 is applied via the decoder circuits of block 704-118 to the DMEM lines while the command word loaded into the RADO register 704-46 is applied to the cache unit 750 via the RADO/ZADO lines. Also, the decoder 704-120 in response to signals [MEM0TB through [MEM3TB forces REQCAC flip-flop 704-134 to a binary ONE. This signals the cache unit 750 of the command. During control state FPOA, the processor under hardware control performs an [END operation wherein it updates the instruction counter and loads the next instruction (STA) into the RBIR, RSIR, RBAS-A, RRBX-A and R29 registers. Also, the hardware circuits of block 704-102 switch back to control state FPOA to begin execution of the STA instruction during the next or second cycle of operation.
The STA instruction requires two cycles for completion. This includes an FPOA cycle and an FSTR cycle. As seen from FIG. 8, the processor 700 carries out operations similar to those described in connection with the first cycle. However, the STA instruction op-code causes the read out of a control word from control store 704-2 which includes a CCS field coded to specify a STR-SGL sequence. Accordingly, the circuits of block 704-108 are operative to force signals [MEM0TB through [MEM3TB to a code of "1100" which specifies a write single operation. Again, the [SZ signals are binary ZEROS. Also, a value specifying the register to be loaded (i.e., A register) via the ZDO lines is transferred to the RRDX-A register 704-158. At the end of the second cycle, the hardware circuits of block 704-102 switch to control state FSTR continuing the I cycle processing for the STA instruction.
As seen from FIG. 8, during the second FPOA cycle, the cache unit 750 executes a cache cycle of operation in parallel with the I cycle operations. Assuming that the data word requested resides in cache store 750-700, the cache unit 750 reads out the requested word and applies it to the ZDI lines. The processor 700 loads the data word into the RDI register 704-164 in response to a strobe signals generated by the decoder of block 704-106. It will be appreciated that when the requested data word does not reside in cache store 750-700, the processor 700 stops its operation until the cache unit 750 fetches the word from main memory 800. Also, during the cache cycle, the processor 700 performs required bounds and access checks in a conventional manner.
As seen from FIG. 8, during the second cycle, the processor 700 also performs an execution cycle which turns out to be an idle cycle. The reason is that during the first cycle, the processor 700 is completing the previous instruction and transfers the CCS address to the ECS address register 701-10. Until this transfer takes place, the processor 700 remains in an idle state. During the idle cycle, the microinstruction word having a format shown in FIG. 6b specified by the CCS address is read out into the ECS output register 701-4. Also, the processor 700 transfers the contents loaded into the RREG register 714-42 to the RRDXB register 704-189. It is the contents of this register which select the register within the execution unit 714 to be operated upon (i.e., for add operation). During the next cycle, the processor 700 completes the execution of the ADA instruction under microprogram control as explained herein.
As seen from FIG. 8, the code value specifying the A register which was previously loaded into the RRDX-A register 704-158 conditions the ZX switch 704-58 to select the contents of the A register 704-50 for storage. That is, the contents of the A register 704-50 are loaded into the RADO register 704-46 via the ZDO switch 704-340 and ZRESB switch 714-38. From FIG. 8, it is seen that processor 700 performs another [END operation wherein it fetches the next instruction (LDI) from the instruction buffer which is loaded into the processor registers. Also, the hardware circuits of block 704-102 switch to control state FPOA at the end of the FSTR cycle. This completes the I cycle processing for the STA instruction.
During the third cycle, the cache unit 750 in response to the cache write single command determines whether the address of the block containing the data word resides in store 750-700. When it does, the cache unit 750 updates the block by writing the data word into store 750-700. Also, as seen from FIG. 8, the cache unit 750 during the fourth cycle forwards a write command to main memory 800 along with the data word applied to the DTS lines via the RADO register, ZAC SW2 switch 750-170 and switch 750-172.
Also, during the third cycle, the processor 700 under microprogram control executes the ADA instruction. That is, the execution unit adder 714-20 of FIG. 3g adds the contents of the A register selected as a function of the RRDXB register contents applied to the ZEB lines to the value read out from memory applied to the RDI lines. The result is transferred to the A register selected as a function of the RRDXB register contents via the ZRESA bus and switch 714-36. This completes the processor's execution of the ADA instruction. As seen from FIG. 8, the microinstruction word specified by the CCS address read out for the STA instruction is transferred to the ECS output register 701-4. Since the processor 700 essentially completes the execution of the STA instruction almost entirely under hardware control, the microinstruction word read out is one specifying no operation as indicated in cycle 4.
During the fourth cycle, the processor 700 begins the I cycle of operation for the LDI instruction. The operation code of the instruction references a CCS word containing a CCS field coded to specify that the instruction is within a LD-SGL-ESC class. This instruction is a 3T instruction which the processor 700 is unable to execute in a pipeline mode of operation. The reason is that EIS instructions during control state FPOA test the value of an indicator bit whose state could be modified during a subsequent E cycle of operation. Hence, the processor 700 ensures that all execution unit instructions which could alter the state of the indicator bit mentioned have been completed. This is done by having the hardware circuits of block 704-102 open the pipeline upon being switched to control state FESC and resume pipeline processing under microprogram control as explained herein.
As seen from FIG. 8, during control state FPOA, the processor 700 executes the same series of operations that were executed during the first cycle. Also, the processor 700 generates a cache read single command for read out of the data word specified by the address portion of the LDI instruction. Assuming that the data word resides in cache, the cache unit 750 is operative during the next cache cycle (cycle 5) to load the RDI register 704-164 with the data word read out of store 750-700.
As previously mentioned, during cycle 4, the cache unit 750 forwards the A register contents to main memory 800 during the cache cycle of operation. Therefore, nothing remains to be done. Hence, no operations are carried out during the E cycle of operation. However, the microinstruction word specified by the CCS address read out in response to the LDI instruction is transferred to the ECS output register 701-4.
As seen from FIG. 8, the hardware circuits of block 704-102 remain in control state FESC until a microinstruction word is read out to ECS output register 701-4 which signals the processor 700 to restart pipeline processing. It is assumed that this occurs during cycle 5. At that time, processor 700 performs an [END operation wherein the LDA instruction is fetched from the I buffer and loaded into the processor's registers.
As mentioned above, during the cache cycle, the indicator data word is loaded into the RDI register 704-164. Also, the microinstruction word containing the start pipeline code is read out from the ECS control store 701-2 into the ECS output register 701-4 during the idle E cycle of cycle 5. As seen from FIG. 8, the execution unit 714 completes its execution of the LDI instruction upon the transfer of the indicator data word into indicator register 701-41 under control of the microinstruction word read out during the idle cycle. In response to this word, the hardware circuits of block 704-102 switch to control state FPOA thereby restarting pipeline operation.
The op-code of the LDA instruction causes a CCS word to be read out from control store 704-2 which contains a CCS code specifying that the LDA instruction is within the LD-SGL class. Since this instruction is in the same class as the ADA instruction, the processor 700 in a pipeline mode of operation executes the same sequences of operations as discussed in connection with the ADA instruction. The only difference in the E cycle wherein a different microinstruction is specified by the CCS address. Accordingly, no further discussion of such instruction is deemed necessary.
From the above, it is seen how the processor 700 carries out its execution of a series of instructions in a pipeline mode of operation. As mentioned, the preferred embodiment of the present invention enables the processor 700 to execute as much of each instruction as possible under hardware control. Moreover, it facilitates the decoding of instructions requiring no cache cycles of operation. These instructions are those within the effective address class (i.e., those following a path to point XX in FIG. 7). For example, when the ADA instruction has a td field specifying a direct upper (DU) or direct lower (DL) operation, (0011 or 0111 code), then the hardware circuits of block 704-102 force signals [MEM0TB through [MEM3TB to a code of "0001". The [SZ signals are forced to a code of either 10 (DU) or 11 (DL).
During control state FPOA, the processor 700 generates an effective address in the same manner as shown in cycle 1. However, since the cache command code specifies a direct memory operation, there is no cache cycle performed by cache unit 750 during cycle 2. That is, during this interval, the effective address contents of the REA register 704-314 are loaded into RDI register 704-164 of FIG. 3c. For a DU operation, bit positions 0-17 of the RDI tegister 704-164 are loaded with the effective address stored in REA register 704-314. In a case of a DL operation, bit positions 18-35 are loaded with the generated effective address. Since there is no cache cycle, no bounds or access checks need be performed. The decoder 704-120 of FIG. 3c does not switch the REQCAC flip-flop 704-134 to a binary ONE in response to a direct code. Therefore, the cache unit 750 does not respond to a cache command code specifying a direct operation and is effectively bypassed. The hardware circuits of blocks 704-108 and 704-124 in response to the CCS code only generate those signals required to transfer the contents of the REA register 704-314 to the RDI register 704-164.
The processor 700 operates to process other instructions within the effective address class in a similar fashion to that described above. Also, the other add, load and store instructions would be processed in a pipeline fashion similar to the ADA, STA and LDA instructions discussed previously.
It will be appreciated that many modifications may be made to the preferred embodiment of the present invention without departing from its teachings.
While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention known, certain changes may be made to the system described without departing from the spirit of the invention as set forth in the appended claims and, in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.
Claims
What is claimed is:
1. A data processing system for performing data manipulations under the control of instructions, said system including buffer storage apparatus, instruction processing apparatus and instruction execution apparatus, said instructions being processed in a pipelined fashion by said instruction processing apparatus during a number of different successive phases of operation to completion, said instruction processing apparatus comprising: a plurality of registers for storing instructions to be processed received from said buffer storage apparatus, each instruction including an operation code having a first number of bits; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to an operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a control sequence code and an address, said control sequence code including a second number of bits which is less than said first number of bits coded for specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said store for storing the word contents of a location specified by said operation code; control sequence decode circuit means coupled to said first control store output register for decoding signals corresponding to said control sequence code; and, hardware control sequencing means coupled to said sequence decode circuit means for generating sequences of control signals in response to said signals for defining the operations to be performed during selected ones of said different successive phases; said first control store being conditioned in response to said signals corresponding to each operation code of an instruction stored in said first register to read out the contents of a predetermined one of said plurality locations into said first control store output register and said decode circuit means in response to said control sequence code conditioning said hardware control sequencing means for generating a predetermined sequence of said control signals for enabling the completion of the operations of as many of said selected ones of said different successive phases under hardwired control before transferring control to said first microinstruction of one of said plurality of execution sequences specified by said address read out from said predetermined location of said first control store.
2. The system of claim 1 wherein said processing apparatus further includes: a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; and an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation.
3. The system of claim 2 wherein said hardware control sequence means further includes: instruction cycle control means connected to said decode circuit means for generating signals corresponding to sequences of control states defining the sequences of operations to be performed by said processing apparatus during said first one of said phases; and, hardware logic decode circuit means coupled to said instruction cycle control means and to said first control store output registers, said cycle control means being conditioned by said decode circuit means to generate signals corresponding to a first predetermined one of said sequences of control states for conditioning said hardward logic decode circuit means to generate said control signals during the cycles of operation defined by the control states of said first predetermined one of said sequences.
4. The system of claim 3 wherein said hardware logic decode circuit means includes circuits for generating signals for causing a next instruction to be fetched from said buffer storage apparatus and loaded into said first one of said plurality of registers.
5. The system of claim 3 wherein certain ones of said instructions have a single word format including an address which can be coded to specify that certain types of indirect address modifications be performed upon the address included therein, said cycle control means being conditioned by said control sequence decode circuit means and signals from said instruction address to generate signals corresponding to a second predetermined one of said sequences of control states for conditioning said hardward logic decode circuit means to generate control signals for conditioning said processing apparatus to perform the specified indirect address modification under hardwired control in response to said control signals.
6. The system of claim 3 wherein certain ones of said instructions have a multiword format including a plurality of addresses, said cycle control means being conditioned by said control sequence decode circuit means and signals from each instruction address to generate signals corresponding to a third predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform those operations required for fetching the different operands specified by each of said plurality of addresses under hardwired control in response to said control signals.
7. The system of claim 6 wherein those operations include operations required for generating an indirect operand address when any one of said instruction addresses is coded to specify an indirect operand address operation.
8. The system of claim 7 wherein each instruction includes at least one address, said different successive phases of processing including an instruction cycle (I cycle) wherein instruction operand addresses are generated, a cache cycle (C cycle) wherein said buffer storage apparatus fetches an operand specified by said instruction address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said processing apparatus and wherein said first one of said phases corresponds to said I cycle.
9. The system of claim 8 wherein said hardward logic decode circuit means includes buffer command decode circuit means, said buffer command decode circuit means being conditioned by said control sequence code and said signals from said cycle control means to generate coded buffer command signals for forwarding to said buffer storage apparatus for fetching said operand specified by said instruction address as required for the execution of said instruction during said C cycle phase of operation.
10. The system of claim 9 wherein said processing apparatus further includes a memory request decoder circuit coupled to said buffer command decode circuit means, said request decoder circuit being only conditioned by certain codings of said buffer command signals to generate a memory request signal for signaling said buffer storage apparatus to perform a C cycle of operation thereby enabling said C cycle of operation to be bypassed in accordance with the coding of said control sequence code.
11. The system of claim 10 wherein said control sequence code indicating an instruction within an effective address class conditions said buffer command decode circuit means to generate command signals specifying a direct memory operation and said request decoder circuit in response to said command signals being inhibited from generating said memory request signal.
12. The system of claim 1 wherein said plurality of locations of said first control store includes a number of different groups of locations, each location containing a control sequence code coded to have the same bit pattern for specifying the same predetermined one of said hardwired sequences of control signals for executing a different instruction of a class of instructions corresponding in number to the number of locations within a corresponding one of said groups associated therewith.
13. The system of claim 12 wherein a number of said different groups of locations contain control sequence codes coded to have bit patterns specifying a number of hardwired control sequences executable within a limited number of cycles of operation whereby said instruction execution by said instruction processing apparatus proceeds primarily under hardwired control.
14. The system of claim 13 wherein said number of hardwired control sequences include a first group of sequences executable within one cycle of operation by said instruction processing apparatus, said first group including a load single sequence of operation during which said buffer storage apparatus is directed to execute a read single memory cycle of operation.
15. The system of claim 13 wherein said number of hardwired control sequences include a second group of sequences executable within two cycles of operation by said instruction processing apparatus, said second group including a load double sequence of operation during which said buffer storage apparatus is directed to execute a read double memory cycle of operation.
16. The system of claim 13 wherein a number of said different groups of locations contain control sequence codes coded to have bit patterns specifying another number of hardwired sequences of control signals requiring more than said limited number cycles of operation.
17. The system of claim 16 wherein said another number of hardwired control sequences of operation include a store double sequence.
18. A data processing system including a microprogrammed data processing unit for performing data manipulations under the control of instructions wherein the processing of each instruction proceeds in a number of different successive phases of operation, said processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code; a first addressable store coupled to a first one of said plurality of registers for receiving signals of the operation code of a next instruction to be processed, said store including a plurality of locations, each for storing a word including at least a multibit control sequence code, said multibit control sequence code consisting of a smaller number of bits than said multibit operation code coded for specifying one of a number of hardwired control sequences, different groups of said locations storing multibit control sequence codes having the same bit pattern; an output register connected to said store for storing the word contents of a location read out in response to said operation code; control sequence decode circuit means coupled to said output register for generating signals resulting from decoding said multibit control sequence code; and, hardwired control sequencing means coupled to said sequence decode circuit means, said hardwired control means being conditioned by said signals from said decode circuit means to generate a predetermined sequence of control signals for defining the series of operations within a number of successive cycles of operation required to be performed for completing the operations of as many of said phases of instruction processing under hardwired control before switching said microprogrammed data processing unit to operate under microprogram control.
19. The data processing system of claim 18 wherein each location of said first control store further includes an address field for identifying a first microinstruction of a different one of a plurality of execution sequences.
20. The system of claim 19 wherein said processing apparatus further includes: a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; and an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation.
21. The system of claim 20 wherein said hardware control sequencing means further includes: instruction cycle control means connected to said decode circuit means for generating signals corresponding to sequences of control states defining the sequences of operations to be performed by said processing apparatus during said first one of said phases; and, hardware logic decode circuit means coupled to said instruction cycle control means and to said first control store output registers, said cycle control means being conditioned by said decode circuit means to generate signals corresponding to a first predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate said control signals during said hardwired cycles of operation defined by the control states of said predetermined sequence.
22. The system of claim 21 wherein said system further includes buffer storage apparatus coupled to said processing unit and wherein said hardware logic decode circuit means includes circuits for generating signals for causing a next instruction to be fetched from said buffer storage apparatus and loaded into said first one of said plurality of registers.
23. The system of claim 21 wherein certain ones of said instructions have a single word format including an address which can be coded to specify that certain types of indirect address modifications be performed upon the address included therein, said cycle control means being conditioned by said control sequence decode circuit means and signals from said instruction address to generate signals corresponding to a second predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform the specified indirect address modification under hardwired control in response to said control signals.
24. The system of claim 21 wherein certain ones of said instructions have a multiword format including a plurality of addresses, said cycle control means being conditioned by said control sequence decode circuit means and signals from each instruction address to generate signals corresponding to a third predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform those operations required for fetching the different operands specified by each of said plurality of addresses under hardwired control in response to said control signals.
25. The system of claim 24 wherein each instruction includes at least one address, said different successive phases of processing including an instruction cycle (I cycle) wherein instruction operand addresses are generated, a cache cycle (C cycle) wherein said buffer storage apparatus fetches an operand specified by said instruction address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said processing apparatus and wherein said first one of said phases corresponding to said I cycle.
26. The system of claim 25 wherein said hardware logic decode circuit means includes buffer command decode circuit means, said buffer command decode circuit means being conditioned by said control sequence code and said signals from said cycle control means to generate coded buffer command signals for forwarding to said buffer storage apparatus for fetching said operand specified by said instruction address as required for the execution of said instruction during said C cycle phase of operation.
27. The system of claim 26 wherein said processing apparatus further includes a memory request decoder circuit coupled to said buffer command decode circuit means, said request decoder circuit being only conditioned by certain codings of said buffer command signals to generate a memory request signal for signaling said buffer storage apparatus to perform a C cycle of operation thereby enabling said C cycle of operation to be bypassed in accordance with the coding of said control sequence code.
28. The system of claim 27 wherein said control sequence code indicating an instruction within an effective address class conditions said buffer command decode circuit means to generate command signals specifying a direct memory operation and said request decoder circuit in response to said command signals being inhibited from generating said memory request signal.
29. The system of claim 28 wherein a number of said different groups of locations contain control sequence codes coded as having bit patterns specifying a number of hardwired control sequences executable within a limited number of cycles of operation whereby said instruction execution by said processing unit proceeds primarily under hardwired control.
30. The system of claim 29 wherein said number of hardwired control sequences include a first group of sequences executable within one cycle of operation, said first group including a load single sequence during which said buffer, storage apparatus is required to execute a read single memory cycle of operation.
31. The system of claim 29 wherein said number of hardwired control sequences include a second group of sequences executable within two cycles of operation by said processing unit, said second group including a load double sequence during which said buffer storage apparatus is directed to execute a read double memory cycle of operation.
32. The system of claim 29 wherein a number of said different groups of locations contain control sequence codes coded to have bit patterns specifying another number of hardwired sequences of control signals requiring more than said limited number cycles of operation.
33. The system of claim 32 wherein said another number of hardwired control sequences include a store double sequence of operation.
34. A data processing system including a cache unit for storing information including data and instructions and a microprogrammed processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different successive phases of operation to completion, said microprogrammed processing unit comprising: a plurality of registers for storing instructions to be processed received from said cache unit, each instruction including an operation code having a first number of bits; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to the operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a control sequence code and an address, said control sequence code including a second number of bits which is less than said first number of bits coded for specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said store for storing the word contents of a location specified by said operation code; a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation; control sequence decode circuit means coupled to said first control store output register for decoding signals corresponding to said control sequence code; and, hardware control sequencing means coupled to said sequence decode circuit means for generating sequences of control signals for defining the operations to be performed during selected ones of said phases of instruction processing; said first control store being conditioned in response to said signals corresponding to each operation code of an instruction stored in said first register to read out the contents of a predetermined one of said plurality locations into said first control store output register and said decode circuit means in response to said control sequence code condtioning said hardware control sequencing means for generating a predetermined sequence of said control signals for enabling the completion of the operations of as many of said selected ones of said different successive phases under hardwired control before transferring control to said one microinstruction of one of said execution sequences of said second control store specified by said address read out from said predetermined location of said first addressable store.
35. The system of claim 34 wherein said hardware control sequence means further includes: instruction cycle control means connected to said decode circuit means for generating signals corresponding to sequences of control states defining the sequences of operations to be performed by said processing unit during said first one of said phases; and, hardware logic decode circuit means coupled to said instruction cycle control means and to said first control store output register, said cycle control means being conditioned by said decode circuit means to generate signals corresponding to a first predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate said control signals during said hardwired cycles of operation defined by the control states of said first predetermined one of said sequences.
36. The system of claim 35 wherein said hardware logic decode circuit means includes circuits for generating signals for causing a next instruction to be fetched from said cache unit apparatus and loaded into said first one of said plurality of registers.
37. The system of claim 35 wherein certain ones of said instructions have a single word format including an address which can be coded to specify that certain types of indirect address modifications be performed upon the address included therein, said cycle control means being conditioned by said control sequence decode circuit means and signals from said instruction address to generate signals corresponding to a second predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform the specified indirect address modification under hardwired control in response to said control signals.
38. The system of claim 37 wherein said those operations include operations required when any one of said addresses is coded to specify an indirect operand address.
39. The system of claim 38 wherein each instruction includes at least one address, said different successive phases of processing including an instruction cycle (I cycle) wherein instruction operand addresses are generated, a cache cycle (C cycle) wherein said cache unit fetches an operand specified by said instruction address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said processing unit and wherein said first one of said phases corresponds to said I cycle.
40. The system of claim 39 wherein said hardware logic decode circuit means includes cache command decode circuit means, said cache command decode circuit means being conditioned by said control sequence code and said signals from said cycle control means to generate coded cache command signals for forwarding to said cache unit for fetching said operand specified by said instruction address as required for the execution of said instruction during said C cycle phase of operation.
41. The method of organizing a microprogrammed processing unit coupled to a cache unit for storing information including data and instructions, each instruction having a multibit operation code, said processing unit for processing instructions in a pipelined fashion wherein each instruction is processed in a number of different successive phases of operation to completion, said microprogrammed processing unit including: a first control store having a plurality of storage locations each for storing an address identifying a first microinstruction of a different one of a plurality of execution sequences to be referenced by the operation code of one of the types of instructions executable by said processing unit and a second control store having a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by one of said operation codes, said method comprising the steps of: storing in each of said plurality of locations of said first control store, an additional multibit control sequence code having a smaller number of bits than said multibit operation code, said multibit control sequence code being coded to specify one of a number of hardwired control sequences; reading out the contents of one of said plurality of locations of said first control store specified by the operation code of an instruction being processed; providing control sequence decode circuit means responsive to the multibit control sequence code contents of said one location to generate signals indicative of one of said hardwired control sequences; and providing hardware control sequencing means conditioned by said signals for generating a predetermined sequence of control signals for completing the operations of as many of said different phases under hardwired control before transferring control to the execution sequence specified by said address contents of said one location.